JP3063956B2 - Associative memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a function for extending the data width for performing a match search to a plurality of words, that is, when a match is detected in a plurality of successive searches, a match as a whole is detected. The present invention relates to an associative memory having a function to be performed.

[0002]

2. Description of the Related Art Conventionally, each digital data is stored in each of a plurality of arranged memory words, search data is inputted, and coincides with all or a predetermined part of the input search data bit pattern. Memory (Associative Me) for searching a memory word in which digital data having a bit pattern to be stored is stored.
memory, content addressable memory; Content A
addressableMemory) has been proposed.

FIG. 1 is a circuit block diagram showing an example of an associative memory.

The associative memory 10 has a large number of memory words 11_1, 11_2, and m-bit memory cells each having m bits as one word and arranged in the horizontal direction in FIG.
, 11_n are provided. Also, the associative memory 1
0 includes a search data register 12 to which one word of search data is input and latched.
And a bit pattern of all or a predetermined part of the search data latched in the memory words 11_1 and 11_
Of the stored data stored in 2,..., 11_n, the bit pattern is compared with the corresponding bit pattern for the corresponding bit pattern, and each memory word 11_1, 11_n is compared.
, 11_n, the corresponding one of the memory words 11_1, 11_2, and the corresponding ones of the matching lines 14_1, 14_2,.
, 11_n and corresponding matching lines 14_1, 14_2,
, 14_n are output with a coincidence signal of logic '1' (here, 5V). Other matching lines 14_1 and 14
,..., 14_n remain at logic '0' (here, 0V).

The matching lines 14_1, 14_2,...
14_n is output to each flag register 15_n.
1, 15_2,..., 15_n. here,
As an example, as shown, each flag register 15_
1, 15_2, ..., 15_n are '0',
It is assumed that '1', '1', '0', ..., '0', '0' are stored. These flag registers 15_1, 1
The signals stored in 5_2,..., 15_n are input to the priority encoder 16. The encode pulse EP is input to the priority encoder 16, and each time the encode pulse EP is input, a flag register (here, a flag register 15_2 and a flag register 15_2) in which a signal of logic "1" is stored in accordance with a predetermined priority order. The address signals AD corresponding to the flag registers having the higher priority among the two registers 15_3) are sequentially output. Here, the lower the suffix, the higher the priority. Therefore, when only one encode pulse EP is input, a memory address corresponding to the flag register 15_2 is output. The address signal AD output from the priority encoder 16 is input to the address decoder 17 as needed. The address decoder 17 decodes the input address signal AD to provide word lines 18_1, 18_2,..., 1 provided corresponding to the respective memory words 11_1, 11_2,.
8_n, one of the word lines corresponding to the input address signal AD (here, word line 18_n).
2) An access signal (here, a signal of logic “1”) is output. As a result, the stored data stored in the memory word 11_2 corresponding to the word line 18_2 to which the access signal has been output is read out to the output register 19.

Next, when another encode pulse EP is input, the address of the memory word 11_3 corresponding to the flag register 15_3 can be obtained.

As described above, the associative memory 10 searches the stored data stored in a large number of memory words 11_1, 11_2,..., 11_n by using all or a predetermined part of the search data. This is a memory configured to obtain an address of a memory word having stored data to be read, and to read out the entire data stored in the memory word as necessary.

In the associative memory having the basic configuration as described above, a technique has been proposed in which the data width to be searched for a match is extended to two or more words.

FIG. 2 is a block diagram showing an example of an associative memory having a data extension function. The components corresponding to the components of the associative memory shown in FIG. 1 are denoted by the same reference numerals as those in FIG. 1, and redundant description of the components will be omitted.

Each of the match lines 14_1, 14_2,... Extending from each memory word 11_1, 11_2,... Is connected to one input terminal of each AND gate 20_1, 20_2,. In addition, each AND gate 20_1, 20_
, Are connected to the respective OR gates 21_2,
Are connected, and one input terminal of each OR gate 21_2, 21_3,... Is connected to the first search control line 22. However, the OR gate corresponding to the top AND gate 20_1 in the figure is omitted, and the first search control line 22 is directly connected to the input terminal of the AND gate 20_1.

The output terminals of the AND gates 20_1, 20_2,... Are connected to the first flag registers 23_1, 23_
The output terminals of the first flag registers 23_1, 23_2,... Are connected to the input terminals of the second flag registers 24_1, 24_2,. Each second flag register 24_1, 24
_2,... Are connected to the priority encoder 16 (not shown in FIG. 2) shown in FIG.
Are connected to the input terminals of the OR gates 21_2, 21_3,... Corresponding to the memory words adjacent to the lower part of FIG.

Each pair of the first and second flag registers 23_1, 24_1, 23_2, 24_2,... Corresponds to each flag register 15_1, 15_1 shown in FIG.
—2,.

The first flag registers 23_1 and 23_
, And the second flag registers 24_1, 24_2,.
, A match result latch signal S1 output to the match result latch control line 25 is input, and the input data input from each data input terminal is latched by the match result latch signal S1. Flag register 23_
, 23_2,..., The input data at the time of rising a of the match result latch signal S1 is latched,
The input data at the time of the falling b of the match result latch signal S1 is latched in the flag registers 24_1, 24_2,.

In the associative memory configured as described above, a match search is performed as follows. Here, as shown, each of the memory words 11_1, 11_
2,11_3,11_4,11_5,11_6 ...
It is assumed that stored data A, B, C, D, C, F,... Are stored.

Here, when each stored data is searched independently, when the search data REF_DATA is inputted and the search is performed, the first search timing signal S is transmitted to the first search control line 22.
2 is output. Here, the search data REF_DATA
Assuming that the data 'B' is input as the data, a match signal of logic '1' is output to the match line 14_2 corresponding to the memory word 11_2 storing the data 'B', and is input to the AND gate 20_2. At the same time, the initial search timing signal S2 is input to the AND gate 20_2 via the OR gate 21_2, so that the AND gate 2
A signal of logic '1' is output from 0_2. At this time, a signal of logic '0' is output to the other matching lines 14_1; 14_3, 14_4,..., And the logic level of '0' is output from the corresponding AND gates 20_1; 20_3, 20_4,. Is output.

The signal of logic '1' output from the AND gate 20_2 is latched by the first flag register 23_2 at the rising edge a of the match result latch signal S1 output to the match result latch control line 25, At the subsequent falling edge b of the matching result latch signal S1, the signal is latched by the second flag register 24_2.

At each timing when the signal of logic '1' is latched in the first flag register 23_2 and the second flag register 24_2, the other first flag register 23_2
_1; 23_3, 23_4,... And other second flag registers 24_1; 24_3, 24_4,.

Thus, each second flag register 2
, Latched by 4_1, 24_2, 24_3,... Are input to the priority encoder 16 shown in FIG.
1_2 address signals AD are obtained.

Next, a case where a search in which the data width is extended is performed will be described. Here, a case will be described in which two-word data consisting of data 'B' and data 'C' expanded to two words is searched.

In this case, a search for data 'B' is first performed in the same manner as described above. Thereby, the memory word 11_
2 and the first and second flag registers 23_2,
24_2, the signal of logic '1' is latched. Next, a search is performed by inputting data “C” as search data REF_DATA. At this time, the first search control line 22 does not output the first search timing signal S2, and the first search control line 22 has a logic “0”. Keep in the state. Search data R
When a search is performed by inputting data “C” as EF_DATA, a match signal of logic “1” is output to match lines 14_3 and 14_5 corresponding to the two memory words 11_3 and 11_5, respectively, but the OR gate 21_3
Since the signal of logic “1” latched in the second flag register 24_2 is input to the
_3 passes through the AND gate 20_3,
And the second flag register 23_3, 24_3 latches a signal of logic '1' indicating coincidence. On the other hand, since the signal of logic '0' latched in the second flag register 24_4 is input to the OR gate 21_5, the match signal of the match line 14_5 is changed to the AND gate 20_5.
And the first and second flag registers 23_5,
In 24_5, a signal of logic '0' indicating mismatch is latched. In this way, a match between two word data consisting of a pair of data 'B' and data 'C' is detected. The coincidence detection of data of three or more words is performed in the same manner.

Although the associative memory shown in FIG. 2 has a data width extending function, data expanded to two words, three words, etc. are stored in adjacent memory words in a predetermined order. If the data to be searched are stored in memory words separated from each other, or are stored in the reverse order, for example, the order of data 'C' and data 'B' However, it is not possible to perform match detection by combining a plurality of data.

FIG. 3 shows an example of a data structure when such a search is required. FIG. 3 shows attributes I,
A data structure is shown in which four data marked II, III, and IV form a set and constitute one data group. To clarify the concept of the data group and the attribute, for example, each data group of each group number 1, 2, 3, 4,... Is data belonging to each individual, and the attribute I
Is the person's name, attribute II is the person's date of birth, attribute I
II indicates an address,...

As described above, each attribute I, II, III, IV
When a search is performed by storing a data group consisting of a plurality of data marked with a in an associative memory, for example, a case of searching for a data group of group number 1 will be described. Search for data 'B' in this order,
In addition to reading out the remaining data 'C' and 'D' of the matching data group, for example, a search for data 'A' and a search for data 'D' are performed to obtain the remaining data 'B' and 'C'.
May be read out, or data 'B' may be searched first and then data 'A' may be searched next.

However, such a search is impossible in the associative memory having the word width expansion function (see FIG. 2). In the associative memory described above, the data 'A'
When the data “B” and the data “B” are searched, the data “A” with the attribute I and the attribute I in the column of the group number 1 shown in FIG.
A distinction is made between a pair of data "B" with I and a pair of data "A" with attribute II and data "B" with attribute III in the column of group number 4. For example, based on the information of the attribute I of 'name' and the attribute II of 'birth date', even if the user tries to know the information of the attributes
In addition, noise other than necessary information is mixed in, for example, a match is detected with the pair of the attribute III and the attribute III.

An associative memory that solves such a problem is as follows:
Proposed by the present applicant (Japanese Patent Application No. 5-2481)
No. 21). Although this is not disclosed, the associative memory according to this proposal will be described below as a related technique.

FIG. 4 is a block diagram showing an example of the associative memory according to the above proposal. The same components as those of the associative memory shown in FIG. 2 are denoted by the same reference numerals as those shown in FIG. 2, and only different points will be described.

Each of the memory words 11_1, 11_2,...
Are attribute storage units 11_1_1 and 11_2 for storing attributes.
_1,... And a data storage unit 11_1_ for storing data
., And each of the memory words 11_1, 11_2,..., Respectively, stores stored data composed of pairs of attributes and data corresponding to each other. Here, as shown, each memory word 1
1_1, 11_2, 11_3, and 11_4 respectively include attribute I data “A”, attribute II data “B”, attribute III data “C”, and attribute IV data belonging to group number 1 shown in FIG. 'D' is stored.
Each of the memory words 11_5, 11_6,... Stores attribute “I” data “C” and attribute II data “F”,. In the search, search data REF_DATA composed of a pair of an attribute and data is input.

Each of the memory words 11_1 and 11_2 has
Data stored there (both attributes and data)
Is a match line 14_ from which a match signal is output when matches with the input search data (both attributes and data).
1, 14_2,..., And attribute match lines 30_1, 30_2,. A circuit for detecting a match of only the attribute or a match of both the attribute and the data is configured in the same manner as a conventional match detection circuit. Since the conventional coincidence detection circuit is a very common technique in the field of associative memory, its illustration and description are omitted here.

There are provided third flag registers 31_1, 31_2,... Corresponding to the respective memory words 11_1, 11_2, and the respective attribute match lines 30_1, 30_2,.
Are the corresponding third flag registers 31_1 and 31_
Extend to the data input terminals 2,. The associative memory has one data line 32_1, 32_2,... For each memory word group including a plurality of memory words storing data belonging to each data group shown in FIG.
Are provided, and the data lines 32_1, 32_2,
. And the output terminals of the second flag registers 24_1, 24_2,.
_2,... Are provided. These first switches 3
.. Are specifically configured using transistors and the like. The same applies to other switches described later. Each of the first switches 33_1, 33_2,...
Are the corresponding third flag registers 31_1 and 31_
When the signal of logic '1' is latched in 2,..., It is cut off when the signal of logic '0' is latched. Each third flag register 31_1, 31_
,... Latch the signals of the corresponding attribute match lines 30_1, 30_2,... At the falling edge b of the match result latch signal S1 output to the match result latch control line 25.

Are provided between the data lines 32_1, 32_2,... And the input terminals of the respective OR gates 21_1, 21_2,..., And the second switches 34_1, 34_2,. 34_1, 34_
.. Indicate the corresponding attribute matching lines 30_1, 30_2,.
Are controlled to be in a conductive state when the signal is logic "1" indicating a match, and to be turned off when the signal is logic "0" indicating a mismatch. The associative memory shown in FIG. 4 is different from the associative memory shown in FIG. 2 in that an OR gate 21_1 is also provided at a stage preceding the AND gate 20_1 corresponding to the uppermost memory word 11_1 shown in the figure.

In the associative memory configured as described above, the match search is performed as follows.

Since the single data search for one word and the first search among a plurality of continuous words are the same as those in the conventional associative memory with a word extension function shown in FIG. Here, the description is omitted, and here, in the first search, the memory word 11 is searched by the search data REF_DATA including the attribute II and the data “B”.
_2, the first and second flag registers 23_
It is assumed that logic '1' is latched in 2,24_2.
At this time, in response to the attribute match, the memory word 11_2
Is output to the attribute match line 30_2 corresponding to the third flag register 3_2.
1_2 is also latched with a signal of logic '1', the corresponding first switch 33_2 is turned on, and the signal of logic '1' stored in the corresponding second flag register 24_2 and representing both the attribute and the data match. A signal is output to data line 32_1. At the same time, the corresponding second switch 3
4_2 is also turned on, but it is useless operation in the first search.

Next, it is assumed that search is performed by inputting search data REF_DATA including attribute IV and data 'D'. At this time, as in the case of the associative memory of FIG. 2, the initial search control line 22 is held at logic '0'. At this time, in response to the attribute match, a signal of logic '1' is output to the attribute match line 30_4 corresponding to the memory word 11_4, whereby the corresponding second switch 34_4 is turned on and output to the data line 32_1. The signal of logic '1' of the second flag register 24_2 corresponding to the memory word 11_2 is input to the AND gate 20_4 via the OR gate 21_4. Therefore, a match between the attribute IV and the data 'D' is detected in the memory word 11_4, a match signal of logic '1' is output to the match line 14_4, and the match result latch output to the match result latch control line 25 is output. According to the signal S1, the signal of logic “1” is latched in the corresponding first and second flag registers 23_4 and 24_4. At this time, the signal of logic “1” output to the attribute match line 30_4 is latched by the corresponding third flag register 31_4, and the corresponding first switch 33
_4 is turned on, and a signal of logic '1' of the second flag register 24_4 is output to the data line 32_1. In the second search, a logic “0” indicating an attribute mismatch is output to the attribute match line 30_2 corresponding to the memory word 11_2, so that the corresponding third flag register 31_2 has “0” in the corresponding third flag register 31_2. Is stored in the memory word 11_
The first switch 33_2 corresponding to No. 2 is turned off.

As a result, the signal of logic "1" of the second flag register 24_4 corresponding to the memory word 11_4 is input to the priority encoder 16 (see FIG. 1), and the address of the memory word 11_4 is obtained. It is known in advance that the attribute IV is stored in the memory word 11_4, and when it is desired to read the data of the attribute III in the same group, for example, subtract 1 from the obtained address to replace the address of the memory word 11_3. Then, the address may be input to the address decoder 17 to read the contents of the memory word 11_3.

On the other hand, at the time of the second search, instead of the search data including the attribute IV and the data 'D', for example, the attribute I
When a search is performed using search data including V and data 'B', the attribute of the memory word 11_4 matches, so that the second switch 34_4 is turned on, and the data line 3
The signal of logic '1' output to 2_1 is taken in, but since the data is different, logic '0' indicating mismatch is output to the match line 14_4, and is output to the first and second flag registers 23_4 and 24_4. Is latched with logic '0' indicating that no match was detected. Also, the attribute does not match for the memory word 11_2 to which the data 'B' matches, so that both the attribute and the data do not match.

As described above, in the associative memory shown in FIG. 4, even in the same group, even if data stored in memory words separated from each other or data is searched in the reverse order of data. , A search can be performed.

Here, the data lines 32_1, 32_2,... In the associative memory shown in FIG. 4 have fixed lengths assuming that the number of data belonging to one group is predetermined. When a fixed-length data line is provided as described above, it is necessary to estimate the maximum number of data belonging to one group and provide a data line having a length corresponding to the maximum number of data. In this case, when a data group is constituted by a smaller number of data than the maximum, a useless memory word is generated. Therefore, it is preferable that the data lines have a variable length according to the number of data belonging to one group.

FIG. 5 is a schematic diagram showing one method for realizing a variable-length data line.

The data line 32 has a plurality of memory words 11_
, 11_2, 11_3,..., And the data line 32 includes switches 40_1, 40_2, 40_3,... Corresponding to the other memory words 11_2, 11_3,. They are connected in series with each other. Each of these switches 40_
, Are the corresponding memory words 11_2, 11_3, 11_4,... And the immediately adjacent memory words 11_1, 11_2, 11_3.
… And between them. Those switches 40_
, 40_3, 40_4,... Every other switch 40_2, 40_4, 40_6,.
1 is turned on by a first switch control signal output to 1,
Every third switch 40_3, 40_7,... Is turned on by a second switch control signal output to the second control line 42, and every eighth switch 40_ among the remaining switches is turned on.
Are turned on by the third switch control signal output to the third control line 43.

The number of data constituting one data group is 2
In the case of, the first switch control signal is output to the first control line 41, so that every other switch 40_2, 40_2
0_4, 40_6,... Are turned on. Thus, each of the two memory words 11_1, 11_2; 11_3, 11_
4; 11 — 5, 11 — 6;. When the number of data constituting one data group is 4, a first switch control signal is output to the first control line 41 and a second switch control signal is output to the second control line 42. . Then, each of the four memory words 1
1_1, 11_2, 11_3, 11_4; 11_5, 1
A data line that is cut every 1_6,... Is formed. Similarly, when the number of data constituting one data group is 8, the first and second switch control signals are output to the first control line 41 and the second control line 42, respectively, and the third
A third switch control signal is output to the control line 43. Thus, each of the eight memory words 11_1,.
8; 11_9,..., A disconnected data line is formed.

According to this method, when the number of data constituting one data group is 2 ⁿ , no space is generated in the memory word, but when the number is other than 2 ⁿ , for example, 3, 5, 9, etc. A memory word will result. A number of switches 40_ are used to prevent the generation of this empty memory word.
.. Can be arbitrarily turned on and off, the number of control lines becomes large, and a control circuit that outputs a switch control signal to those control lines becomes complicated. Therefore, the method shown in FIG. 5 is not suitable for completely arbitrarily controlling the length of the data line.

FIG. 6 is a schematic diagram showing another method for realizing a variable data line.

Data lines 32 extend over a number of memory words.
Extend and are connected in series with each other to the data line 32,
Each of the switches 40_2, 40_3, 40_4 corresponding to each of the other memory words except the topmost memory word
. Are provided in the same manner as in FIG. Each attribute storage unit 11_1_1, 11_2 is stored in each memory word.
_1, 11_3_1,..., And their attribute storage units 11_1_1, 11_2_1, 11_3_1,.
Stores respective attributes I, II, III, and IV shown in FIG. In this example, the attribute storage units 11_1_1,
The attributes stored in 11_2_1, 11_3_1,...
Depending on the attribute I or the other attributes II, III, IV, the corresponding switch is kept off for the attribute I, and the corresponding switch is turned on for the other attributes II, III, IV. It is configured so that With such a configuration, regardless of how many pieces of data make up one data group, or where data groups having different numbers of data are mixed, the data of the attribute I is arranged at the head of each data group. As a result, automatically cut data lines are formed for every sufficient number of memory words.

FIG. 7 is a circuit diagram showing an example of an attribute determination circuit for determining whether the attribute is I or other.

Here, '000' is assigned to the attribute I, and when the attribute stored in the attribute storage unit 11_i_1 is the attribute I ('000'), '0' is output from the OR gate, and therefore, the transistor 40 Is turned off, and the data lines on both sides of the transistor 40 'are electrically disconnected. Attribute storage unit 11_i
When the attribute stored in _1 is an attribute other than the attribute I, “1” is output from the OR gate, the transistor 40 is turned on, and the data lines on both sides of the transistor are connected.

As described above, in the associative memory shown in FIG. 4, the lengths of the data lines 32_1, 32_2,... Can be adjusted according to the number of data constituting one data group. Of course, instead of using the attribute data, the length of the data line may be adjusted by controlling the switch using a dedicated control line.

[0047]

In an associative memory, a reduction in power consumption is required as in other general RAM memories. In a general RAM memory, an address is input and a memory word at that address is accessed. Therefore, a large number of memory words are divided into a large number of blocks, and designated by the address according to the input address. The power consumption is reduced by activating only a block including a memory word.

However, since the associative memory is used to search for a memory word in which search data is input and storage data matching the search data is stored, even if the memory is divided into blocks, Since it is not known whether a match is detected in a word or not, it is necessary to activate all blocks, and power consumption cannot be reduced simply by dividing into blocks.

Japanese Unexamined Patent Publication No. Hei 3-212896 discloses that the associative memory array is divided into a plurality of one-way arrays to form each block, and block selecting means for selecting any one of the blocks is provided. It describes that the current consumption of the associative memory is reduced by comparing only the block selected by the selection unit with the search data.

However, in the technique described in Japanese Patent Application Laid-Open No. Hei 3-212896, it is necessary to preliminarily include memory block selection information as a part of an input address at the time of retrieval.
Further, there is a problem that extra hardware and processing time are required for the interpretation.

In view of the above, it is an object of the present invention to provide an associative memory in which only necessary parts are activated in a situation where it is not necessary to activate the entire circuit, thereby reducing power consumption. And

[0052]

The associative memory of the present invention that achieves the above object stores a large number of stored data,
In an associative memory to which search data is input and search for storage data corresponding to the input search data, (1) at least one memory word group including a plurality of memory words in which each storage data is stored. A large number of memory words divided into a plurality of memory blocks (2) provided in correspondence with a large number of memory words, at the time of a search, stored in the corresponding memory word corresponding to the inputted search data A flag register that stores a match flag indicating that stored data corresponding to the input search data has been stored when it is detected that data has been stored. A bit for driving a bit line of a predetermined memory block at the time of this search according to the state of the match flag stored in the register Characterized by comprising a drive circuit.

[0053]

According to the associative memory of the present invention, as described with reference to FIG. 4, for example, when data for a plurality of words is continuously searched, the entirety of a plurality of blocks are activated for the first search. In the second and subsequent searches, the previous search result is reflected in the current search, and a memory block including a memory word in which a match was previously detected and / or the same memory word group are divided and stored. Only another possible memory block (for example, an adjacent block) is activated, and power consumption is reduced.

[0054]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 8 is a block diagram of a first embodiment of the content addressable memory according to the present invention.

In this associative memory, a large number of memory words are divided into a plurality of memory blocks and a plurality (N in the embodiment) of memory blocks 51__
, 51_2,..., 51_N. Each of the memory blocks 51_1, 51_2,..., 51_N is configured by at least one memory block group including a plurality of memory blocks, which is a unit in which a search over a plurality of words is performed.

Each of the blocks 51_1, 51_2,..., 51
_N include bit line drive circuits 52_1 and 52_
, 52_N are provided, and each bit line drive circuit 52_1, 52_2,..., 52_N has a search data line 53, control lines 54A, 54B,
5_1, 55_2, ..., 55_N are connected.

The search data line (also referred to as a bit line)
53 is input with search data for reading / writing from / into a memory or performing a search.

The control line 54A is activated when performing a search operation.

The control line 54B is activated at the time of inputting the first search data in a search over a plurality of words, and invalidates the search results up to the previous time.

The in-block match lines 55_1 and 55_
2, ..., 55_N are activated when at least one or more matches among a plurality of words included in each memory block occur.

The intra-block match line and a circuit for generating the same (not shown) are provided in a general associative memory for prioritizing a plurality of divided memory blocks. It is not new hardware required to implement.

The bit line driving circuits 52_1 and 52_
2,..., 52_N are their respective lines 53, 54A, 54
In accordance with the signal states of B, 55_1, 55_2,..., 55_N, as a result of the search, a match occurs in itself, and when the corresponding intra-block match line is activated, the bit line (including the bit bar line) ) 56_1,56_2, ..., 56
_N is activated to activate only the corresponding memory block and perform a search operation.

FIG. 9 is a circuit diagram showing the ith bit line drive circuit of FIG.

In FIG. 9, 60_i is an OR gate for outputting the logical sum of the signal of the initial search control line 54B and the intra-block matching line 55_i, and 61_i is the memory block 51.
_I, a transfer gate turned on and off by the output of the OR gate 60_i for activating the bit line 56_i_1, an inverter 62_i for inverting the output of the OR gate 60_i, and 63_i for inverting the output of the transfer gate 61_i. And a bit bar line 56_i_ connected to the memory block 51_i.
2 is an inverter for activating 2.

First, at the time of the first search, the first search control line 5
4B, a control signal of logic “1” is applied, the control signal is transmitted to the transfer gate 61 — i via the OR gate 60 — i, and the transfer gate 61 —
i is turned on, and the search data input via the search data line 53 is applied to the bit lines 56_i_1 and the bit bar lines 56_i_2. In the first search, all the memory blocks 51_
A search is performed at 1, 51_2,..., 51_N.

The flag registers in the memory block 51_i (the second flag registers 24_1, 24_2,
..) Is stored in any one of the blocks, the OR gate 64 — i that performs the logical OR operation of the storage states of the flag registers in the block, and the logical “1” is supplied to the intra-block match line 55 — i. 'Is output.

At the time of the second or subsequent search, a control signal of logic "0" is applied to the control line 54B. Therefore, only when a match is detected in any of the memory words of the block 51_i in the previous search, the search data input via the search data line 53 in the current search is changed to the bit line 56_i_1. , Bit bar line 56_i_2. If no match is detected in any of the memory words of the memory block 51_i during the previous search, the output of the OR gate 60_i is logic '0' because the in-block match line 55_i remains at logic '0'. And the transfer gate 61 — i is in the “off” state, and the search data input via the search data line 53 at the time of this search is the bit line 56 — i_1,
Not applied to the bit bar line 56_i_2, the bit line 56
_I_1 and power consumption due to charging and discharging of the bit bar line 56_i_2 are suppressed.

As an example, consider a case where four consecutive search data are searched. When the first search data is input, the control line 54B is activated, and the bit line driving circuit 5
All the bit lines (including the bit bar lines) are activated via 2_1, 52_2, ..., 52_N, and all N blocks 51_1, 51_2, ..., 51_N are activated.

When a match is found in p (p ≦ N; N is the total number of blocks) blocks in the first search,
The p intra-block match lines are activated, and the second search operation is performed only on the p memory blocks. As a result, if a match is detected in q blocks (q ≦ p), then the q intra-block match lines are activated. Assume that a match is detected in r (r ≦ q) third and s (s ≦ r) memory blocks in order.

The number of memory blocks activated in this manner is sequentially reduced, and the power consumption of a circuit that does not have a bit line driving circuit and always searches for all memory words is expressed by (p / N) × ( q / N) × (r / N) × (s / N) <<
1 power consumption.

Normally, p, q, r, s << N, and it is possible to achieve a great reduction in power consumption for a plurality of successive search operations.

Next, a second embodiment of the present invention will be described in detail.

FIG. 10 shows the overall structure of the second embodiment.
FIG. 11 shows a detailed configuration.

In the memory block 51_i of FIG. 11, 70_1_i to 70_k_i are each a memory word 1
The register 71_i for storing the match flag output from the 1_1_i to 11_k_i is a corresponding switch element 72_1 when the match flag is stored in any of the match flag storage registers 70_1_i to 70_k_i.
_I to 72_k_i, a wired NOR including a wire grounded by 73_i is connected to a power supply to precharge the switch, and a switch element for maintaining the state is connected to the wire NOR 74_i.
Is an inverter for inverting the output of the above to make an in-block match signal (hit flag). The combination of the wired NOR 71_i and the inverter 74_i corresponds to the OR gate 64_i in FIG.

In the bit line driving circuit 52_i of FIG. 11, reference numeral 80_i denotes a corresponding memory block 51_i and the preceding and succeeding memory blocks 51_i-1 (not shown), 51_i.
A register 81_i for storing the in-block hit flag input from _i + 1 is an OR gate (corresponding to the OR gate 60_i in FIG. 9) for outputting the logical sum of the output of the in-block hit flag storage register 80_i and the output of the first search control line 54B. ), 82_i are the OR gates 81_i.
AND gate (not shown in FIG. 9) that outputs the logical product of the output of the search control line 54A (not shown in FIG. 9) and the output of
i denotes a transfer gate (corresponding to the transfer gate 61_i in FIG. 9) for activating the bit line 56_i_1, the on / off state of which is controlled by the output of the AND gate 82_i, and 84_i denotes a bit bar line 56_i.
and AND gate 82_i for activating i_2
A transfer gate with an inverter whose on / off state is controlled by the output of the transfer gate (corresponding to a combination of the transfer gate 61 — i and the inverter 63 — i in FIG. 9);
85_i and 86_i are bit lines 56_i_
This is a switch element for precharging 1,56_i_2.

When search data belonging to the same word group is input across two memory blocks, even if a block in which a match is not detected in the above-mentioned search is activated in the current search, Need to be For this reason, in the second embodiment, a certain bit line driving circuit is also supplied with the in-block matching lines on both sides thereof.

Although it is conceivable that search data belonging to the same word group is input over three blocks, it is generally difficult to imagine that certain related data extends over three or more blocks. It is sufficient to consider data spanning two blocks. If it is assumed that the data covers three blocks, not only the adjacent blocks but also the intra-block matching lines of the adjacent blocks may be input to the block line driving circuit.

The effect of the second embodiment will be described along with the search operation.

As an example, consider a case where a search for a word group over three words is performed three times in a row. First, at the time of the first search, the first search control line 54B is activated, the search data is applied to the bit line, and the control line 5
Activate 4A. Since the control line 54B is activated,
In the first search, all the memory blocks l are activated, and the search is performed on all memory areas.

When the control line 54A is activated, the precharge of the bit line drive circuit and the precharge of the memory block are released, search data is applied to the memory, and the search result is detected.

The result is stored in the match flag storage register 70_i in the memory block and also in the in-block hit flag storage register 80_i of the bit line drive circuit 52_i. As a whole, p (p ≦ N;
When a match is detected in the memory blocks of (N is the total number of blocks), in the second search, 3p (3p ≦ N) memory blocks are activated in the worst case where all the match detection blocks are not at both end positions. Is done. As a result, if a match is detected in q memory blocks, in the third search,
At worst, 3q memory blocks are activated. As a result, power consumption is (N / N) × (3p / N) × (3q / N) << 1 times that of the circuit not having the configuration of the present embodiment.

Usually, p and q << N, and a great reduction in power consumption is achieved.

FIG. 12 shows a third embodiment of the present invention.

The present embodiment is effective when the number of data words extending between memory blocks can be assumed in advance.

That is, it is necessary to activate the memory blocks on both sides only when the word in which the coincidence forms the same word group as the word of the adjacent memory block. If the word group exists in a single memory block, only the own memory block needs to be activated even if a match occurs.

Therefore, in the memory block, the in-block coincidence signal is sent to only its own bit line driving circuit, to its own bit line driving circuit, and to its own bit line driving circuit. Although they go to the circuit, they are classified and output in three ways.

By adopting this configuration, the probability of activated blocks is lower than in the second embodiment, and a significant reduction in power consumption is achieved.

In each of the above embodiments,
Although all memory blocks are activated at the time of the initial search, the number of memory blocks to be activated at the time of the initial search can be limited, for example, by a technique described in Japanese Patent Application Laid-Open No. 3-212896. It is.

[0090]

As described above, in the associative memory of the present invention, at the time of a plurality of consecutive searches, a memory block that matches in the previous search and / or the same memory word group is divided and stored. Since only other memory blocks (for example, adjacent blocks) that may be present are activated, power consumption is significantly reduced.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram showing an example of a conventional associative memory

FIG. 2 is a block diagram showing an example of a conventional associative memory having a data extension function;

FIG. 3 is a diagram showing an example of data of a group structure.

FIG. 4 is a block diagram showing a comparative example of an associative memory;

FIG. 5 is a schematic diagram showing one method for realizing a variable-length data line.

FIG. 6 is a schematic diagram showing another method for realizing a variable-length data line.

FIG. 7 is a circuit diagram illustrating an example of an attribute determination circuit.

FIG. 8 is a block diagram of a first embodiment of an associative memory according to the present invention;

FIG. 9 is a circuit diagram of a bit line driving circuit used in the first embodiment.

FIG. 10 is a block diagram of a second embodiment of the content addressable memory according to the present invention;

FIG. 11 is a circuit diagram of a bit line driving circuit used in a second embodiment.

FIG. 12 is a block diagram of a third embodiment of the content addressable memory according to the present invention;

[Explanation of symbols]

11_1, 11_2,..., Memory words 11_1_1, 11_2_1,... Attribute storage units 11_1_1, 11_2_2,. 21_1, 21_2, ... OR gate 23_1, 23_2, ... first flag register 24_1, 24_2, ... second flag register 25 Match result latch control line 30_1, 30_2, ... attribute match line 31_1, 31_2, ... third flag register 32_1, 32_2, ... Data lines 33_1, 33_2, ... First switches 34_1, 34_2, ... Second switches 51_1, 51_2, ... Memory blocks 52_1, 52_2, ... Bit line drive control Circuit 53 Search data line 54A Search control line 54B Initial search control line 55_1, 55_2, ... Match line in block 56_1, 56_2, ... Bit line (including bit bar line) 70_1_i, 70_2_i, ... Match flag storage register 80_i Hit flag in block Storage register

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-3-212896 (JP, A) JP-A-6-333395 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G11C 15/00-15/06 G06F 17/30 WPI (DIALOG)

Claims (9)

(57) [Claims] 1. An associative memory for storing a large number of stored data, inputting search data, and searching for stored data corresponding to the input search data. Memory words divided into a plurality of memory blocks so as to include at least one memory word group each, and a memory corresponding to each of the plurality of memory words at the time of search. When it is detected that the storage data corresponding to the input search data is stored in the word, a match flag indicating that the storage data corresponding to the input search data is stored is stored. A flag register, and in accordance with the state of the match flag stored in the flag register in the previous search, Associative memory to the bit line drive circuit for driving the bit line constant in the memory block, further comprising a said. 2. The content addressable memory according to claim 1, wherein said bit line driving circuit drives a bit line of a memory block including a memory word corresponding to a flag register storing said match flag. 3. The bit line driving circuit according to claim 2, wherein the bit line driving circuit further drives a bit line of another memory block in which the memory word group may be divided and stored. Associative memory. 4. The associative memory according to claim 3, wherein said another memory block to which said bit line is driven is a memory block adjacent to a memory block including a memory word corresponding to a flag register storing said coincidence flag. memory. 5. The associating method according to claim 2, wherein said bit line driving circuit drives a bit line of a corresponding memory block according to a division state of said memory word group into another memory block. memory. 6. An associative memory according to claim 1, wherein at the time of the first search for said memory word group, bit lines of all memory blocks are driven. 7. The associative memory according to claim 1, wherein even during the first search for said memory word group, only bit lines of a predetermined memory block are driven. 8. An associative memory according to claim 1, wherein said match flag is generated from an output of a circuit for prioritizing memory blocks. 9. The memory word group including a memory word corresponding to the flag register in response to storing the match flag in the flag register during a previous search. , An associative memory including a plurality of continuous search control circuits for executing the current search.