JP3597882B2 - Associative memory - Google Patents

Description

[0001]
[Industrial applications]
The present invention provides an associative function having a function of extending the data width for performing a match search to a plurality of words, that is, a function of detecting a match as a whole when a match is detected in a plurality of successive searches. Regarding memory.
[0002]
[Prior art]
Conventionally, each digital data is stored in each of a plurality of arranged memory words, search data is input, and the input search data has a bit pattern that matches all or a predetermined part of the bit pattern. 2. Description of the Related Art An associative memory (Content Addressable Memory) for searching a memory word in which digital data is stored has been proposed.
[0003]
FIG. 2 is a circuit block diagram illustrating an example of the associative memory.
The associative memory 10 is provided with a large number of memory words 11_1, 11_2,..., 11_n composed of m-bit memory cells arranged in the horizontal direction in FIG. The associative memory 10 includes a search data register 12 into which one-word search data is input and latched. The bit pattern of all or a predetermined part of the search data latched in the search data register 12 and each memory word .., 11_n are compared with the bit patterns of the portions corresponding to the bit patterns in the stored data, and are provided corresponding to the respective memory words 11_1, 11_2,..., 11_n. , 14_n corresponding to the memory words 11_1, 11_2,..., 11_n having the same bit pattern as the logic lines “1”, 14_2,. ) Is output. The other matching lines 14_1, 14_2,..., 14_n remain at logic ‘0’ (here, 0V).
[0004]
The signals output to the match lines 14_1, 14_2,..., 14_n are stored in the flag registers 15_1, 15_2,. Here, as an example, as shown, '0', '1', '1', '0', ..., '0', '0' are stored in the flag registers 15_1, 15_2, ..., 15_n, respectively. It shall have been done. The signals stored in the flag registers 15_1, 15_2,..., 15_n are input to the priority encoder 16. The encode pulse EP is input to the priority encoder 16 and each time the encode pulse EP is input, a flag register (here, a flag register 15_2 and a flag register 15_2) storing a signal of logic '1' in accordance with a predetermined priority order. The address signal AD corresponding to the flag register having the higher priority among the two registers 15_3) is sequentially output. Here, the smaller the suffix, the higher the priority. Therefore, when only one encode pulse EP is input, the memory address corresponding to the flag register 15_2 is output. The address signal AD output from the priority encoder 16 is input to the address decoder 17 as needed. The address decoder 17 decodes the input address signal AD, and inputs the input address of the word lines 18_1, 18_2,..., 18_n provided corresponding to the respective memory words 11_1, 11_2,. An access signal (here, a logical “1” signal) is output to any one of the word lines (here, the word line 18_2) corresponding to the signal AD. Thereby, the stored data stored in the memory word 11_2 corresponding to the word line 18_2 to which the access signal has been output is read out to the output register 19.
[0005]
Next, when another encode pulse EP is input, the address of the memory word 11_3 corresponding to the flag register 15_3 can be obtained.
As described above, the associative memory 10 searches the stored data stored in the many memory words 11_1, 11_2,..., 11_n using all or a predetermined part of the search data, and This is a memory configured to be able to obtain the address of a memory word and to read out the entire data stored in the memory word as needed.
[0006]
In the associative memory having the basic configuration as described above, a technique has been proposed in which the data width to be searched for a match is extended to two or more words.
FIG. 3 is a block diagram illustrating an example of an associative memory having a data extension function. The components corresponding to the components of the associative memory shown in FIG. 2 are denoted by the same reference numerals as those in FIG. 2, and redundant description of the components will be omitted.
[0007]
Each of the match lines 14_1, 14_2,... Extending from each of the memory words 11_1, 11_2,... Is connected to one input terminal of each of the AND gates 20_1, 20_2,. Are connected to the other input terminals of the AND gates 20_1, 20_2,..., Respectively, and one input terminal of each OR gate 21_2, 21_3,. 22. However, the OR gate corresponding to the uppermost AND gate 20_1 in the drawing is omitted, and the first search control line 22 is directly connected to the input terminal of the AND gate 20_1.
[0008]
The output terminal of each AND gate 20_1, 20_2,... Is connected to the data input terminal of each first flag register 23_1, 23_2,..., And the output terminal of each first flag register 23_1, 23_2,. Are connected to the input terminals of the flag registers 24_1, 24_2,. The output terminals of the second flag registers 24_1, 24_2,... Are connected to the priority encoder 16 (not shown in FIG. 3) shown in FIG. 2, and the OR gate 21_2 corresponding to the memory word adjacent to the lower part in FIG. , 21_3,....
[0009]
Each pair of the first and second flag registers 23_1, 24_1, 23_2, 24_2,... Corresponds to each flag register 15_1, 15_2,.
The first flag registers 23_1, 23_2,... And the second flag registers 24_1, 24_2,... Both receive the match result latch signal S1 output to the match result latch control line 25, and the match result latch signal. The input data input from each data input terminal is latched by S1, but the first flag registers 23_1, 23_2,... Latch the input data at the time of the rising edge a of the match result latch signal 51, and the second flag register 23_1, 23_2,. The input data at the time of the falling b of the match result latch signal S1 is latched in the flag registers 24_1, 24_2,.
[0010]
In the associative memory configured as described above, a match search is performed as follows. Here, as shown in the figure, each of the memory words 11_1, 11_2, 11_3, 11_4, 11_5, 11_6,... Stores stored data A, B, C, D, C, F,. I do.
Here, when each stored data is searched independently, the first search timing signal S2 is output to the first search control line 22 when the search is performed by inputting the search data REF_DATA. Here, assuming that data 'B' is input as search data REF_DATA, a match signal of logic '1' is output to match line 14_2 corresponding to memory word 11_2 storing data 'B', and AND gate 20_2 is output. The first search timing signal S2 is also input to the AND gate 20_2 via the OR gate 21_2, so that a signal of logic “1” is output from the AND gate 20_2. Also, at this time, a signal of logic '0' is output to the other matching lines 14_1; 14_3, 14_4,..., And the corresponding AND gates 20_1; 20_3, 20_4,. A signal is output.
[0011]
The signal of logic “1” output from the AND gate 20_2 is latched by the first flag register 23_2 at the timing of the rising edge a of the match result latch signal S1 output to the match result latch control line 25, and the subsequent match result The signal is latched by the second flag register 24_2 at the timing of the falling b of the latch signal S1.
[0012]
Further, at each timing when the signal of logic '1' is latched in the first flag register 23_2 and the second flag register 24_2, the other first flag registers 23_1; 23_3, 23_4,. Registers 24_1; 24_3, 24_4,... Latch a signal of logic “0”.
The signals of logic '0', '1', '0',... Latched in the second flag registers 24_1, 24_2, 24_3,... Are input to the priority encoder 16 shown in FIG. The address signal AD of the word 11_2 is obtained.
[0013]
Next, a case in which a search with an extended data width is performed will be described. Here, a case will be described in which two-word data consisting of data "B" and data "C" expanded to two words is searched.
In this case, a search for data "B" is first performed in the same manner as described above. As a result, the signal of logic “1” is latched in the first and second flag registers 23_2 and 24_2 corresponding to the memory word 11_2. Next, a search is performed by inputting data 'C' as search data REF_DATA. At this time, the first search control line 22 does not output the first search timing signal S2, and the first search control line 22 has a logic '0'. Keep in the state. When data “C” is input as search data REF_DATA and a search is performed, a match signal of logic “1” is output to match lines 14_3 and 14_5 corresponding to the two memory words 11_3 and 11_5 shown in FIG. Since the signal of logic '1' latched in the second flag register 24_2 is input to 21_3, the match signal on the match line 14_3 passes through the AND gate 20_3, and the first and second flag registers 23_3 , 24_3, a signal of logic '1' indicating a match is latched. On the other hand, since the signal of logic '0' latched in the second flag register 24_4 is input to the OR gate 21_5, the match signal of the match line 14_5 is cut off by the AND gate 20_5, and the first and second flag registers 23_5 and 24_5 are latched with a signal of logic '0' indicating mismatch. In this way, two-word data consisting of a pair of data 'B' and data 'C' is detected as coincident. Match detection of data of three or more words is performed in the same manner.
[0014]
However, the associative memory shown in FIG. 3 has a data width extending function, but data expanded to two words, three words, etc., must be stored in a predetermined order in adjacent memory words. In the case where a plurality of data to be searched are stored in memory words separated from each other or in the reverse order, for example, in the order of data 'C' and data 'B', a plurality of data are stored. No combined match detection is possible.
[0015]
FIG. 4 shows a data structure when such a search is required. FIG. 4 shows a data structure in which four data to which attributes I, II, III, and IV are respectively provided as a set to form one data group. To clarify the concepts of the data group and the attribute, for example, each data group of each group number 1, 2, 3, 4,... Is data belonging to each individual, and the attribute I is The name and attribute II indicate the date of birth of the person, and the attribute III indicates the address,...
[0016]
When a data group consisting of a plurality of data to which the attributes I, II, III, and IV are assigned is stored in an associative memory and a search is performed, for example, a data group with a group number 1 is searched. For example, the search for the data "A" and the search for the data "B" are performed in this order, and not only the remaining data "C" and "D" of the matching data group are read, but also the data "A". If you want to read the remaining data 'B' and 'C' by searching for 'and data' D ', or search for data' B 'first, then search for data' A ' Sometimes you want to.
[0017]
However, such a search is impossible with the associative memory having the word width expansion function described above (see FIG. 3). Further, in the above-mentioned associative memory, when data "A" and data "B" are searched, data "A" and data II with attribute I in the column of group number 1 shown in FIG. Can be distinguished from the pair of the data "B" with the attribute II and the data "B" with the attribute II and the data "B" with the attribute III in the column of the group number 4. For example, based on the information of the attribute I of "name" and the information of attribute II of "date of birth", even if the user tries to know the information of the attributes III and IV of a specific individual matching them, Even in the case of a pair, noise other than necessary information is mixed, for example, a match is detected.
[0018]
An associative memory that solves such a problem has been proposed by the present applicant (see Japanese Patent Application No. 5-248121). Hereinafter, the associative memory according to this proposal will be described.
FIG. 5 is a block diagram showing an example of the associative memory according to the above proposal. The same components as those of the associative memory shown in FIG. 3 are denoted by the same reference numerals as those shown in FIG. 3, and only different points will be described.
[0019]
Each of the memory words 11_1, 11_2,... Includes an attribute storage unit 11_1_1, 11_2_1,... For storing attributes, and data storage units 11_1_2, 11_2_2,. Stores stored data composed of pairs of attributes and data corresponding to each other. Here, as shown in the figure, each of the memory words 11_1, 11_2, 11_3, and 11_4 has attribute I, data 'A', attribute II, data 'B', and attribute belonging to the group number 1 shown in FIG. III, data 'C', attribute IV, data 'D' are stored. Each of the memory words 11_5, 11_6,... Stores an attribute I, data “C”, an attribute II, data “F”,. In the search, search data REF_DATA including a pair of an attribute and data is input.
[0020]
A match signal is output to each of the memory words 11_1 and 11_2 when the stored data (both attributes and data) stored therein matches the input search data (both attributes and data). In addition to the matching lines 14_1, 14_2,..., There are provided attribute matching lines 30_1, 30_2,. Note that the matching of only the attribute and the matching of both the attribute and the data are configured in the same manner as the conventional match detection circuit, and the conventional match detection circuit is a very common technique in the field of associative memory. And illustration thereof will be omitted.
[0021]
There are provided third flag registers 31_1, 31_2,... Corresponding to the respective memory words 11_1, 11_2, and each attribute match line 30_1, 30_2,. Extends to the input terminal. Further, the associative memory is provided with one data line 32_1, 32_2,... For each of a memory word group including a plurality of memory words storing data belonging to each data group shown in FIG. The first switches 33_1, 33_2,... Are provided between the data lines 32_1, 32_2,... And the output terminals of the second flag registers 24_1, 24_2,. These first switches 33_1, 33_2,... Are specifically configured using transistors and the like. The same applies to other switches described later. Each of the first switches 33_1, 33_2,... Becomes conductive when the corresponding third flag register 31_1, 31_2,. It is shut off when it is done. The third flag registers 31_1, 31_2,... Latch the signals of the corresponding attribute match lines 30_1, 30_2,... At the falling edge b of the match result latch signal S1 output to the match result latch control line 25. I do.
[0022]
Are provided between the data lines 32_1, 32_2,... And the input terminals of the respective OR gates 21_1, 21_2,..., And the second switches 34_1, 34_2,. Are controlled by signals on the corresponding attribute match lines 30_1, 30_2,... So that the signal is in a conductive state when the signal is a logic “1” indicating a match, and is turned off in a logic “0” indicating a mismatch. . The associative memory shown in FIG. 5 differs from the associative memory shown in FIG. 3 in that an OR gate 21_1 is also provided before the AND gate 20_1 corresponding to the uppermost memory word 11_1 in the figure.
[0023]
In the associative memory configured as described above, the match search is performed as follows.
Since the single data search for one word and the first search among a plurality of continuous words are the same as those of the conventional associative memory with a word extension function shown in FIG. 3, the description is omitted here. Here, in the first search, logic “1” is latched in the first and second memory words 23_2 and 24_2 corresponding to the memory word 11_2 by the search data REF_DATA including the attribute II and the data “B”. Shall be. At this time, in response to the attribute match, a signal of logic '1' is output to the attribute match line 30_2 corresponding to the memory word 11_2, whereby the signal of logic '1' is also output to the corresponding third flag register 31_2. The signal is latched, the corresponding first switch 33_2 is turned on, and the signal of logic '1', which is stored in the corresponding second flag register 24_2 and indicates the coincidence of both the attribute and the data, is output to the data line 32_1. At the same time, the corresponding second switch 34_2 is also turned on, but this is an unnecessary operation in the first search.
[0024]
Next, it is assumed that search is performed by inputting search data REF_DATA including attribute IV and data 'D'. At this time, as in the case of the associative memory of FIG. 3, the initial search control line 22 is held at logic "0". At this time, in response to the attribute match, a signal of logic '1' is output to the attribute match line 30_4 corresponding to the memory word 11_4, whereby the corresponding second switch 34_4 is turned on and output to the data line 32_1. Further, a signal of logic '1' of the second flag register 24_2 corresponding to the memory word 11_2 is input to the AND gate 20_4 via the OR gate 21_4. Therefore, a match between the attribute IV and the data 'D' is detected in the memory word 11_4, a match signal of logic '1' is output to the match line 14_4, and the match result latch output to the match result latch control line 25 is output. The signal of logic “1” is latched in the corresponding first and second flag registers 23_4 and 24_4 by the signal S1. At this time, the signal of logic “1” output to the attribute match line 30_4 is latched by the corresponding third flag register 31_4, the corresponding first switch 33_4 is turned on, and the signal of the second flag register 24_4 is A signal of logic “1” is output to the data line 32_1. In the second search, a logic '0' indicating an attribute mismatch is output to the attribute match line 30_2 corresponding to the memory word 11_2, and '0' is stored in the corresponding third flag register 31_2. , The first switch 33_2 corresponding to the memory word 11_2 is turned off.
[0025]
As a result, the signal of logic '1' of the second flag register 24_4 corresponding to the memory word 11_4 is input to the priority encoder 16 (see FIG. 2), and the address of the memory word 11_4 is obtained. It is known in advance that attribute IV is stored in 11_4, and when it is desired to read, for example, data of attribute III in the same group, 1 is subtracted from the obtained address to obtain the address of memory word 11_3. What is necessary is just to input the address to the address decoder 17 and read out the contents of the memory word 11_3.
[0026]
On the other hand, at the time of the second search, if the search is performed using the search data including the attribute IV and the data “B” instead of the search data including the attribute IV and the data “D”, for the memory word 11_4, Since the attributes match, the second switch 34_4 is turned on, and the signal of logic “1” output to the data line 32_1 is taken in. However, since the data is different, the logic “0” indicating mismatch does not appear on the match line 14_4. The logic "0" is output and latched in the first and second flag registers 23_4 and 24_4 to indicate that no match was detected. Also, the attribute does not match for the memory word 11_2 to which the data 'B' matches, and therefore both the attribute and the data do not match.
[0027]
As described above, in the associative memory shown in FIG. 5, in the same group, even if data stored in memory words separated from each other is searched or data is searched in reverse order. Even a search can be performed.
Here, the data lines 32_1, 32_2,... In the associative memory shown in FIG. 5 have fixed lengths assuming that the number of data belonging to one group is predetermined. When a fixed-length data line is provided, it is necessary to estimate the maximum number of data belonging to one group and provide a data line having a length corresponding to the maximum number of data. In this case, useless memory words are generated when a data group is constituted by a smaller number of data than the maximum. Therefore, it is preferable that the data lines have a variable length according to the number of data belonging to one group.
[0028]
FIG. 6 is a schematic diagram showing one method for realizing a variable-length data line.
A data line 32 extends over a plurality of memory words 11_1, 11_2, 11_3,..., And the data line 32 has switches corresponding to the other memory words 11_2, 11_3,. 40_1, 40_2, 40_3,... Are arranged in series with each other. These switches 40_2, 40_3, 40_4,... Are arranged between the corresponding memory words 11_2, 11_3, 11_4,... And the memory words 11_1, 11_2, 11_3,. Each of the switches 40_2, 40_4, 40_6,... Among the switches 40_2, 40_3, 40_4,... Is turned on by the first switch control signal output to the first control line 41, and every third switch is turned on. , 40_3, 40_7,... Are turned on by the second switch control signal output to the second control line 42, and every third switch 40_5,. Is turned on by the switch control signal of.
[0029]
When the number of data constituting one data group is 2, a first switch control signal is output to the first control line 41 to turn on every other switch 40_2, 40_4, 40_6,. Thus, data lines cut for each of the two memory words 11_1, 11_2; 11_3, 11_4; 11_5, 11_6; are formed. When the number of data constituting one data group is 4, the first switch control signal is output to the first control line 41 and the second switch control signal is output to the second control line 42. Then, data lines cut for each of the four memory words 11_1, 11_2, 11_3, 11_4; 11_5, 11_6,... Are formed. Similarly, when the number of data constituting one data group is 8, the first and second switch control signals are output to the first control line 41 and the second control line 42, respectively, and the third control A third switch control signal is output on line 43. .., 11_8; 11_9,..., And data lines cut off for each of the eight memory words 11_1,.
[0030]
According to this method, when the number of data constituting one data group is a multiple of 2, no free space is generated in the memory word, but when the number of data other than a multiple of 2, for example, 3, 5, 9, or the like, an empty memory is used. Words will result. If a large number of switches 40_2, 40_3,... Can be turned on and off arbitrarily so as not to generate this empty memory word, the number of control lines becomes large and switch control signals are output to those control lines. A complicated control circuit is required. Therefore, the method shown in FIG. 6 is not suitable for completely arbitrarily controlling the length of the data line.
[0031]
FIG. 7 is a schematic diagram showing another method for realizing a variable data line.
A data line 32 extends over a number of memory words, and switches 40_2, 40_3, 40_4,... Corresponding to each of the other memory words except the uppermost memory word are connected to the data line 32 in series. The points provided are the same as those in FIG. Each memory word is provided with attribute storage units 11_1_1, 11_2_1, 11_3_1,..., And the attribute storage units 11_1_1, 11_2_1, 11_3_1,. Is stored. In this example, according to whether the attribute stored in the attribute storage units 11_1_1, 11_2_1, 11_3_1,... Is the attribute I or the other attributes II, III, IV, in the case of the attribute I, the corresponding switch is kept off. In the case of other attributes II, III and IV, the corresponding switches are turned on. With this configuration, the attribute I data is placed at the head of each data group, regardless of the number of data that constitutes one data group, and even if data groups with different numbers of data are mixed. As a result, automatically cut data lines are formed for every number of memory words equal to the number of memory words.
[0032]
FIG. 8 is a circuit diagram illustrating an example of an attribute determination circuit that determines whether an attribute is I or other.
Here, '000' is assigned to the attribute I, and when the attribute stored in the attribute storage unit 11_i_1 is the attribute I ('000'), '0' is output from the OR gate. Is turned off, and the data lines on both sides of the transistor 40 are electrically disconnected. If the attribute stored in the attribute storage unit 11_i_1 is an attribute other than the attribute I, "1" is output from the OR gate, the transistor 40 is turned on, and the data lines on both sides of the transistor are connected.
[0033]
Thus, in the associative memory shown in FIG. 5, the length of the data lines 32_1, 32_2,... Can be adjusted according to the number of data constituting one data group. Of course, instead of using the attribute data, the length of the data line may be adjusted by controlling the switch using a dedicated control line.
[0034]
[Problems to be solved by the invention]
The associative memory according to the above proposal is, as described above, in that a search over a plurality of memory words at addresses apart from each other in a memory word group in which one data group is stored and a search in a reverse order are allowed. Although it is extremely superior to the conventional associative memory, the configuration shown in FIG.
(A and B) or (X and Y) ... (1)
It is not possible to perform a mixed search of AND (or) and OR (or), such as whether or not there is a data group that matches. For example, when the data as shown in FIG. 5 is stored, first, when the first search timing signal S2 is input and the search is performed with the attribute I and the data A, the second memory word 24 1 becomes logic "1". Next, when the search is performed with the attribute II and the data B without inputting the first search timing signal S2, the second memory word 24 2 becomes logical "1" and the second memory word 24 2 is reset to logic '0'. Up to this point, next, when searching with the attribute III and the data X, whether or not the first search timing signal S2 is input, any of the second memory words 24 shown in FIG. 1,24 ,... Also become logical "0", which results in a failure in the search of the expression (1). In order to avoid this, it is necessary to examine an intermediate search result in the middle of a series of searches (for example, from the beginning to the end of the above formula (1)) by an external device such as a microcomputer. However, there is a problem that the search speed is reduced.
[0035]
In view of the above circumstances, the present invention makes it possible to perform a complicated logic search, for example, as in the above equation (1), without accessing the search results up to the middle during a series of searches. An object is to provide an associative memory.
[0036]
[Means for Solving the Problems]
The associative memory of the present invention that solves the above object stores a plurality of stored data, and the search data is input, and in the associative memory that searches the stored data corresponding to the input search data,
(1) A plurality of memory words for storing a plurality of stored data for each stored data
(2) There is a correspondence between search data input at the time of a search provided for each of the plurality of memory words and each of the stored data stored in each of the plurality of memory words. A plurality of flag registers for storing hit flags indicating the existence of the corresponding relationship when it is detected that
(3) A hit column register for sequentially storing whether a hit flag is stored in any of the plurality of flag registers for each of a plurality of searches.
It is characterized by having.
[0037]
Here, the associative memory of the present invention includes the above (1) to (3),
(4) The memory word stores, for each stored data, each stored data constituting a plurality of data groups each including a set of a plurality of stored data;
(5) When it is detected that a correspondence exists between the stored data stored in the predetermined memory word and the input search data, the correspondence is stored in the flag register corresponding to the predetermined memory word. And a first mode for storing a hit flag indicating the presence of a search flag, and a data to which a corresponding relationship is detected in a predetermined first memory word at the time of this search, and to which the stored data stored in the first memory word belongs. A hit flag is stored in a flag register corresponding to an arbitrary second memory word other than the first memory word belonging to a memory word group consisting of a plurality of memory words for storing respective stored data constituting the group. If so, the hit flag is stored in the flag register corresponding to the first memory word, and the second memory word is stored. Coincidence detecting circuit and a second mode to reset the hit flag stored in the flag register corresponding to the de
It is preferable to provide
[0038]
Also, the associative memory of the present invention stores each storage data consisting of a pair of an attribute for identifying a plurality of storage data in one data group from each other and data with the attribute to each of the plurality of memory words. The search may be performed by using stored search data including pairs of attributes and data.
[0039]
[Action]
Since the associative memory of the present invention includes the hit string register of the above (3), an intermediate search result during a series of searches is stored in the hit string register. Is realized.
[0040]
【Example】
Hereinafter, examples of the present invention will be described.
FIG. 1 is a circuit block diagram showing a characteristic part of the present invention in an embodiment of the associative memory of the present invention. This circuit block shows a part of the associative memory shown in FIG. 5 and a part added to the associative memory shown in FIG. 5, based on the associative memory shown in FIG.
[0041]
Here, as shown, each memory word 11 1,11 2, ..., 11 m, ..., 11 .., A, B, C, C,..., A, A, C, and F, respectively, with attributes I to IV and data G, H, I, J, A, B, E, E,. Is stored. In this embodiment, the attribute register 12 1 and the attribute data stored in the input data register 12 2 is used as a search data with a pair with the input data stored in the memory word 11. 1,11 2, ..., 11 m, ..., 11 Search is performed by inputting to n,.
[0042]
The associative memory is provided with a search mode register 51. The search mode register 51 stores an initial search timing signal S2 in each of a series of searches (here, four searches). A flag for determining whether to input is stored. Here, in order to perform a search described later, '1, 0, 1, 0' is stored in the search mode register 51, and in a series of four searches, an initial search timing signal is used in the first search. S2 is input, the first search timing signal S2 is not input in the second search, the first search is regarded as the first search in the third search, the first search timing signal S2 is input, and the first search timing is input in the fourth search. The signal S2 is not input.
[0043]
Also, each memory word 11 1,11 2, ..., 11 m, ..., 11 n,... corresponding to n,. 1,11 2, ..., 11 m, ..., 11 A flag register 24 storing a hit flag indicating whether a match is detected at n,. 1,24 2, ..., 24 m, ..., 24 ,... are provided. This flag register 24 1,24 2, ..., 24 m, ..., 24 , are the second flag registers 24 of the associative memory shown in FIG. 1,24 It corresponds to 2, ...
[0044]
This associative memory also contains all memory words 11 1,11 2, ..., 11
m, ..., 11 A search line 52 extending across n ... is provided.
Between the search line 52 and the ground, each memory word 11 1,11 2, ..., 11 m, ..., 11 n, two transistors 53 connected in series with each other 1,54 1:53 2,54 2; ...; 53 m, 54 m; ...; 53 n, 54 . are arranged. Two transistors 53 each 1,54 1:53 2,54 2; ...; 53 m, 54 m; ...; 53 n, 54 n; one of the transistors 53 1,53 2, ..., 53 m, ..., 53 The gates of n,... 1,24 2, ..., 24 m, ..., 24 n,... and the other transistor 54 1,54 2,…, 54 m, ..., 54 The gates of n,... are connected to one common control line 55.
[0045]
A lower end of the search line 51 shown in FIG. 1 is a sense amplifier constituting a sense amplifier 56 for detecting the state of charge of the search line 51 and detecting a logic “0” or a logic “1”. It is connected to the input of the inverter 57. The sense amplifier 56 has an input of a sense amplifier inverter 57 and a power supply V._DD, A feedback P-channel transistor 58 whose gate is connected to the output of the sense amplifier inverter 57, and the input of the sense amplifier inverter 57 and the power supply V_DDAnd a precharge P-channel transistor 59 whose gate is connected to the control line 55.
[0046]
The output of the sense amplifier inverter 57 constitutes a hit column register 60. In this embodiment, four flip-flops 60 are provided. 1,60 2,60 3,60 4 is connected. Each flip-flop 60 1,60 2,60 3,60 4, the set pulses S3, S4, S5, and S6 are input for each search that constitutes a series of searches, respectively, and the logic “0” or logic “1” signal output from the sense amplifier 56 is input to each of them. Is stored.
[0047]
Using the associative memory having the above configuration, here,
{(Data C exists in attribute III) and (Data D exists in attribute IV)}
Or
{(Data A exists in attribute I) and (Data B exists in attribute II)} (2)
Shall be searched.
First, the attribute register 12 The attribute III is set to 1 and the input register 12 2 is set to data C, and a first search is performed using attribute III and data C. At this time, the first search timing signal S2 is input.
[0048]
Then, memory word 11 m + 2 and memory word 11 A match is detected at n + 2 and the flag register 24 m + 2 and flag register 24 A logic ‘1’ indicating that a match has been detected is set at n + 2. All other flag registers are reset to logic '0' even if logic '1' is stored.
At this time, a signal of logic “0” is applied to the control line 55 and the search line 52 is precharged through the transistor 59, and the flag register 24 1,24 2, ..., 24 m, ..., 24 When the logic of n,... is determined, the control line 55 changes to logic ‘1’, and the precharge ends and the transistor 54 1,54 2,54 m, ..., 54 are turned on, and the flag register 24 1,24 2, ..., 24 m, ..., 24 If logic “1” is set in any of m,. 1,53 2, ..., 53 m, ..., 53 n,... among the n,... m + 2 and flag register 24 n + 2) (the transistor 53 in the above case). m + 2 and transistor 53 n + 2) is turned on, the charge on the search line 52 is discharged, and the output of the sense amplifier inverter 57 becomes logic "1". When the output of the sense amplifier inverter 57 is determined, the set pulse S3 is input, whereby the flip-flop 60 on the left end of FIG. A logic "1" indicating that a match is detected in the first search is set to 1.
[0049]
Next, the attribute register 12 The attribute IV is set to 1 and the input register 12 2 is set to data D, and a second search is performed using the attribute IV and data D. At this time, the first search timing signal S2 is not input.
In this search, no match is detected, and all flag registers 24 1,24 2, ..., 24 m, ..., 24 are reset to logic "0". That is, the first half of equation (2),
(Data C exists in attribute III) and (Data D exists in attribute IV) (3)
Is not detected.
[0050]
All flag registers 24 1,24 2, ..., 24 m, ..., 24 Since n,... have been reset to logic '0', the inspection line 52 remains in a precharged state, and the logic '0' is output from the sense amplifier inverter 57, and the set pulse S4 is input. And the second flip-flop 60 from the left of the hit column register 60 shown in the figure. 2 is stored with logic ‘0’.
[0051]
Next, a search is performed with the attribute I and the data A, and an initial search timing signal S2 is input, and three memory words 11 5,11 m, 11 n, a match is detected, and the corresponding flag register 24 5,24 m, 24 n is set to logic "1", the logic "1" is output from the sense amplifier inverter 57, and the set pulse S5 is input, and the third flip-flop 60 in the hit column register 60 from the left in FIG. 3 is set to logic "1".
[0052]
Next, a search is performed using the attribute II and the data B, and since the AND search is performed, the first search timing signal S2 is not input. At this time, two memory words 11 m + 1,11 A match is detected at n + 1 and the corresponding flag register 24 6,24 The logic ‘1’ is set to m + 1. At the same time, the flag register 24 5,24 m, 24 n is reset to logic '0'. In addition, the logic "1" is output from the sense amplifier inverter 57 in response to the detection of the match, and the input of the set pulse S6, the right end flip-flop 60 4 stores the logic ‘1’.
[0053]
In the case of the associative memory shown in FIG. 1,24 2, ..., 24 m, ..., 24 Since only the final search result remains in n,..., it is not possible to know an intermediate result by the search as in the above equation (2). In the example of equation (2), after equation (3),
(Data A exists in attribute I) and (Data B exists in attribute II) (4)
Since there is a data group that satisfies the condition (1), it is finally detected that the expression (4) is satisfied even in the associative memory having the configuration shown in FIG. When the expression (3) comes, the associative memory having the configuration shown in FIG. 5 will detect only the mishit in the search result of the latter expression (3).
[0054]
On the other hand, in the embodiment shown in FIG. 1, since the hit example register 60 is provided, the result of each search constituting a series of searches is held, so that various search conditions can be handled. In addition, as shown in FIG. 1, only one system is required to provide the hit string register 60 and its associated circuit over all the memory words constituting the associative memory. Can be added.
[0055]
Although the above embodiment has been illustrated and described as an example of performing a search four times as a series of searches, the present invention is not limited to the case where the four searches are performed as a series of searches. Needless to say, flip-flops constituting the hit string register 60 may be provided in a number of flip-flops equal to or greater than the maximum number of searches constituting a series of searches, and the number of searches as a series of searches may be variably configured.
[0056]
【The invention's effect】
As described above, the associative memory of the present invention includes a hit string register that sequentially stores whether or not a hit flag is stored in any of a plurality of flag registers for each of a plurality of searches. Intermediate search results for each of a plurality of searches making up the search can be collectively known after the series of searches is completed, which contributes to simplification of the system and improvement of the degree of search. In addition, the addition of circuit elements accompanying this is extremely small for the entire associative memory.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a characteristic portion of the present invention in one embodiment of an associative memory of the present invention.
FIG. 2 is a circuit block diagram illustrating an example of an associative memory.
FIG. 3 is a block diagram illustrating an example of an associative memory having a data extension function.
FIG. 4 is a diagram illustrating an example of data of a group structure.
FIG. 5 is a block diagram illustrating an example of an associative memory.
FIG. 6 is a schematic diagram showing one method for realizing a variable-length data line.
FIG. 7 is a schematic diagram showing another method for realizing a variable data line.
FIG. 8 is a circuit diagram illustrating an example of an attribute determination circuit.
[Explanation of symbols]
11_1, 11_2, ... memory words
11_1_1, 11_2_1,... Attribute storage unit
11_1_2, 11_2_2, ... Data storage unit
14_1, 14_2, ... Matching line
16 priority encoder
17 Address decoder
18_1, 18_2, ... word line
20_1, 20_2, ... AND gate
21_1, 21_2, ... or gate
23_1, 23_2,... First flag register
24_1, 24_2, ... second flag register
25 Match result latch control line
30_1, 30_2, ... attribute matching line
31_1, 31_2,... Third flag register
32_1, 32_2, ... data lines
33_1, 33_2, ... 1st switch
34_1, 34_2, ... 2nd switch
52 search line
56 sense amplifier
60-bit string register

Claims (3)

In the associative memory for storing a plurality of stored data and receiving search data, and searching for stored data corresponding to the input search data,
A plurality of memory words for storing a plurality of stored data for each stored data;
At the time of a search provided corresponding to each of the plurality of memory words, there may be a corresponding relationship between the input search data and each of the stored data stored in each of the plurality of memory words. A plurality of flag registers for storing a hit flag indicating the existence of the corresponding relationship when detected;
A hit column register for sequentially storing whether or not the pit flag is stored in any of the plurality of flag registers for each of a plurality of searches. In the associative memory for storing a plurality of stored data and receiving search data, and searching for stored data corresponding to the input search data,
A plurality of storage words each storing a plurality of storage data, each of which forms a plurality of data groups each including a set of a plurality of storage data,
At the time of a search provided corresponding to each of the plurality of memory words, there may be a corresponding relationship between the input search data and each of the stored data stored in each of the plurality of memory words. A plurality of flag registers for storing a hit flag indicating the existence of the corresponding relationship when detected;
When it is detected that there is a correspondence between the stored data stored in the predetermined memory word and the inputted search data, the presence of the correspondence in the flag register corresponding to the predetermined memory word is determined. A first mode for storing a hit flag to be represented, and a data group to which a correspondence relationship is detected in a predetermined first memory word at the time of the current search and to which stored data stored in the first memory word belongs. The hit flag is stored in the flag register corresponding to an arbitrary second memory word other than the first memory word belonging to a memory word group including a plurality of memory words for storing respective stored data to be stored. The hit flag is stored in the flag register corresponding to the first memory word and the second A match detection circuit having a second mode for resetting the hit flag stored in the flag register corresponding to the memory word; and determining whether the hit flag is stored in any of the plurality of flag registers. A hit string storage register for sequentially storing a plurality of searches. Each storage data comprising a pair of an attribute for identifying a plurality of stored data in one data group from each other and data to which the attribute is attached is stored in each of the plurality of memory words, and the attribute and the 3. The associative memory according to claim 1, wherein a search is performed using search data composed of a pair with data.

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