JP3110585B2 - Semiconductor memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention stores a large number of comparison codes corresponding to respective memory areas, receives a reference code from the outside, and stores the contents of the memory area corresponding to the comparison code matching the reference code. For reading semiconductor memory.

[0002]

2. Description of the Related Art Conventionally, semiconductor memories having various structures have been proposed and widely used. As one of those semiconductor memories, there is a method in which a plurality of texts are conceptually arranged in a tree structure while allowing re-appearance, and a predetermined code number is searched according to the arrangement order of the texts. Semiconductor memories to be realized have been conventionally considered. Hereinafter, this method will be described first, and then a semiconductor memory which realizes this method will be described.

[0003]

[Table 1]

[0004]

[Table 2]

Table 1 shows that each text T0, T1, T2, T
3 is a correspondence table of two-bit text codes identified with the texts T0, T1, T2, and T3. Table 2 shows a text chain in which texts are arranged and the text chains. It is a correspondence table with the assigned code number. Here, the 10-bit chain code is a code number represented by a binary code.

FIG. 3 is a diagram showing an example of text arranged in a tree structure. First, two branches extend from the top node (vertex) in the figure, and texts T0 and T1 are arranged at each node beyond each branch. The code number C1 is assigned to the node where the text T0 is arranged, while the code number is not assigned to the node where the text T1 is arranged. From these nodes, three branches further extend from the node where the text T0 is arranged, and texts T0, T1, and T3 are arranged at the nodes ahead of the three branches. Also, code numbers C3, C4, and C5 are assigned to these nodes, respectively. From these nodes, two branches further extend from the node where the text T0 is arranged.
Texts T1 and T2 are provided at each node at the end of the branch.
Are arranged, and code numbers C8 and C9 are assigned to these nodes, respectively. Also at the top,
Two branches extend from the node where the text T1 is arranged, and texts T0 and T2 are arranged at the nodes ahead of the two branches, respectively. Of these nodes, the text T2 is arranged. Code number C
7 is attached. Furthermore, these texts T0, T2
Are respectively extended from each of the nodes on which the text T0 is disposed. The text T0 is disposed at the tip of the branch extending from the node on which the text T0 is disposed, and the code number C10 is assigned. The texts T1 and T3 are arranged at the nodes at the tips of two branches extending from the node where the text T2 is arranged, and the nodes are assigned code numbers C11 and C12.

Here, the method of searching the tree-structured data will be specifically described as follows. First, consider the case where the text chain T0 → T1 is input. At this time, the desired output chain code is '00000000100' as defined in Table 2.

To obtain this result, first, the text T0
Is input as the text code '00'. The text T0 on the tree structure is arranged at the branch destination node of the node number (0) (the node number (0) is the first node number of the search). Text T0 connected to the tip of a branch extending from the node with node number (0)
There is only one, but there are some other nodes where the text T0 is arranged and connected to nodes other than the node with the node number (0).

Therefore, here, in order to recognize that the text input to the tree structure data is the first text T0 of the tree structure, the text data '00' is used.
, And in addition, the search is performed using both the node number (0). The code number C1 (chain code '00000000') is assigned to the node where the text T0 of this branch point is arranged.
01 ') is given, but this time it is not the code number to be obtained.

Next, when text data "01" corresponding to the text T1 is input, the node number (1) (data "0001") of the immediately preceding text T0 and the text data "01" input this time are input. The tree structure database is searched by both. This makes it possible to clearly distinguish the text T1 at another branch from the text T1 at the branch of the node with the node number (1).

Thus, the branch of the text chain T0 → T1 is determined, and the code number C4 (chain code '00000000100') assigned to the tip of the T1 is output as the code number to be obtained. Similarly, any chain codes C1,.
.., C12 can be obtained. FIG. 4 is a diagram showing an example of a semiconductor memory in which this tree-structured database is implemented as hardware.

The decoding unit 20 of the semiconductor memory includes:
Text data input terminals TD0 and TD1 and node number input terminals ND0, ND1, ND2 and ND3 are provided. The node number input terminals ND0, ND1, ND
2 and ND3 are input to the node number setting circuit 22. A node number data output 26 from the memory unit 25 is also connected to the node number setting circuit 22, and the output is switched by an output switching terminal SW1.

The numbers written at the left end of the decoding unit 20 are the node numbers (1),
(2), (3),..., (12). For example, the node number (1) in the bottom row represents a node in the upper part of the tree structure data in FIG. 1 where the text T0 is arranged. In the decoding unit 20, a line segment corresponding to each node extending in the horizontal direction to the coincidence detection circuit 21 and a text data input terminal TD extending in the vertical direction are provided.
0, TD1 data line and node number setting circuit 2
Data lines from 2 intersect. When the intersection is indicated by a black circle, the data of the data line is the normal data "1", and when there is no black circle, the data line is the inverted data "0". 21
Is set to '1' (active). That is, the node number (1) corresponds to the text data input terminals TD0 and TD1 and the node number setting circuit 2
When all of the outputs from 2 are '0', the output of the match detection circuit 21 corresponding to the node number (1) is '1'.

Here, the node number setting circuit 22 has
The node number (0) of the node at the vertex shown in FIG.
00 ') is set, and in this state, when the data' 00 'of the text T0 is input from the text data input terminals TD0 and TD1, the output of the coincidence detection circuit 21 corresponding to the node number (1) becomes'1'. Become. Then, the lowermost row (memory area) of the memory section 25 on the right side of the figure becomes active, and the output of the output circuit 28 having the intersection where the white circle 27 exists becomes “1”. Specifically, node number data output 2
6 to '0001', code valid bit output 29 to '1', and chain code data output 30 to '
00000000001 'is output. Here, the code valid bit output 29 indicates whether the data output from the chain code output 30 is valid or invalid. That is, the code number is assigned to the node with the node number output from the node number data output 26. Indicates whether or not it is attached. Here, since the code valid bit output 29 is “1”, the data output from the chain code data output 30 is valid. However, here, the data output from the chain code output 30 is a code number to be obtained. do not use. The data '0001' output from the node number data output 26 is input to the node number setting circuit 22.

Next, text data input terminals TD0, T
When data '01' of text T1 is input to D1,
Since the output of the node number setting circuit 22 is the value “0001” from the previous search result of the text T0, the input of the decoding unit 20 is now “010001”.
A match in this pattern is the node number (4) where the text T1 is arranged (see FIG. 3). As a result, the output of the match detection circuit 21 corresponding to the node number (4) becomes'
1 ′, and the fourth row from the bottom of the memory unit 25 becomes active. Therefore, the code valid bit output is
1 ', chain code data output is'00000001'
00 ', and finally this chain code is obtained as a code number. At this time, node number data '0100' is obtained at the same time, but this is not used here.

As described above, by referring to both the input data and the node number, even when a large number of branches are branched from each node, high-speed search and match comparison are performed. Here, it is desirable that the coincidence detection circuit section 20 be configured such that only one row of the output of the coincidence detection circuit 21 for each search data becomes “1”. if,
If this is not realized and the configuration is such that the outputs of the plurality of coincidence detection circuits 21 are 1 'at the same time, the method of determining the data in the memory unit 25 becomes complicated. Of course, it is also possible to configure the hardware so that the outputs of the plurality of coincidence detecting circuits 21 are simultaneously set to "1", and the plurality of outputs which are simultaneously set to "1" are sequentially output one by one. However, the hardware cost can be reduced by devising a method of creating tree-structured data so that only one output becomes “1” at the same time.

FIG. 5 is a circuit diagram showing a part of the semiconductor memory shown in FIG. 4, and FIG. 6 is a circuit diagram further embodying the circuit shown in FIG. FIG. 5 and FIG.
0111 'input data (text data' 11 'and output from node number setting circuit 22 are' 0111 ')
5 is a circuit diagram corresponding to the node number (12) in FIG. 4 in which the output of the match detection circuit 21 is “1”.

As shown in FIG. 6, a decoding unit 20 includes a coincidence detecting circuit 21 and seven transistors Tr1, Tr2, Tr3, Tr4, Tr4 connected in series with each other.
5, Tr6; Tr11, and includes a large number of coincidence comparison circuits 201. These seven transistors Tr1, Tr2, Tr3, Tr4, Tr5, Tr6; T
r11, six transistors Tr1, Tr2, Tr
Data line DL is applied to each gate of Tr3, Tr4, Tr5 and Tr6.
1, DL2, DL3, DL4, DL5, DL6 and data bar lines DBL1, DBL2, DBL3, DBL4
One of DBL5 and DBL6 is connected. Further, a precharging transistor Tr10 is provided, and this transistor Tr10 is a P-channel transistor for precharging at the potential of the point A. The transistor Tr11 is an N-channel transistor provided between the transistor Tr1 and the ground line, and suppresses the discharge of the potential at the point A during the precharge.
The match detection circuit 21 is connected to the inverter 211 and the feedback P
It is composed of a channel transistor Tr12.

In the memory unit 25, the inverter 21
1 are output from the memory transistors MTr1, MTr2,
It is connected to each gate of MTr3 and MTr4. These memory transistors MTr1, MTr2, MTr3,
MTr4 has one data output line DOL3 and one data output line DOL.
4, DOL5 and DOL6, and the other is connected to a ground line.

Further, each of the data output lines DOL1,.
, DOL15 are provided at one end with precharging P-channel transistors PTr1,..., PTr15, and at the other end with an inverter 251 and a feedback P-channel transistor Tr13.
Here, first, a precharge control terminal 31 for initialization
Is applied, the potential at the point A is set to "1". Accordingly, the output of the coincidence detecting circuit 21, which is the inverter output of the potential at the point A, becomes "0". When the output of the coincidence detection circuit 21 becomes “0”, each of the memory transistors MTr1, MTr2, MTr3, and MTr4 is turned off, and when “0” is applied to the precharge control terminal 31, the precharge P , PTr15 are turned on, and each data output line DOL1,..., DOL15 maintains the state of “1”, and the inverter 251 which is the inverter output thereof
Keep the state of '0'. At this time, the code valid bit output also outputs '0'. By this signal output, it can be known that the output of the chain code data is invalid data.

Next, the text data input terminals TD0, TD0,
When the desired input data is applied from TD1 and the output from the node number setting circuit 22 is determined, and then "1" is applied to the precharge control terminal 31, a search state is entered. By repeatedly performing the initialization state and the search state in synchronization with the application of each input data, desired chain code data, that is, a code number can be obtained.

The above is an example of a conventional semiconductor memory for storing tree-structured data. When a semiconductor memory having a large memory capacity is configured, the memory area is reduced for the purpose of reducing power consumption during operation and the like. Is often divided into a plurality of blocks. FIG. 7 is a circuit diagram showing an example of a configuration in which the above-described semiconductor memory suitable for storing tree-structured data is divided into blocks, and FIG. 8 is a partially enlarged view of FIG. 7 for easy understanding. It is a circuit diagram.

In this semiconductor memory, a memory section 31 divided into n blocks, in which a large number of memory areas each consisting of memory cells for one word (m bits) are collected. 1,3
1 2, ..., 31 n and a decoding unit 32 1,32 2, ..., 32 n is also in each memory unit 31
1,31 2, ..., 31 It is divided into n parts corresponding to n. Each memory unit 31 1,31 2, ...,
31 n, each of the decoding units 3
2 1,32 2, ..., 32 Each word line 34 extends one by one from n.

Each memory unit 31 1,31 2, ..., 31
n, each highest-order memory cell constituting each memory area
Bit line 36 extending to 1 1,36 2 1, ..., 3
6 n 1 is each transistor 38 1 1,38 2
1, ..., 38 n 1 through the sense amplifier 40 In one
Connected, each of the second highest
Bit line 36 extending to memory cell 1 1,36 2
2, ..., 36 n 2 is a transistor 38 1
2,38 2 2, ..., 36 n Sensea via 2
Amp 40 2 and so on.
Line 3 extending to each lowermost memory cell constituting the area
6 1 m, 36 2 m, ..., 36 n m is each tran
Vista 38 1 m, 38 2 m, ..., 38 n m
Via the sense amplifier 40 m. this
Each transistor 38 1 1,38 1 2, ..., 3
8 1 m; 38 2 1,38 2 2, ..., 38
2 m; ...; 38 n 1,38 n 2, ..., 38 n
The gate of m is each block provided for each block.
Selection circuit 50 1,50 2, ..., 50 construct n
Inverter 52 1,52 2, ..., 52 output of n
It is connected. In addition, this inverter 52 1,52
2, ..., 52 The input of n is two P-type transistors 54
1,56 1; 54 2,56 2; ...; 54 n,
56 Power supply V through n_ppIs connected to These two
One P-type transistor 54 1,56 1; 54 2,
56 2; ...; 54 n, 56 P type of one of n
Transistor 54 1,54 2,…, 54 game of n
Is connected to the precharge line 58 and the other P-type
Transistor 56 1,56 2, ..., 56 game of n
The inverter 52 1,52 2, ..., 52 out of n
Connected with power.

Each inverter 52 1,52 2,
..., 52 Each sensing line 60 connected to the input of n
1,60 2, ..., 60 n is provided extending vertically in the figure.
Each sensing line 60 1,60 2, ..., 60
n indicates that at each intersection with each word line 14, the gate
Each transistor 62 connected to the word line 1,62
2, ..., 62 n is grounded.

In the semiconductor memory configured as described above, reading is performed as follows. First, the precharge line 58 is set to the state of logic '0'. At this time, each word line 34 is in the state of logic '0'. Thereby, each P-type transistor 54 1,54 2,…, 54 n through each sensing line 60 1,60 2, ..., 60
n is precharged. Then the precharge line 58
Is returned to the state of logic '1'.

Next, a reference code RC is input from outside. This reference code RC corresponds to the row decoder 32 1,32
2, ..., 32 The comparison signal of each memory area stored in n is compared with the reference code, and if it matches the reference code, a code signal is output to the corresponding word line 34 because of the logic “1”. Here, the uppermost word line 34a of the leftmost block in the figure
It is assumed that a decoded signal of logic '1' has been output to the.
At this time, the transistor 62a whose gate is connected to the word line 34a 1 becomes conductive and the sensing line 60
The charge that has been precharged to 1 1 and the sensing line 60 is discharged. 1 becomes the state of logic '0'. This sensing line 60 The logic '0' of 1 1 and the inverter 52 1 outputs a hit signal of logic '1' indicating that a comparison code matching the reference code exists. This hit signal causes the transistor 38 1 1,38 1 2, ..., 38 1
m becomes conductive and these transistors 38 1
1,38 1 2, ..., 38 1 m through the memory array unit 31 1 memory cell is a sense amplifier 40
1,40 2, ..., 40 m. Therefore, the content stored in the memory area corresponding to the word line 34a is 1 1,36 1 2, ..., 36
1 via the transistor 38 1 1,38 1
2…, 38 1 m and the sense amplifier 4
0 1,40 2, ..., 40 m and the output terminal 64 1,64 2, ..., 64 m.

[0028]

As shown in FIG. 7, the memory unit 31 is divided into a plurality of blocks. 1,32 2, ...,
31 n and the decoding unit 32 1,32 2, ..., 32
In a semiconductor memory provided with n and allowing only one comparison data that matches the reference data RC, if there are a plurality of comparison data that match the input reference data RC, the storage contents of the plurality of memory areas are superimposed. Output, and a correct output cannot be obtained. This problem arises when designing this semiconductor memory based on the specification of specific tree structure data, as shown in FIG. 6, by connecting data lines DL1, DL2,. Which of DL6 and data bar lines DBL1, DBL2,..., DBL6 are to be connected is determined.
Even if the design is correct, each transistor Tr1, T
r,..., Tr6 gates and data lines DL1, DL2,
, DL6 and data bar lines DBL1, DBL2, ..., D
It occurs when connection with BL6 is not performed normally. In such a case, in order to increase the efficiency of the failure analysis, it is preferable to immediately determine that the memory areas have been selected at the same time.

The present invention has been made in view of the above circumstances, and has as its object to provide a semiconductor memory in which failure analysis is made more efficient.

[0030]

According to the present invention, there is provided a semiconductor memory having a memory section having a large number of memory areas each including a predetermined number of memory cells, and a comparison code corresponding to each of the memory areas. In a semiconductor memory including a plurality of blocks each including a pair with a decoding unit that selects a memory area corresponding to a comparison code that matches a reference code by comparing with an input reference code, (1) Matching with the input reference code A hit detection circuit provided in each of the blocks to generate a hit signal indicating that a comparison code to be executed exists; and (2) generating a hit signal indicating that the hit signal has been generated by the plurality of hit detection circuits. First multiple hit detection circuit to be generated (3) The comparison code that matches the input reference code is 1
A second multi-hit signal generation method that excludes a case where a plurality of blocks exist in one of the blocks and excludes a case where only one or less comparison codes matching the input reference code exist in all blocks. And two multiple hit detection circuits.

[0031]

The semiconductor memory of the present invention has a
Sensing wire 60 1,60 2, ..., 60 n and inva
Data 52 1,52 2, ..., 52 as indicated by n
A simple hit detection circuit is provided for each block (see above).
(1)), the output of the hit detection circuit for each of those blocks
And a hit signal is output from multiple hit detection circuits.
1st multiple hit detection circuit (upper
(2)). However, this alone
Indicates that multiple memory areas in the same block are selected
No case is detected.

Therefore, the semiconductor memory of the present invention is further provided with the second multiple hit detecting circuit of the above (3), thereby detecting a case where a plurality of memory areas in the same block are selected. . The second multiple hit detection circuit covers the case where a plurality of memory areas in one block are selected, as shown in (3) above, and covers the normal case, that is, over all the blocks. It suffices that the case where only one memory area is selected or the case where no memory area is selected over all blocks is excluded. In other cases, that is, when a plurality of memory areas are selected across a plurality of blocks, the second plurality of hit detection circuits can be detected by the first plurality of hit detection circuits of (2). Then, this case may not be detected, or a part of this case may be detected by overlapping the first multiple hit detection circuit.

[0033]

Embodiments of the present invention will be described below. FIG.
1 is a circuit diagram of an embodiment of a semiconductor memory according to the present invention.
Here, to avoid complexity, the memory, decoding,
The hit detection circuit is shown only for one block, and a part thereof is omitted.

In each block, a large number of word lines 34 are transferred from the decode unit 32 to the corresponding memory unit 31 in the horizontal direction of the drawing.
Extends to. In addition, a large number of sensing lines 260 extend across all the blocks in parallel with the word lines 34 and reach the second multiple hit detection circuit 300. A sensing line 60 constituting the hit detection circuit 100 extends vertically between the decoding unit 32 and the memory unit 31 and is connected to a first sense amplifier 68. Each transistor 62 is connected to each intersection of the sensing line 60 and each word line 34 as shown. Also,
Each word line 34 has a logic '1'
A number of word sensing circuits 262 are connected to transmit a signal of logic “1” to the corresponding sensing line 260 when a signal of (H level) is output.

Prior to the search operation, the sensing line 60 is supplied with a charge from the power supply of the first sense amplifier 68 and is precharged. When the search is started, if there is comparison data that matches the reference data, the corresponding word line 3
4 changes from logic '0' (L level) to logic '1' (H level), the transistor 62 whose gate is connected to the word line 34 turns on, and the electric charge of the sensing line 60 passes through the transistor 62. Is discharged, and the first sense amplifier 68 outputs a logic '1' hit signal indicating that comparison data matching the reference data was present in the block. In addition, the sensing line 260 corresponding to the word line 34 that has changed to the logic “1” at the same time is charged via the corresponding word line sensing circuit 262 to become the logic “1”.

On the other hand, when there is no comparison data that matches the reference data in the block, the output of the first sense amplifier 68 stays at logic "0" and the word line sensing circuit 262 in the block. In some cases, the sensing line 260 is not charged. However, the sensing line 260 may be charged by the word line sensing circuit 262 provided in another block. The hit detection circuit 100 as described above is provided for each of a plurality of blocks.
0 (the first sense amplifier 68) is input to the OR circuit 70, which indicates whether one or more pieces of comparison data that match the input reference data exist or do not exist. Hit / miss hit signal H / MH for the entire semiconductor memory Is output.

The output signal of the hit detection circuit 100 provided for each block is also input to the first multiple hit detection circuit 200. First multiple hit detection circuit 20
In 0, the detection side bit line 102 and the reference bit line 104
Is extending. The detection bit line 102 is grounded through a number of transistors 106 corresponding to the number of blocks, and the gates of these transistors 106 have hit detection circuits 100 (first sense amplifiers 68) of each block.
Output is connected. Also, this detection bit line 10
2 is a precharge P-channel transistor 108
To the power supply Vdd. The gate of the precharge P-channel transistor 108 is connected to the precharge line 58.

The reference bit line 104 is also grounded via a number of transistors 110 and 112. The gate of the leftmost transistor in the figure is connected to the precharge line 58, and the gates of the other transistors 110 are grounded. I have. The transistor 110 is a transistor for equalizing the load capacitance with the detection amount bit line 102 side, and the transistor 112 is a reference side current draw transistor. The wire drawing transistor 112 has 1.5 times the current drawing capability of each of the detection-side transistors 106. Like the detection bit line 102, the reference bit line 104 is connected to the power supply Vdd via the precharge P-channel transistor 114, and the precharge P-channel transistor 11
4 is connected to the precharge line 58.

Detection bit line 102 and reference bit line 1
04 is connected to the second sense amplifier 120,
The input sections of the sense amplifier 120 are connected to each other via an equalizing P-channel transistor 116. The gate of the equalizing P-channel transistor 116 is also connected to the precharge line 58.

The reference bit line 104 is short-circuited, and the input section of the sense amplifier 120 is completely kept at the same potential. Thereafter, when the output of the hit detection circuit 100 provided for each block is determined, the potential of the precharge line 58 is set to the H level. Then, due to the difference in current drawing capability between each transistor 106 and transistor 112 (the transistor 112 has 1.5 times the current drawing capability as described above), a hit signal (logic “1”) is output from only one block. ) Is output, the discharge speed of the reference bit line 104 is faster than the discharge speed of the detection bit line 102, and therefore, the output Y1 of the sense amplifier 120 becomes logic '0' (L).
Level). On the other hand, when the hit signal is output from two or more blocks, the discharge of the detection bit line 102 is performed by the plurality of transistors 106. Therefore, the discharge speed of the detection bit line 102 is higher than that of the reference bit line. Therefore, the output Y1 of the sense amplifier 120 becomes logic "1" (H level).

The second multiple hit detection circuit 300
Has the same structure as the multiple hit detection circuit 200 of
Although detailed description is omitted, the second multiple hit detection circuit 3
A sensing line 260 extending over a plurality of blocks is connected to the gate of each transistor 206 connected to the detection bit line 202 that constitutes 00, and one of the sensing lines 260 has a logic “1”. (H level), the detection bit line 202 is discharged.
The transistor 2 connected to the reference bit line 204
12 indicates each transistor 20 on the detection amount bit line 202 side.
It has 1.5 times the current drawing capacity of 6. As a result, when there is no comparison data that matches the reference data input from the outside and none of the sensing lines 260 remains at logic “0” (L level), or
Only one sensing line 260 is logic '1' (H level)
, The output Y2 of the sense amplifier 220 becomes logic “0”, and the plurality of sensing lines 260 become logic “0”.
When it becomes "1", the output Y2 of the sense amplifier 220 becomes logic "1".

The outputs Y1 and Y2 of the first and second plural hit detection circuits 120 and 220 are used to determine the final output Y3.
If there is no comparison code that matches the reference code or if there is only one comparison code, it is logical "1".
(H level), a signal of logic '0' (L level) is obtained when there are abnormalities in which a plurality of comparison codes coincide with the reference code, whereby normal / abnormal can be immediately identified.

FIG. 2 is a circuit diagram of another embodiment of the present invention. The same elements as those in the embodiment shown in FIG. 1 are denoted by the same reference numerals as those in FIG. 1, and only different points will be described. In the embodiment shown in FIG. 2, the hit detection circuit 100 and the second multiple hit detection circuit 30 are provided for each block.
0 'is provided, and the signal Y2 is obtained by collecting the outputs of the second multiple hit detection circuit 300' for each block.
Has been generated. Based on the signal Y2 and the output Y1 of the first multiple hit detection circuit 200, the final output Y3 is a logical "1" (H level) in a normal case, and a logical "0" (L level) in a abnormal case of multiple hits. Is obtained.

[0044]

As described above, the semiconductor memory of the present invention detects the output of a plurality of hit signals from the output of the hit detection circuit provided for each block, and detects the first plurality of hit signals. And a case where a plurality of comparison codes matching the input reference code exist in one block, and all the comparison codes matching the input reference code Since there is provided a second multiple hit detection circuit for generating a second multiple hit signal that excludes a case where only one or less exists over a block, an abnormal state in which a plurality of memory areas are simultaneously selected can be immediately identified. .

[Brief description of the drawings]

FIG. 1 is a circuit diagram of an embodiment of a semiconductor memory according to the present invention.

FIG. 2 is a circuit diagram of another embodiment of the present invention.

FIG. 3 is a diagram illustrating an example of text arranged in a tree structure.

FIG. 4 is a diagram illustrating an example of a semiconductor memory in which a database having a tree structure is implemented as hardware.

FIG. 5 is a circuit diagram showing a part of the semiconductor memory shown in FIG. 4;

FIG. 6 is a circuit diagram further embodying the circuit shown in FIG. 5;

FIG. 7 is a circuit diagram showing a configuration example when a semiconductor memory suitable for storing tree-structured data is divided into blocks;

FIG. 8 is an enlarged circuit diagram showing a part of FIG. 7;

[Description of Signs] 31 Memory unit 32 Decoding unit 100 Hit detection circuit 200 First multiple hit detection circuit 300, 300 'Second multiple hit detection circuit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) G11C 15/00-15/06 WPI (DIALOG)

Claims (1)

(57) [Claims] 1. A memory section having a large number of memory areas each including a predetermined number of memory cells, storing a comparison code corresponding to each of the memory areas, comparing the input code with a reference code, and matching the reference code. In a semiconductor memory including a plurality of blocks each including a pair with a decoding unit that selects the memory area corresponding to a comparison code, generating a hit signal indicating that a comparison code matching the input reference code exists. A hit detection circuit provided for each of the blocks; a first multiple hit detection circuit for generating a first multiple hit signal indicating that the hit signal has been generated by the plurality of hit detection circuits; A case where a plurality of comparison codes matching the code exist in one block is covered. A semiconductor memory, comprising: a second multiple hit detection circuit that generates a second multiple hit signal that excludes a case where only one or less matching comparison codes exist in all blocks.