JP2875126B2 - Encoding device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an encoding apparatus suitable for quickly obtaining and outputting a code number determined by an arrangement order of a plurality of texts arranged in a tree structure, and particularly to an encoding apparatus with low power consumption. About.

[0002]

2. Description of the Related Art Various application techniques of a semiconductor memory have been proposed. One of them is as follows.
Each text is arranged at each node of the tree structure to allow re-appearance, and a code number is assigned to each node as necessary, and a code assigned to a node existing after tracing the branch of this tree structure An encoding device has been proposed which converts a text chain in which texts are arranged in an order along a tracing route into a code number by obtaining a number (Japanese Patent Application No. 4-87219).

[0003] A description will now be given of the technology on which the present invention is based along this encoding apparatus.

[0004]

[Table 1]

[0005]

[Table 2] ──────────────────────────────────── Text chain code number Chain code (10 bits) T0 C1 0 0 0 0 0 0 0 0 0 1 1 T0 → T0 C3 0 0 0 0 0 0 0 0 0 0 1 0 T0 → T1 C4 0 0 0 0 0 0 0 0 1 0 0 T0 → T3 C5 0 0 0 0 0 0 1 0 0 0 T1 → T2 C700 0 0 0 0 0 1 0 0 0 0 T0 → T0 → T1 C8 0 0 0 0 0 1 0 0 0 0 0 T0 → T0 → T2 C9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T1 → T0 → T0 C10 0 0 0 0 0 0 0 0 0 T1 → T2 → T1 C1 1 1 1 0 0 0 0 0 0 0 0 0 T1 → T2 → T3 C12 1 0 0 0 0 0 0 0 0 0 0 ────────────────────────────────── Table 1 And each text T0, T1, T2, T3, each of these text T0, T1, T2, T3 and 2 to be identified
It is a correspondence table with a text code consisting of bits.
Is a correspondence table of text chains in which texts are arranged and code numbers assigned to the text chains. Here, the 10-bit chain code is a code number represented by a binary code.

Here, the data structure handled by the encoding device according to the above proposal will be described first. FIG.
FIG. 3 is a diagram illustrating an example of text arranged in a tree structure. In this figure, the numbers in parentheses indicate the node numbers assigned to the respective nodes. First, two branches extend from the node (vertex) assigned the node number (0) at the top of the figure,
Each text T0, T1 is arranged at each node ahead of each branch. The code number C1 is assigned to the node of the node number (1) in which the text T0 is arranged,
On the other hand, the code number is not assigned to the node of the node number (2) in which the text T1 is arranged. From these nodes, three branches further extend from the node of node number (1) where the text T0 is arranged, and the texts T0, T1 and T3 are arranged at the nodes ahead of the three branches. Have been. Also, code numbers C3, C4, and C5 are assigned to these nodes, respectively. Two branches extend from the node of node number (3) in which the text T0 is arranged among these nodes.
Texts T1 and T2 are respectively arranged at the nodes of the node numbers (8) and (9) at the end of the branch, and code numbers C8 and C9 are assigned to these nodes, respectively. Also, two branches extend from the node of the node number (2) where the text T1 is disposed, and texts T0 and T2 are disposed at the nodes ahead of the two branches, respectively. Of the nodes of the node number (7) where the text T2 is arranged, the code number C
7 is attached. Furthermore, these texts T0, T2
Are extended from each of the nodes on which the text T0 is arranged, and the tip of the branch extending from the node with the node number (6) where the text T0 is arranged, and the node with the node number (10) is the text T0. Is arranged, and the code number C10
Are attached to each of the nodes of the node numbers (11) and (12) at the ends of two branches extending from the node of the node number (7) where the text T2 is arranged.
T3 is arranged, and code numbers C11 and C12 are assigned to these nodes.

Here, the encoding method using the tree-structured data will be specifically described as follows. First, consider the case where the text chain T0 → T1 is input. In this case, the desired output chain code is “00000000100” as defined in Table 2.
It is.

To obtain this result, first, the text T0
Is input as the text code '00'. The text T0 on the tree structure is arranged at the branch destination node of the node number (0) (the node number (0) is the first node number of encoding). Text T connected to the tip of a branch extending from the node with node number (0)
Although there is only one 0, there are some other nodes in which the text T0 is arranged and connected to nodes other than the node with the node number (0).

Therefore, here, in order to recognize that the text input to the tree structure data is the first text T0 of the tree structure, the text data '00' is used.
And the node number (0) (data '000
0 '). Note that the text T of this branch is
A code number C1 (chain code '00000000001') is given to the node where 0 is arranged.
This time, it is not the code number to be sought.

Next, when text data "01" corresponding to the text T1 is input, the node number (1) (data "0001") of the immediately preceding text T0 and the text data "01" input this time are input. The tree structure database is searched by both. This makes it possible to clearly distinguish the text T1 at another branch from the text T1 at the branch of the node with the node number (1).

Thus, the branch of the text chain T0 → T1 is determined, and the code number C4 (chain code '00000000100') assigned to the tip of the T1 is output as the code number to be obtained. Similarly, any chain codes C1,.
.., C12 can be obtained. The encoding device according to the above proposal is an effective device for handling tree-structured data as shown in FIG. 5, in which each node of the tree structure is assigned a node number, and the input text and the current position are assigned. It is configured to determine the node to proceed to next based on the node number of the node to be executed. For this reason, even if a large number of branches extend from the node at the current position, unlike the case where the branches are sequentially searched, a node to be immediately advanced is found by one search operation, and therefore the text chain is extremely large. It has the feature that it is converted to a code number in a short time.

FIG. 6 is a diagram showing an example of an encoding device according to the above proposal. The decoder unit 20 of this encoding device is provided with text data input terminals TD0 and TD1, and node number input terminals ND0, ND1, ND2 and ND3. The node number input terminals ND0, ND1, N
Data input from D2 and ND3 is input to the node number setting circuit 22. The node number setting circuit 22
Is also connected to a node number data output 26 from the memory unit 25, and the input is switched by an input switching terminal SW.

The numbers written at the left end of the decoder section 20 are the node numbers (1),
(2), (3),..., (12). For example, the node number (1) in the bottom row represents the node in the upper part of the tree structure data in FIG. 5 where the text T0 is arranged. In the decoder section 20, a line segment extending in the left-right direction to the coincidence detection circuit 21 and corresponding to each node, and a text data input terminal TD extending in the vertical direction.
0, TD1 data line and node number setting circuit 2
Data lines from 2 intersect. At the intersection, a black dot is displayed when the data of the data line is normal data '1', and a data without the black circle is when the data of the data line is inverted data '0'. The output of the detection circuit 21 is configured to be “1” (active). That is, when the output from the text data input terminals TD0 and TD1 and the node number setting circuit 22 are all "0", the output of the coincidence detecting circuit 21 corresponding to the node number (1) is the node number (1). It becomes '1'. Here, the node number (0) (data '000) of the node at the vertex shown in FIG.
0 '), and the text data input terminal T
When data "00" of the text T0 is input from D0 and TD1, the match detection circuit 2 corresponding to the node number (1)
The output of 1 becomes '1'. Then, the lowermost row of the memory unit 25 on the right side of the figure becomes active, and the output of the output circuit 28 connected to the intersection where the white circle 27 exists becomes “1”. Specifically, from the node number data output 26 to '00
01 ', code valid bit output 29 to' 1 ', and chain code data output 30 to' 000000 '
0001 'is output. Here, the code valid bit output 29 indicates whether the data output from the chain code output 30 is valid or invalid. That is, the code number is assigned to the node with the node number output from the node number data output 26. Indicates whether or not it is attached. Here, this code valid bit output 29 is
Since it is 1 ', the data output from the chain code data output 30 is valid, but here, the data output from the chain code output 30 is not used as a code number to be obtained. The data '0001' output from the node number data output 26 is input to the node number setting circuit 22.

Next, text data input terminals TD0, T
When data '01' of text T1 is input to D1,
Since the output of the node number setting circuit 22 is the value “0001” from the previous search result of the text T0, the input of the decoder unit 20 is now “010001”.
A match in this pattern is the node number (4) where the text T1 is arranged (see FIG. 5). As a result, the output of the match detection circuit 21 corresponding to the node number (4) becomes'
1 ′, and the fourth row from the bottom of the memory unit 25 becomes active. Therefore, the code valid bit output is
1 ', chain code data output is'00000001'
00 ', and finally this chain code is obtained as a code number. At this time, node number data '0100' is obtained at the same time, but this is not used here.

As described above, by referring to both the input data and the node number, even when a large number of branches are branched from each node, high-speed search and comparison can be performed, and encoding is performed. Speedup is realized. FIG. 7 is a circuit diagram showing a part of the encoding device shown in FIG.
FIG. 8 is a circuit diagram further embodying the circuit shown in FIG.
FIGS. 7 and 8 show the match detection circuit 21 for input data of “110111” (text data “11” and output from the node number setting circuit 22 of “0111”).
6 is a circuit diagram corresponding to the node number (12) in FIG.

As shown in FIG. 8, the decoder section 20 includes six transistors Tr1 and Tr1 connected in series to each other.
Each data line DL1, DL2, DL3, DL4, DL5 is connected to each gate of Tr2, Tr3, Tr4, Tr5, Tr6.
DL6 or each data bar line DBL1, DBL2, D
One of BL3, DBL4, DBL5, and DBL6 is connected. Further, precharge transistors Tr10 and Tr11 are provided at two locations. Of these, the transistor Tr10 is a P-channel transistor for precharge at the point A potential. The transistor Tr11 is an N-channel transistor provided between the transistor Tr1 and the ground line, and suppresses the discharge of the potential at the point A during the precharge. The coincidence detecting circuit 21 includes an inverter 20 'and a feedback P-channel transistor Tr12.

In the memory unit 25, the inverter 2
0 ′ is output from the memory transistors MTr1, MTr
2, MTr3, and MTr4.
These memory transistors MTr1, MTr2, MTr
3 and MTr4, one of which is a data output line DOL3, DO
L4, DOL5, DOL6 and the other are connected to a ground line.

Further, each of the data output lines DOL1,.
, DOL15 are formed at one end with precharging channel transistors PTr1,..., PTr15, and at the other end with an inverter 21 ′ and a feedback P-channel transistor Tr13. Here, first, a precharge control terminal 31 for initialization
Is applied, the potential at the point A is set to "1". Accordingly, the output of the coincidence detecting circuit 21, which is the inverter output of the potential at the point A, becomes "0". When the output of the coincidence detection circuit 21 becomes “0”, each of the memory transistors MTr1, MTr2, MTr3, and MTr4 is turned off, and when “0” is applied to the precharge control terminal 31, the precharge P The channel transistors PTr1,..., PTr15 are turned on, the data output lines DOL1,..., DOL15 maintain a state of “1”, and the inverted output of the inverter 21 ′ maintains a state of “0”. At this time, the code valid bit output also outputs '0'. By this signal output, it can be known that the output of the chain code data is invalid data.

Next, text data input terminals TD0, TD0,
When the desired input data is applied from TD1 and the output from the node number setting circuit 22 is determined, and then "1" is applied to the precharge control terminal 31, a search state is entered. By repeatedly performing the initialization state and the search state in synchronization with the application of each input data, desired chain code data, that is, a code number can be obtained.

The above is an example of the encoding device according to the above proposal.

[0021]

In order to reduce the power consumption of the semiconductor memory, the semiconductor memory is provided with a structure divided into a plurality of circuit blocks instead of being always in an active state. A method of activating only a circuit block to which an address belongs according to address data has been considered.

However, in the case of the encoding device as described above,
The input is not the address data but the input data consisting of the text data and the node number.
5 has a structure in which the address (node number) 5 is generated by the decoder unit 20, even if the above-described encoding device is divided into a plurality of circuit blocks and configured, depending on the input data, It is not clear whether the active state should be set to the active state. Therefore, it is not possible to adopt a method of selecting a circuit block to be activated based on input address data (input data) employed in a conventional semiconductor memory. .

In view of the above circumstances, according to the present invention, for example, when a structure in which the above-described encoding device is divided into a plurality of circuit blocks is provided, a circuit block to be in an active state can be determined, thereby reducing power consumption. It is an object to provide an implemented coding device.

[0024]

According to the encoding apparatus of the present invention which achieves the above object, each text is arranged at each node of a tree structure allowing re-appearance, and a code number is assigned to each node as necessary. By calculating the code number assigned to the node existing at the end of tracing the branch of the tree structure,
The present invention relates to an encoding device for converting a text chain in which texts are arranged in an order along a route followed to a code number, and (1) a decoder which receives input data and specifies a node corresponding to the input data Unit (2) A memory unit having a large number of memory areas corresponding to each node and outputting the stored contents of the memory area corresponding to the node specified by the decoder unit (3) Inputting input data to the decoder unit and inputting data from the memory unit A plurality of circuit blocks with block numbers are provided, each having a state switching section for switching between an active state in which the output of stored contents is permitted and an inactive state in which these inputs and outputs are shut off.

Here, the decoder section constituting each of the circuit blocks includes: a) a text input section for inputting text as part of input data; b) input of a node number assigned to each node as part of input data. C) a node number input unit for specifying a node corresponding to the input data based on input data consisting of a text and a node number.

The memory unit constituting each of the circuit blocks includes: (a) a node number assigned to the node from a memory area corresponding to the node designated by the node designation unit, (B) A code number output unit that outputs a code number assigned to the node from a memory area corresponding to the node specified by the node specifying unit. (C) A node specified by the node specifying unit. And a block number output unit for outputting the block number of the next active circuit block assigned to the node from the memory area corresponding to the block number and inputting the block number to the state switching unit.

In the coding apparatus of the present invention, 2
The same block numbers may be assigned to the above circuit blocks. The block number may be fixedly determined for each circuit block, or may be configured to be externally loaded before data search.

[0028]

The coding apparatus according to the present invention includes a plurality of circuit blocks, and stores the block number of the next circuit block to be activated in each memory area constituting the memory section of each circuit block. When a certain memory area is searched, a block number stored in the memory area is output, and this block number is switched between an active state and an inactive state of each circuit block. Since each circuit block is configured to be input to each section, each state switching section constituting each circuit block switches its own circuit block to an active state or an inactive state based on the input block number. As a result, only the circuit blocks necessary for searching for the code number can be set in the active state, and a low power consumption type encoding device is realized.

[0029]

Embodiments of the present invention will be described below. FIG. 1 is a diagram illustrating an example of text arranged in a tree structure. The difference from the tree structure shown in FIG. 5 is that a block number is assigned by enclosing the information corresponding to each node in which of the plurality of divided circuit blocks the information corresponding to each node is stored. If necessary, the block number (encircled number) of the circuit block in which the information of the node immediately downstream of the point and the node where each text is arranged is stored, if necessary, It is a point that is attached.

When searching for a code number, a circuit block having a block number 0 among a plurality of circuit blocks is first activated, and for example, a search is performed for a node having a node number (1). Since the node with the node number (1) is assigned the block number 1, the circuit block with the block number 1 is activated this time, and the node with the node number (3) is searched, for example. Since the node with the node number (3) is assigned the block number 3, if the search is further continued, the circuit block with the block number 3 is set to the active state. As described above, the information on the node to be searched next is stored, and the circuit blocks are sequentially activated, thereby realizing low power consumption.

FIG. 2 is a circuit diagram showing an embodiment of the encoding apparatus according to the present invention. FIG. 3 is a diagram showing a plurality of circuit blocks 100 shown in FIG. 0, ..., 100 m-1, 100 m
One of the circuit blocks 100 FIG. 3 is a diagram showing a circuit portion corresponding to k in more detail. Each circuit block 100 shown in FIGS. 0, ..., 100 k,
…, 100 m-1, 100 For m, a partial circuit 100 surrounded by a dashed line in FIG. 6 is applied. In this case, however, it is necessary to make a modification such as adding an area for storing a block number to the memory section 25 shown in FIG. 6, but this modification is obvious. And description thereof will be omitted.

Each circuit block 100 0, ..., 100
k, ..., 100 m-1, 100 m (hereafter circuit block
100 k), text input terminal, no
In the front part of the input terminal (see Fig. 3),
Remote inverter 102 k and tri-state inbar
P-channel transformer connecting the output side of the
Transistor 104 k is provided. Tri-state
Inverter 102 k input side is the data input bus 110
Is connected to

Each circuit block 100 From k
In addition to code number data and chain code data,
The block number data is output.
Each of the N-channel transistors 112 k is placed
Node number data and chain
Data and block number data are N-channel
Star 112 k and data output bus 120
Amplifier 130 0, ..., 130 k, ..., 130
n and output. Also tri-state in
Barta 102 k, P channel transistor 104
k, N channel transistor 112 k is a block
Selection circuit 140 k. That is, the block
Selection circuit 140 k output is a logical ‘1’ (H level)
In the case, the tri-state inverter 102 k and N
Channel transistor 112 When k becomes conductive,
P-channel transistor 104 k is in the cut-off state
This causes the block selection circuit 140 to k
Corresponding circuit block 100 k becomes active
Text data register 150, node number register
Text data stored in the data 152 (see FIG. 2).
Code number data is transmitted via the data input bus 110.
To tri-state inverter 102 circuit via k
Block 100 k. Also, the circuit block
100 node number data output from k, chain
Code data and block number data are
Transistor 112 Data output bus 1 via k
20 to the sense amplifier 130 0, ...,
130 k, ..., 130 n.

The block number data is 2 in this embodiment.
The two sense amplifiers shown in bits and shown in FIG.
130 0,130 1 and the block number
The output is stored in the
Each circuit block 100 via the selection bus 160 0,
…, 100 k, ..., 100 m-1, 100 to m
Each block selection circuit 140 provided accordingly 0, ...,
140 k, ..., 140 m-1, 140 m
You.

On the other hand, the block selection circuit 140 If the output of k is logic “O” (L level), the tri-state inverter 102 k is in a non-conducting state (a state where the output side is in a high impedance state). When k is turned on, the text input terminal and the node number input terminal are fixed to the state of logic '1' (H level). In addition, the N-channel transistor 112 k is turned off. Thereby, the block selection circuit 140 circuit block 100 corresponding to k
k is in an inactive state with no data input or output.

FIG. 4 is a block diagram showing each block selection circuit 140. k
It is a circuit diagram. This block selection circuit 140 k is two
Signal of logic "1" (H level) when the input of
Exclusive NOR gate 142 that outputs
k 1,142 k 2 and AND gate 144
Have been. Each exclusive NOR gate 142 k
1,142 k 2. One input terminal of each
Connected to the power supply or power supply.
It is fixed to a state of '0' or logic '1'. This
Are fixed in the block selection circuit 140. k
Circuit block 100 corresponding to k block number
You. Block input via the block selection bus 160
Exclusive NOR gate 1 with two lock number data
42 k 1,142 k From each other input terminal of 2
Block number input from one of the input terminals
And the output of AND gate 144 is logic
"1" AND gate 14 if even one bit does not match
4 becomes logic '0'. This And Gate 144
Is output from the block selection circuit 140 corresponding to k
Tri-state inverter 102 k control terminal, P
Channel transistor 104 k gate and N channel
Channel transistor 112 k is transmitted to the gate
Road block 100-0, ..., 100 k, ..., 100-
m-1 and 100-m are controlled as described above.
Be done. Here, the block selection circuit shown in FIG.
140 Two exclusive noagas that make up k
142 k 1,142 k 2 each one input terminal
Is connected to ground or power,
Assume that logic ‘0’ and logic ‘1’ are fixed.
Instead of fixing in this way, each
Equipped with a register in front of one input terminal for searching data
Write the block number to that register first
You may comprise.

Referring to FIG. 2, the data detection of this encoding apparatus is described.
The circuit operation at the time of searching will be described. Here we mentioned earlier
Data search of text chain T0 → T1 as in the example
The case where the code number C4 is obtained by executing
You. First, the first node (node number (0) shown in FIG. 1)
Node number “0000” assigned to the
And stored in the node number register 152.
At the same time, for example, text T0 (text data $ 0
0 '; see Table 1) is input from outside
Stored in register 150. Furthermore, from outside
The number of times the data of the indicated node numbers (1) and (2) are stored
Block number of road block 0 (block number data $ 0
0 ') is input and stored in the block number register 154.
Is done. The data stored in the block number register 154
The block number data “00” is stored in the block selection bus 16.
0, each block selection circuit 140 0, ..., 14
0 k, ..., 140 m-1, 140 m
Here, for example, the circuit block 100 Only 0 is active
And the other circuit blocks are inactive.
Therefore, the text data register 150 and the node
Text data $ 0 stored in number register 152
0 '(text T0) and node number data' 0000 '
(Node number (0)) passes through the data input bus 110
Circuit block 100 0, which causes
As described above, the data output bus 120 and the sense amplifier
130 0,130 1, ..., 130 k, ..., 130
n and the node number (1) and the code number C1
Is output, and here the block number 1 is also output.
You. Output node number (1) (node number data
'01') and block number 1 (block number data
"01") are the node number register 152 and the block
Is stored in the block number register 154. Code number C1
Is output to the outside. Here, this code number C1
Is not adopted as described above. Also outside
Text T1 (text data '01') is input
And stored in the text data register 150.

Next, the block number data “01” stored in the block number register 154 is transferred to each block selection circuit 140 via the block selection bus 160. 0, ...,
140 k, ..., 140 m-1, 140 m, and this time, a circuit block with a block number 1 (not shown here but a circuit block 100-1)
) Is active, and all other circuit blocks are inactive. Thereafter, the text data '01' stored in the text data register 150 and the node number data '0001' stored in the node number register 152 are transferred to the circuit block 100 via the data input bus 110. 1 and the code number C4 is output to the node number (4) node.

As described above, the number of the circuit block to be activated next is stored in the memory area, and the block number stored at the time of data retrieval of each text constituting the text chain is output. By providing a configuration in which a circuit block for which data is searched next is made active, it is not necessary to operate the entire circuit at the same time, and an encoding device with low power consumption is realized.

In the above embodiment, the block number is represented by 2 bits, but this is merely an example, and it goes without saying that the block number is not limited to that represented by 2 bits.

[0041]

As described above, the encoding apparatus of the present invention has a plurality of circuit blocks, and the memory block of the circuit section to be activated next has a plurality of circuit blocks. The block number is stored, the block number stored in the memory area is output, and the output block number is used as a state switching unit for switching each circuit block between an active state and an inactive state. Since input is performed, only necessary circuit blocks can be set in an active state, and a low power consumption type encoding device is realized.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating an example of text arranged in a tree structure.

FIG. 2 is a circuit diagram showing an embodiment of the encoding apparatus according to the present invention.

FIG. 3 shows one of a plurality of circuit blocks shown in FIG. 2;
FIG. 3 is a diagram showing a circuit portion corresponding to one circuit block in more detail.

FIG. 4 is a circuit diagram of each block selection circuit.

FIG. 5 is a diagram illustrating an example of text arranged in a tree structure.

FIG. 6 is a diagram illustrating an example of an encoding device according to a conventional proposal.

FIG. 7 is a circuit diagram showing a part of the encoding device shown in FIG. 6 taken out therefrom;

FIG. 8 is a circuit diagram further embodying the circuit shown in FIG. 7;

[Explanation of symbols]

100 0, ..., 100 k, ..., 100 m-1, 1
00 m circuit block 102 k tri-state inverter 104 k P-channel transistor 110 Data input bus 112 k N-channel transistor 120 data output bus 130 0, ..., 130 k, ..., 130 n sense amplifier 140 0, ..., 140 k, ..., 140 m block selection circuit 150 text data register 152 node number register 154 block number register 160 block selection bus

Claims (1)

(57) [Claims] 1. A method in which each text is arranged at each node of a tree structure to allow re-appearance, a code number is assigned to each node as needed, and a node existing before a branch of the tree structure is traced. In the encoding device for converting a text chain in which the texts are arranged in the order along the route followed by calculating the code number attached to the input data, the input data corresponds to the input data that is input. A decoder unit that specifies the node to be processed, a memory unit that includes a large number of memory areas corresponding to the respective nodes, and outputs a storage content of a memory area corresponding to the node specified by the decoder unit. An active state that permits input of input data and an output of stored contents from the memory unit, and an inactive state that shuts off these inputs and outputs. A plurality of circuit blocks each having a block number and having a state switching unit for switching, a decoder unit constituting each circuit block, a text input unit for inputting the text as a part of the input data, and each of the nodes A node number input unit for inputting a node number appended to the input data as a part of the input data, and a node specifying unit for specifying a node corresponding to the input data based on the input data including the text and the node number. A node number that outputs a node number assigned to the node from a memory area corresponding to the node specified by the node specifying unit and inputs the node number to the node number input unit. Outputting a code number assigned to the node from an output unit and a memory area corresponding to the node specified by the node specifying unit; A code number output unit for outputting a block number of a next active circuit block assigned to the node from a memory area corresponding to the node designated by the node designation unit and inputting the block number to the state switching unit A coding number output unit.