JPH06139782A - Decoding circuit of semiconductor memory - Google Patents

Abstract

PURPOSE:To enable the decoding circuit to continue a retrieval from a condition at the time of mishit without doing the retrieval over from the beginning by providing a constitution in which the content of a latch circuit are preserved as they are when mishit signal is outputted from a mishit detecting circuit. CONSTITUTION:A hit signal '1' is outputted from an output terminal H/MH of a hit detecting circuit, output signals from a node number output 26 are inputted to a flip-flop circuit 225 through an AND circuit 222 and an OR circuit 224 and are set. Moreover, when a mishit signal '0' is outputted, the circuit 222 is cut off, data are inputted to a circuit 225 through an AND circuit 223, an output terminal Q of the circuit 225 is connected to the input terminal of the circuit 223 and therefore, the data set in the circuit 225 are reset when none of coincident detecting circuits are active. Thus, the node number set in the circuit 225 is held as it is, the retrieval does not go back to a beginning and the operations are continued when erroneous data are inputted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a decoding circuit for designating a memory area in a semiconductor memory in which the contents to be read out of the semiconductor memory are stored based on an input bit pattern.

[0002]

2. Description of the Related Art Conventionally, various semiconductor memories have been widely used. As one application example of the semiconductor memory, the applicant of the present application has proposed a first input section for inputting a bit pattern from the outside and the semiconductor memory. A second input unit is provided which has a latch circuit for latching a bit pattern forming a part of the read content and which inputs the latched bit pattern to the latch circuit. By decoding the bit pattern input from both the input unit 2 and the input unit 2, the memory area in which the content to be read next is stored from the predetermined memory area in which the predetermined content is stored. An encoding device provided with a matching detection circuit for selection has been proposed (Japanese Patent Application No. 4-87219).

The coding apparatus according to this proposal allows a plurality of texts to be re-appeared and is arranged in a tree structure in an ideal manner.
This is a device to which a semiconductor memory is applied, which obtains a code number that is predetermined according to the sequence order of the text. The technique on which the present invention is based will be described below with reference to this encoding device.

[0004]

[Table 1]

[0005]

[Table 2]

Table 1 shows each text T0, T1, T2, T
3 is a correspondence table of 3 bits and a text code consisting of 2 bits which is equated with each of these texts T0, T1, T2 and T3. Table 2 shows a text chain in which the texts are arranged and the text chain. It is a correspondence table with the generated code numbers. The 10-bit chain code is a code number represented by a binary code.

Here, first, the data structure handled by the encoding apparatus according to the above proposal will be described. Figure 4
It is a figure showing an example of the text arranged in the tree structure. In this figure, the numbers in parentheses represent the node numbers given to each node. First, two branches extend from the node (vertex) with the node number (0) at the top of the figure,
Texts T0 and T1 are arranged at the nodes at the ends of the branches. Of these, the code number C1 is attached to the node of the node number (1) in which the text T0 is arranged,
On the other hand, no code number is given to the node having the node number (2) in which the text T1 is arranged. Three branches further extend from the node of the node number (1) where the text T0 is arranged among these nodes, and the texts T0, T1, and T3 are arranged at the nodes at the ends of these three branches, respectively. Has been done. Moreover, code numbers C3, C4, and C5 are assigned to the respective nodes. Two branches further extend from the node of the node number (3) in which the text T0 is arranged among these nodes, and
Texts T1 and T2 are arranged at the nodes with node numbers (8) and (9) at the end of the book branch, respectively, and code numbers C8 and C9 are given to these nodes, respectively. Two branches extend from the node of the node number (2) where the text T1 is arranged, and the texts T0 and T2 are arranged at the nodes at the ends of these two branches, respectively. Among these, the code number C is assigned to the node of the node number (7) where the text T2 is arranged.
7 is attached. Furthermore, these texts T0, T2
One and two branches respectively extend from the node in which the text T0 is arranged, and the text T0 is included in the node at the node number (10) at the end of the branch extending from the node in which the text T0 is arranged in the node number (6). Is placed, and the code number is C10.
Is added to each of the nodes of the node numbers (11) and (12) at the tips of the two branches extending from the node of the arranged node number (7) in which the text T2 is placed. T3 is arranged, and code numbers C11 and C12 are given to these respective nodes.

Here, the encoding method using the tree-structured data will be specifically described as follows. First, consider the case where the text chain T0 → T1 is input. At this time, the desired output chain code is '0000000100' as defined in Table 2.
Is.

To obtain this result, first the text T0
The text code '00' corresponding to is input. The text T0 on the tree structure is arranged at the node at the branch destination of the node number (0) (node number (0) is the first node number of encoding). Text T connected to the end of the branch extending from the node with node number (0)
Although there is only one 0, there are some other nodes in which the text T0 is arranged, which are connected to nodes other than the node with the node number (0).

Therefore, here, in order to recognize that the text input to this tree structure data is the first text T0 of the tree structure, this text data '00' is used.
In addition to that, node number (0) (data '000
0 ') is searched. The text T at the end of this branch
Although the code number C1 (chain code '0000000001') is given to the node in which 0 is arranged,
This time it is not the code number that should be requested.

Next, when the text data "01" corresponding to the text T1 is input, the node number (1) (data "0001") of the text T0 immediately before the text data "01" and the text data "01" input this time are input. The tree structure database is searched by both. As a result, it is possible to clearly distinguish the text T1 at the other branch end and the text T1 at the branch end of the node with the node number (1).

Thus, the branch of the text chain T0 → T1 is determined, and the code number C4 (chain code '00000000100') attached to the tip of this T1 branch is output as the code number to be obtained. Similarly, any chain code C1, ... Defined in Table 1
..., C12 can be obtained. The encoding device according to the above proposal is an effective device for handling the data of the tree structure as shown in FIG. 4, and assigns a node number to each node of the tree structure to input the input text and the current position. It is configured to obtain the node to be moved to the next based on the node number of the node that performs the process. For this reason, even if a large number of branches extend from the node currently located, unlike a case where these branches are searched sequentially, a node that should immediately advance to the next is found in one search operation, and therefore the text chain is extremely It has the feature of being converted into a code number in a short time.

FIG. 5 is a diagram showing an example of the encoding device according to the above-mentioned proposal. Match detection circuit section 20 of this encoding device
Include text data input terminals TD0, TD1 (first input section) and node number input terminals ND0, ND1, ND.
2 and ND3 are provided. The data input from the node number input terminals ND0, ND1, ND2, ND3 are input to the node number setting circuit 22 (latch circuit forming the second input section). The node number data output 26 from the encoding circuit section 25 is also connected to the node number setting circuit 22, and the input is switched by the input switching terminal SW.

The numbers written at the leftmost end of the coincidence detection circuit section 20 represent the node numbers (1), (2), (3), ..., (12) of each node of the tree structure shown in FIG. ing. For example, the node number (1) in the bottom line represents the node in which the text T0 is arranged in the upper row of the tree structure data in FIG. In the match detection circuit unit 20, line segments corresponding to each node extending to the match detection circuit 21 in the left-right direction and data lines from the text data input terminals TD0 and TD1 and node numbers set in the vertical direction are set. The data lines from circuit 22 intersect. A black circle is displayed at this intersection when the data on the data line is the normal data "1", and when there is no black circle when the data on the data line is the inverted data "0". The output of the detection circuit 21 is configured to be "1" (active). That is, in the case of the node number (1), when all the outputs from the text data input terminals TD0 and TD1 and the node number setting circuit 22 are "0", the output of the match detection circuit 21 corresponding to the node number (1) is It becomes "1".

Here, in the node number setting circuit 22, the node number shown in FIG.
Node number (0) of the vertex node shown in (data '00
00 ') is set and the data' 00 'of the text T0 is inputted from the text data input terminals TD0 and TD1 in that state, the output of the coincidence detection circuit 21 corresponding to the node number (1) becomes'1'. Become. Then, the bottommost row of the encoding circuit section 25 on the right side of FIG.
The output of the output circuit 28 connected to the intersection where
It becomes 1 '. Specifically, from the node number data output 26 to '0001', from the code valid bit output 29 to '
1 ', and chain code data output 30 to '00
00000001 'is output. Here, the code valid bit output 29 indicates whether the data output from the chain code output 30 is valid or invalid, that is, the node with the node number output from the node number data output 26 has a code number It indicates whether or not it is attached. Here this code valid bit output 2
9 is '1', so chain code data output 30
Although the data output from the device is valid, the data output from the chain code output 30 is not used as the code number to be obtained here. The data “0001” output from the node number data output 26 is input to the node number setting circuit 22.

Next, the text data input terminals TD0, T
When the data '01' of the text T1 is input to D1,
Since the output of the node number setting circuit 22 is the value "0001" from the previous search result of the text T0, the input of the match detection circuit unit 20 is "010001" this time. The match in this pattern is the node number (4) in which the text T1 is arranged (see FIG. 4). As a result, the output of the match detection circuit 21 corresponding to the node number (4) becomes "1", and the fourth row from the bottom of the encoding circuit section 25 becomes active. Therefore, the code valid bit output is "1" and the chain code data output is "000".
0000100 ', and finally this chain code is obtained as a code number. At this time, node number data "0100" is obtained at the same time, but this is not used here.

As described above, by referring to both the input data and the node number, even when a large number of branches are branched from each node, high-speed search and match comparison are performed, and encoding is performed. The speedup of is realized. FIG. 6 is a circuit diagram showing a part of the encoding device shown in FIG.
FIG. 7 is a circuit diagram in which the circuit shown in FIG. 6 is further embodied.
FIGS. 6 and 7 correspond to the input data of “110111” (text data “11” and the output from the node number setting circuit 22 is “0111”).
3 is a circuit diagram corresponding to the node number (12) in FIG.

As shown in FIG. 7, the coincidence detection circuit section 20.
Are six transistors T connected in series with each other.
The data lines DL1, DL2, DL3, DL4, D are connected to the gates of r1, Tr2, Tr3, Tr4, Tr5, Tr6, respectively.
L5, DL6 or each data bar line DBL1, DBL
Any one of 2, DBL3, DBL4, DBL5 and DBL6 is connected. Further, precharging transistors Tr10 and Tr11 are provided at two locations, and the transistor Tr10 is a P-channel transistor for precharging the potential at the point A. The transistor Tr11 is an N-channel transistor provided between the transistor Tr1 and the ground line, and suppresses discharge of the potential at the point A during precharge. The coincidence detection circuit 21 includes an inverter 20 'and a feedback type P.
A channel transistor Tr12 is provided.

In the encoding circuit section 25, the output of the inverter 20 'is the memory transistors MTr1 and MTr.
2, the gates of MTr3 and MTr4 are connected.
These memory transistors MTr1, MTr2, MTr
One of the data output lines DOL3, DO
The other of L4, DOL5, and DOL6 is connected to the ground line.

Further, the respective data output lines DOL1, ...
, DOL15 has precharge channel transistors Tr1, ..., PTr15 at one end, and an inverter 21 'and a feedback P-channel transistor Tr13 at the other end. First, the precharge control terminal 31 for initialization is set to '
When 0'is applied, the potential at the point A is set to '1'.
Along with this, the output of the coincidence detection circuit 21, which is the inverter output of the point A potential, becomes "0". When the output of the coincidence detection circuit 21 becomes "0", the memory transistors MTr1, MTr2, MTr3, MTr4 are turned off, and when "0" is applied to the precharge control terminal 31, the precharge P The channel transistors PTr1, ..., PTr15 are turned on, the respective data output lines DOL1, ..., DOL15 maintain the state of "1", and the output of the inverter 21 ', which is an inverted output thereof, is "1".
Keep 0'state. At this time, the code valid bit output also outputs "0". By this signal output, it can be known that the output of the chain code data is invalid data.

Then, the text data input terminals TD0,
When desired input data is applied from TD1 and the output from the node number setting circuit 22 is determined, and then "1" is applied to the precharge control terminal 31, the search state is entered. By repeating the initialization state and the search state in synchronization with the application of each input data, a desired chain code data, that is, a code number can be obtained.

The above is an example of the encoding apparatus according to the above proposal.

[0023]

In the above coding device, a problem arises, for example, when the output of any match detection circuit 21 shown in FIG. 5 is not active. For example, consider the time when the search starts from the node number (0) shown in FIG. 4 and progresses to the node number (1). At this time, the node number setting circuit shown in FIG.
001 ') is set. In that state, the text data input terminals TD0 and TD1 have text T
It is expected that any one of the data "00" of 0, the data "01" of the text T1 or the data "11" of the text T3 will be input (see FIG. 4). Here, for example, by pressing the key of the keyboard of the device incorporating this encoding device by mistake, the data '1' of the text T2 is input to the text data input terminals TD0, TD1.
It is assumed that 0'is input. At this time, the entire bit pattern becomes “100001” in order from the left side of FIG. 5, does not match any node, and therefore, the output of any match detection circuit 21 is not activated. in this case,
The node number data output 26 outputs incorrect data of "0000", and this data is output to the node number setting circuit 2
Although it is input to 2, and the search is advanced to the intermediate node, the search returns to the first node of the node number (0), and there is a problem that the search needs to be restarted from the beginning.

In view of the above problems, the present invention has made it possible to proceed without re-starting from the beginning, even if the active signal is not output from the decoder circuit (match detection circuit section 20) as described above. It is an object of the present invention to configure a decoding circuit of a semiconductor memory configured to be able to continue the search from.

[0025]

The decoding circuit of a semiconductor memory according to the present invention for achieving the above object is input from a large number of memory areas constituting a semiconductor memory based on an input bit pattern. In a semiconductor memory decoding circuit that selects a memory area corresponding to a bit pattern, a first input unit that inputs a bit pattern from the outside and a bit pattern that constitutes a part of the content read from the semiconductor memory are latched. By decoding a bit pattern that is input from both the first input section and the second input section that has a latch circuit and that inputs the bit pattern latched in the latch circuit , A memory area in which the content to be read next is stored is selected from among a predetermined number of memory areas in which a predetermined number of content is stored. A coincidence detecting circuit for, and the hit detecting circuit for detecting whether or not any of the above predetermined number of the memory area is selected by the coincidence detection circuit unit,
A bit detection circuit section for detecting whether or not any one of the predetermined plurality of memory areas is selected by the coincidence detection circuit section, wherein the latch circuit is provided by the coincidence detection circuit section. The contents of the latch circuit are stored when none of the memory areas is selected.

[0026]

The decoding circuit of the semiconductor memory according to the present invention is provided with the above-mentioned bit detection circuit section, and the content thereof is provided in the second input section when none of a predetermined number of memory areas is selected. Since it has a configuration to store in the latch circuit, even if incorrect data is input,
When the correct data is input next, the search will be continued.

[0027]

EXAMPLES Examples of the present invention will be described below. FIG. 1 is a diagram corresponding to FIG. 7 referred to when describing the encoding device according to the above-described proposal, which is configured to include the decoding circuit according to the embodiment of the present invention. Elements corresponding to the circuit elements shown in FIG. 7 are assigned the same numbers and symbols as those given in FIG. 7, and only the differences will be described.

The difference between the circuit shown in FIG. 1 and the circuit shown in FIG. 7 is that a hit detection circuit 100 is provided. The hit detection circuit 100 is provided with a hit detection line HL extending in the vertical direction of the figure. At the intersection of the hit detection line HL and the coincidence detection circuit 21, a hit detection transistor HTr is provided as shown in the figure. It is equipped.
Although only one hit detection transistor HTr is shown in FIG. 1, the hit detection line HL extends in the vertical direction of FIG. 5 along the output ends of the many match detection circuits 21 shown in FIG. A hit detection transistor HTr as shown in FIG. 1 is arranged at each intersection of each of the plurality of coincidence detection circuits 21 and the hit detection line HL. The hit detection circuit 100 also includes a precharge transistor Tr1 for precharging the hit detection line HL.
01, an inverter 103 for sensing the potential of the hit detection line HL, and a latch transistor Tr102 for latching the output of the inverter 103.

Here, this semiconductor memory (encoding device)
When a signal of "0" (L level) is input from the precharge control terminal 31 prior to the sensing of the content stored in the hit detection line through the precharge transistor Tr101 together with the precharge of other parts. HL is also precharged. After that, the match detection circuit unit 20 detects a match, and the node number set in the node number setting circuit 22 and the text data input terminals TD0 and TD1.
The output of the coincidence detection circuit 21 that matches the hit pattern determined by the text data input from is active "1". Even if any one of the many match detection circuits 21 becomes active '1', the charge precharged on the hit detection line HL corresponds to the activated match detection circuit 21. It is discharged via the hit detection transistor HTr, and a hit signal'indicating that any one of the match detection circuits 21 is activated is output from the output terminal H / MH (output terminal of the inverter 103) of the hit detection circuit 100. 1'is output. On the other hand, there is no match detection circuit 21 that matches the bit pattern determined by the node number and the text data, and there are many match detection circuits 21.
If none of the match detection circuits among these hit detection circuits are active, all the hit detection transistors HTr remain in the cutoff state, the hit detection lines HL remain precharged, and any match detection circuit from the inverter 103 is detected. A mishit signal "0" indicating that the circuit 21 has not been activated is output.

By the way, when configuring a semiconductor memory,
The match detection circuit unit 20 (decoding unit) and the encoding circuit unit 25 (memory unit) shown in FIG. 5 may be divided into a plurality of blocks. FIG. 2 is a partial circuit diagram of hit detection means for a semiconductor memory divided into a plurality of blocks.

When the block is divided into a plurality of blocks, each block is provided with the hit detection circuit 100 described with reference to FIG. 1, and the output terminals of the hit detection circuit 100 for each block are H / MH_1 and H / H. MH_2, ..., H / MH_
When n, those output terminals H / MH_1, H / M
The signals output from H_2, ..., H / MH_n are input to the OR circuit 110, and the output terminals of the OR circuit 110 are
By the output terminal H / MH_ of the hit detection circuit as a whole, either the match detection circuit 21 of any block becomes active (hit '1') or any match detection of any block. It is detected whether the circuit 21 has not become active (miss hit "0").

FIG. 3 is a circuit diagram of 1-bit of the node number setting circuit 22 shown as a block in FIG. The input switching terminal SW sets the node number input from the node number setting terminal NDi (i = 0, 1, 2, 3; see FIG. 1) to the node number setting circuit 22 or outputs from the node number data output 26. This is a terminal to which a switch signal for switching whether to set the output node number is input. When the switch signal is "1", the node signal input from the node number setting terminal NDi is the AND circuit 221 and the OR circuit 224.
When a pulse signal for data setting is input from the data input terminal D to the flip-flop circuit 225 via the data input terminal and from the data set terminal DS to the clock input terminal CL of the flip-flop circuit 225, the node is set at that timing. The signal is a flip-flop circuit 225
Is set to. When the switch signal is “0”, the AND circuit 221 is cut off, and the data passes through the AND circuit 222 or 223. Normally, since the hit signal “1” is output from the output terminal H / MH_ of the hit detection circuit 100 (see FIG. 1), the signal output from the node number data output 26 is output to the AND circuit 222 and the OR circuit 224. The data set pulse signal is input to the flip-flop circuit 225, and is set in the flip-flop circuit 225 at the timing when the data set pulse signal is input.

When the hit detection circuit 100 outputs a mishit signal "0", the AND circuit 222 is also cut off,
Data is input to the flip-flop circuit 225 via the AND circuit 223. One of the input terminals of the AND circuit 223 has the flip-flop circuit 2
If the output terminals Q of 25 are connected and therefore none of the coincidence detection circuits 21 (see FIG. 5) is activated, the flip-flop circuit 225 is input at the timing when the data set pulse signal is input. The set data is set again, so that the node number set in the flip-flop circuit 225 is stored as it is.

In the present embodiment, as described above, the hit detection circuit 100 is provided, and when the hit detection circuit 100 outputs the mishit signal, the contents of the node number setting circuit 22 are saved. Even if the input data is input, the search can be continued without returning to the drawing.

[0035]

As described above, the decode circuit of the semiconductor memory of the present invention includes the first input section and the second input section having the latch circuit, and the mishit signal is received from the hit detection circuit section. Since the contents of the latch circuit are stored as they are when they are output, even if a mishit occurs, the search can be continued from the state that has been advanced to that point without restarting from the beginning.

[Brief description of drawings]

FIG. 1 is a diagram corresponding to FIG. 7, configured to include a decoding circuit according to an embodiment of the present invention.

FIG. 2 is a partial circuit diagram of hit detection means for a semiconductor memory divided into a plurality of blocks.

3 is a block diagram of the node number setting circuit shown in FIG.
It is a circuit diagram for 1 bit.

FIG. 4 is a diagram showing an example of text arranged in a tree structure.

5 is a diagram showing an example of an encoding device in which the database shown in FIG. 4 is implemented as hardware.

FIG. 6 is a circuit diagram showing a part of the encoding device shown in FIG.

FIG. 7 is a circuit diagram in which the circuit shown in FIG. 6 is further embodied.

[Explanation of symbols]

 20 coincidence detection circuit section 21 coincidence detection circuit 22 node number setting circuit 100 hit detection circuit 221, 222, 223 AND circuit 224 OR circuit 225 flip-flop circuit

Claims (1)

[Claims] 1. Based on the input bit pattern,
In a semiconductor memory decoding circuit for selecting a memory area corresponding to a bit pattern input from a large number of memory areas forming a semiconductor memory, a first input unit for inputting a bit pattern from the outside, and the semiconductor memory A second circuit having a latch circuit for latching a bit pattern forming part of the read content, and inputting the latched bit pattern to the latch circuit
Of a predetermined number of memory areas in which a predetermined number of contents are stored by decoding the bit patterns input from both the input unit and the first input unit and the second input unit. A match detection circuit section that selects a memory area in which the content to be read next is stored; and a hit that detects whether any one of the predetermined number of memory areas is selected by the match detection circuit section. A semiconductor circuit, wherein the latch circuit stores the content of the latch circuit when none of the predetermined plurality of memory areas is selected by the coincidence detection circuit section. Memory decode circuit.