JPH06139781A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To make the semiconductor memory suitable for the retrieval of conventional tree structure data and to enable the retrieval of simple conversion table data by providing two mask circuits. CONSTITUTION:When tree stricture data are stored in a semiconductor memory 100 and are retrieved, second output data Dk are outputted to an external from an output selector and a conventional function is obtained. Moreover, when simple conversion table data are stored and are retrieved, make a first coincident data storage region 150-R-1 and a first output data storage region 110-R-1 into a first pair, store the retrieval side data in the region 150, store the retrieved side data in the region 110, input the retrieved data through a data register 160 and the corresponding output data are obtained. Similarly, a second coincident data and an output data storage region are retrieved as a second pair. Therefore, no useless region is generated in the storage sections 150 and 110 and their effective utilization is realized when simple conversion table data are stored and retrieved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory in which a large number of output data are stored, an address is designated based on an input bit pattern, and the output data stored in the address is read out.

[0002]

2. Description of the Related Art Conventionally, various semiconductor memories have been widely used. For example, when converting a JIS code into a new JIS code, search data and search target data have a one-to-one correspondence and search data One application example of a semiconductor memory has been considered in which by inputting, the searched data corresponding to the input search data is read.

As another application example of the semiconductor memory,
For example, the kana character array "Ha → Tsu → Me → I" is converted to the Chinese character "invention", and the Kana character array "Ha → Tsu → Mi → Mi" that is halfway identical to the Kana character array is converted to Kanji. "First ears"
Multiple search data (texts) are arranged in a tree structure, allowing re-appearance, etc., and searched data (code number) that is predetermined according to the sequence order of the texts. There has been proposed a semiconductor memory that seeks (Japanese Patent Application No. 4-87219).

The technique underlying the present invention will be described below along with the semiconductor memory according to this proposal.

[0005]

[Table 1]

[0006]

[Table 2]

Table 1 shows each text T0, T1, T2, T
3 is a correspondence table of 3 bits and a text code consisting of 2 bits which is equated with each of these texts T0, T1, T2 and T3. Table 2 shows a text chain in which the texts are arranged and the text chain. It is a correspondence table with the generated code numbers. The 10-bit chain code is a code number represented by a binary code.

First, the data structure handled by the encoding device according to the above proposal will be described. Figure 6
It is a figure showing an example of the text arranged in the tree structure. In this figure, the numbers in parentheses represent the node numbers given to each node. First, two branches extend from the node (vertex) with the node number (0) at the top of the figure,
Texts T0 and T1 are arranged at the nodes at the ends of the branches. Of these, the code number C1 is attached to the node of the node number (1) in which the text T0 is arranged,
On the other hand, no code number is given to the node having the node number (2) in which the text T1 is arranged. Three branches further extend from the node of the node number (1) where the text T0 is arranged among these nodes, and the texts T0, T1, and T3 are arranged at the nodes at the ends of these three branches, respectively. Has been done. Moreover, code numbers C3, C4, and C5 are assigned to the respective nodes. Two branches further extend from the node of the node number (3) in which the text T0 is arranged among these nodes, and
Texts T1 and T2 are arranged at the nodes with node numbers (8) and (9) at the end of the book branch, respectively, and code numbers C8 and C9 are given to these nodes, respectively. Two branches extend from the node of the node number (2) where the text T1 is arranged, and the texts T0 and T2 are arranged at the nodes at the ends of these two branches, respectively. Among these, the code number C is assigned to the node of the node number (7) where the text T2 is arranged.
7 is attached. Furthermore, these texts T0, T2
One and two branches respectively extend from the node in which the text T0 is arranged, and the text T0 is included in the node at the node number (10) at the end of the branch extending from the node in which the text T0 is arranged in the node number (6). Is placed, and the code number is C10.
Is added to each of the nodes of the node numbers (11) and (12) at the tips of the two branches extending from the node of the arranged node number (7) in which the text T2 is placed. T3 is arranged, and code numbers C11 and C12 are given to these respective nodes.

Here, the method of encoding using the tree structured data will be specifically described as follows. First, consider the case where the text chain T0 → T1 is input. At this time, the desired output chain code is '0000000100' as defined in Table 2.
Is.

To obtain this result, first the text T0
The text code '00' corresponding to is input. The text T0 on the tree structure is arranged at the node at the branch destination of the node number (0) (node number (0) is the first node number of encoding). Text T connected to the end of the branch extending from the node with node number (0)
Although there is only one 0, there are some other nodes in which the text T0 is arranged, which are connected to nodes other than the node with the node number (0).

Therefore, here, in order to recognize that the text input to this tree structure data is the first text T0 of the tree structure, this text data '00' is used.
In addition to that, node number (0) (data '000
0 ') is searched. The text T at the end of this branch
Although the code number C1 (chain code '0000000001') is given to the node in which 0 is arranged,
This time it is not the code number that should be requested.

Next, when the text data "01" corresponding to the text T1 is input, the node number (1) (data "0001") of the text T0 immediately before that and the text data "01" input this time are input. The tree structure database is searched by both. As a result, it is possible to clearly distinguish the text T1 at the other branch end and the text T1 at the branch end of the node with the node number (1).

With this, the branch of the text chain T0 → T1 is determined, and the code number C4 (chain code '00000000100') attached to the tip of the branch of this T1 is output as the code number to be obtained. Similarly, any chain code C1, ... Defined in Table 1
..., C12 can be obtained. The semiconductor memory according to the above proposal is an effective device for handling tree-structured data as shown in FIG. 6, and each node of the tree-structure is given a node number so that it can be located with the input text. It is configured to obtain a node to be advanced to the next based on the node number of the node. For this reason, even if a large number of branches extend from the node currently located, unlike a case where these branches are searched sequentially, a node that should immediately advance to the next is found in one search operation, and therefore the text chain is extremely It has the feature of being converted into a code number in a short time.

FIG. 7 is a diagram showing an example of the semiconductor memory according to the above proposal. The coincidence detection circuit section 20 of the semiconductor memory includes text data input terminals TD0 and TD1 (first input section) and node number input terminals ND0 and ND1,
ND2 and ND3 are provided. The data input from the node number input terminals ND0, ND1, ND2, ND3 are input to the node number setting circuit 22 (register which constitutes the second input section). The node number data output 26 from the encoding circuit section 25 is also connected to the node number setting circuit 22, and the input is switched by the input switching terminal SW.

The numbers written at the leftmost end of the coincidence detection circuit section 20 represent the node numbers (1), (2), (3), ..., (12) of each node of the tree structure shown in FIG. ing. For example, the node number (1) in the bottom line represents the node in which the text T0 is arranged in the upper row of the tree structure data in FIG. In the match detection circuit unit 20, line segments corresponding to each node extending to the match detection circuit 21 in the left-right direction and data lines from the text data input terminals TD0 and TD1 and node numbers set in the vertical direction are set. The data lines from circuit 22 intersect. A black circle is displayed at this intersection when the data on the data line is the normal data "1", and when there is no black circle when the data on the data line is the inverted data "0". The output of the detection circuit 21 is configured to be "1" (active). That is, in the case of the node number (1), when all the outputs from the text data input terminals TD0 and TD1 and the node number setting circuit 22 are "0", the output of the match detection circuit 21 corresponding to the node number (1) is It becomes "1".

Here, the node number setting circuit 22 is provided with a circuit shown in FIG.
Node number (0) of the vertex node shown in (data '00
00 ') is set and the data' 00 'of the text T0 is inputted from the text data input terminals TD0 and TD1 in that state, the output of the coincidence detection circuit 21 corresponding to the node number (1) becomes'1'. Become. Then, the bottommost row of the encoding circuit section 25 on the right side of FIG.
The output of the output circuit 28 connected to the intersection where
It becomes 1 '. Specifically, from the node number data output 26 to '0001', from the code valid bit output 29 to '
1 ', and chain code data output 30 to '00
00000001 'is output. Here, the code valid bit output 29 indicates whether the data output from the chain code output 30 is valid or invalid, that is, the node with the node number output from the node number data output 26 has a code number It indicates whether or not it is attached. Here this code valid bit output 2
9 is '1', so chain code data output 30
Although the data output from the device is valid, the data output from the chain code output 30 is not used as the code number to be obtained here. The data “0001” output from the node number data output 26 is input to the node number setting circuit 22.

Next, the text data input terminals TD0, T
When the data '01' of the text T1 is input to D1,
Since the output of the node number setting circuit 22 is the value "0001" from the previous search result of the text T0, the input of the match detection circuit unit 20 is "010001" this time. The match in this pattern is the node number (4) in which the text T1 is arranged (see FIG. 6). As a result, the output of the match detection circuit 21 corresponding to the node number (4) becomes "1", and the fourth row from the bottom of the encoding circuit section 25 becomes active. Therefore, the code valid bit output is "1" and the chain code data output is "000".
0000100 ', and finally this chain code is obtained as a code number. At this time, node number data "0100" is obtained at the same time, but this is not used here.

As described above, by referring to both the input data and the node number, even when a large number of branches are branched from each node, high-speed search and match comparison are performed, and encoding is performed. The speedup of is realized. FIG. 8 is a circuit diagram showing a part of the semiconductor memory shown in FIG.
FIG. 9 is a circuit diagram in which the circuit shown in FIG. 8 is further embodied.
8 and 9 show that the match detection circuit 21 corresponds to the input data of "110111" (text data "11" and the output from the node number setting circuit 22 is "0111").
3 is a circuit diagram corresponding to the node number (12) in FIG.

As shown in FIG. 9, the coincidence detection circuit section 20.
Are six transistors T connected in series with each other.
The data lines DL1, DL2, DL3, DL4, D are connected to the gates of r1, Tr2, Tr3, Tr4, Tr5, Tr6, respectively.
L5, DL6 or each data bar line DBL1, DBL
Any one of 2, DBL3, DBL4, DBL5 and DBL6 is connected. Further, precharging transistors Tr10 and Tr11 are provided at two locations, and the transistor Tr10 is a P-channel transistor for precharging the potential at the point A. The transistor Tr11 is an N-channel transistor provided between the transistor Tr1 and the ground line, and suppresses discharge of the potential at the point A during precharge. The coincidence detection circuit 21 includes an inverter 20 'and a feedback type P.
A channel transistor Tr12 is provided.

In the encoding circuit section 25, the output of the inverter 20 'is the memory transistors MTr1 and MTr.
2, the gates of MTr3 and MTr4 are connected.
These memory transistors MTr1, MTr2, MTr
One of the data output lines DOL3, DO
The other of L4, DOL5, and DOL6 is connected to the ground line.

Further, the respective data output lines DOL1, ...
, DOL15 has precharge channel transistors Tr1, ..., PTr15 at one end, and an inverter 21 'and a feedback P-channel transistor Tr13 at the other end. First, the precharge control terminal 31 for initialization is set to '
When 0'is applied, the potential at the point A is set to '1'.
Along with this, the output of the coincidence detection circuit 21, which is the inverter output of the point A potential, becomes "0". When the output of the coincidence detection circuit 21 becomes "0", the memory transistors MTr1, MTr2, MTr3, MTr4 are turned off, and when "0" is applied to the precharge control terminal 31, the precharge P The channel transistors PTr1, ..., PTr15 are turned on, the respective data output lines DOL1, ..., DOL15 maintain the state of "1", and the output of the inverter 21 ', which is an inverted output thereof, is "1".
Keep 0'state. At this time, the code valid bit output also outputs "0". By this signal output, it can be known that the output of the chain code data is invalid data.

Then, the text data input terminals TD0,
When desired input data is applied from TD1 and the output from the node number setting circuit 22 is determined, and then "1" is applied to the precharge control terminal 31, the search state is entered. By repeating the initialization state and the search state in synchronization with the application of each input data, a desired chain code data, that is, a code number can be obtained.

The above is an example of the semiconductor memory according to the above proposal.

[0024]

As described above, the data structure used for searching has a one-to-one correspondence between search data and searched data (hereinafter referred to as "simple conversion table data"). There is also an "array" of search data
Also corresponds to one searched data (hereinafter, referred to as “tree structure data”). When dealing with simple conversion table data having a structure in which search data and searched data have a one-to-one correspondence, for example, an ordinary semiconductor memory is used and the searched data is stored in the semiconductor memory and then input to the semiconductor memory. This is realized by using the address data to be searched as the search data. Also, the "array" of search data
The semiconductor memory that handles the tree structure data corresponding to the searched data is realized by using the semiconductor memory according to the above-described proposal.

However, an ordinary semiconductor memory is not suitable for handling tree-structured data. On the other hand, in the above proposal, the semiconductor memory can be used not only for tree-structured data but also for simple conversion table data. The node number setting circuit 22 always holds "0000",
The area corresponding to the node number setting circuit 22 of the match detection circuit section 20 and the area corresponding to the node number data output 26 of the encoding circuit section 25 are not used,
A huge waste will occur.

In view of the above circumstances, it is an object of the present invention to provide a semiconductor memory capable of handling both simple conversion table data and tree structure data without causing a large amount of waste.

[0027]

A semiconductor memory according to the present invention which achieves the above object comprises: (1) Predetermined first and second predetermined output data.
Output data storage unit having a large number of output data storage areas each including first and second output data storage areas (2) First input for inputting first search data from outside (3) A register in which second search data is stored, search data input from the outside, and first output data read from the output data storage unit are selectively used as the second search data. Second input section having input selector for input to register (4) Predetermined first and second matching data are stored respectively, and the first and second matching data and first and second input section are stored. A plurality of match data storage areas corresponding to each of the plurality of output data storage areas, which are first and second match data storage areas for comparing the first and second search data input from Matched data storage unit (5) Stored in the first and second matched data storage areas that are respectively arranged between the matched data storage areas and the output data storage areas that correspond to each other and that form the corresponding matched data storage areas. When each of the first and second matching data and each of the first and second search data match, a matching signal for instructing reading of the output data stored in the corresponding output data storage area (6) A plurality of match detection circuits each of which outputs a plurality of match detection circuits.
(7) A first mask circuit for treating the first match data and the first search data as matching regardless of the first match data attached to the match data storage area of The plurality of second matching data storage areas are stored in the second
A second mask circuit for treating the second match data and the second search data as a match regardless of the second match data attached to the match data storage area. It is a feature.

[0028]

The semiconductor memory of the present invention comprises the first input section and the second input section described above, and the plurality of output data storage areas constituting the output data storage section also have the first output data storage area and the second output data storage area. It is divided into the output data storage area of
Since the first input data read from the output data storage area of No. 2 is provided with the configuration in which the second input unit can be input again, the conventionally proposed semiconductor memory shown in FIGS. The tree structure data can be searched in the same manner as.

Further, the semiconductor memory of the present invention includes a first mask circuit for masking the first search data inputted from the first input section, and a second search circuit inputted from the second input section. A second mask circuit for masking the search data is provided, and the second input section is provided with an input selector so that the search data from the outside can be input to the second input section. Therefore, for example, the simple conversion table data is stored with the first matching data storage area and the first output data storage area as a first pair, and
The matching data storage area and the second output data storage area are used as a second pair to store the simple conversion table data, and the second input section side is masked to retrieve the first pair. Then, the first input unit side is masked and the second pair can be searched. Therefore, it is possible to prevent waste that would occur when the conventionally proposed semiconductor memory (see FIGS. 7 to 9) advantageous for handling tree-structured data is forcibly applied to handle simple conversion table data. A semiconductor memory suitable for handling both structural data and simple conversion table data is configured. Further, the tree structure data can be stored in each part of the coincidence data storage unit and the output data storage unit, and the simple conversion table data can be stored in the other parts without waste.

[0030]

EXAMPLES Examples of the present invention will be described below. Figure 1
FIG. 3 is a block diagram showing a structure of a semiconductor memory according to an embodiment of the present invention. The data read out by the search is output data storage unit 11 which constitutes the semiconductor memory 100.
0 is stored as output data. The output data storage unit 110 is provided with a large number (here, n) of output data storage areas 110_0, ..., 110_k, ..., 110_n, and each output data storage area 110_0 ,.
10_k, ..., 110_n are the first output data storage areas 110_0_1, ..., 110_k_1, ..., 110_n.
_1 and the second output data storage area 110_0_2, ...,
110_k_2, ..., 110_n_2.

Each first output data storage area 110_0_
1, ..., 110_k_1, ..., 110_n_1 store the respective first output data C ₀ , ..., C _k ..., C _n, and the respective second output data storage areas 110_0_2 ,.
110_k_2, ..., 110_n_2 store the respective second output data D ₀ , ..., D _k ..., D _n . The output data read from the output data storage unit 110 (first
Output data C _k and second output data D _k ; which are represented here by the subscript k) are input to the output selector 120 and selectively selected by the select signal C2 as the first output data C _k or The second output data D _k is output from the output selector 120 to the outside of the semiconductor memory 100.

Further, the read first output data C _k
Is also input to the input selector 130. Search data can also be input from the outside to the input selector 130, and the first output data C _k or the search data input from the outside can be selectively supplied by the select signal C1.
The second search data is input to the data register 140 (register in the present invention).

Further, in the semiconductor memory 100, the data on the searching side is stored in the matching data storage section 150. In the match data storage unit 100, a large number (n) of match data storage areas 150_0, ..., 150_k ,.
150_n are provided, and each matching data storage area 1
50_0, ..., 150_k, ..., 150_n are the first matching data storage areas 150_0_1 ,.
1, ..., 150_n_1 and second matching data storage area 1
50_0_2, ..., 150_k_2, ..., 150_n_
It consists of two. First matching data storage area 1
50_0_1, ..., 150_k_1, ..., 150_n_
1 stores the respective first match data A ₀ , ... A _k , ..., A _n, and the respective second match data storage areas 150_0.
The second coincidence data B ₀ , ... B _k , ..., B _n are stored in _2, ..., 150_k_2, ..., 150_n_2.

Each matching data storage area 150_0, ..., 1
50_k, ..., 150_n are output data storage areas 1
10_0, ..., 110_k, ..., 110_n, respectively, and each first match data A _k (represented by the subscript k), each second match data B _k , each first output data C _k , And each of the fourth output data D _k forms each data set.

The first search data input from the outside is
The data is set in the data register 160 and further input to the match data storage unit 150 via the mask circuit 170,
Each of the first matching data storage areas 150_0, ..., 150_
Each of the first match data A stored in k, ..., 150_n
_0, ... A _k, ..., are compared with each A _n. In addition, the first mask data is input from the outside to the mask register 1
It is set to 80 and input to the mask circuit 170. The mask circuit 170 is a circuit that masks each bit by the first mask data. Specifically, the masked bit is the first search data set in the data register 160. And each first match data storage area 150_0_1, ..., 150_k_
, ..., 150_n_1, the first match data A ₀ , ... A _k , ..., A _n , regardless of the value (logic “0” or logic “1”), they match each other Treated as.

The second search data input from the outside or the first output data C _k read from the output data storage unit 100 is input to the input selector 130 and the select signal is input as described above. One of them is output from the input selector 130 according to C1, is set in the data register 140 as the second search data, and is further passed through the mask circuit 190 to the matching data storage unit 150.
Entered in. The second search data input to the match data storage unit 150 is stored in each second match data storage area 1
50_0_2, ..., 150_k_2, ..., 150_n_
Each of the second match data B ₀ , ... B _k , ...,
It is compared with each of B _n . The second mask data is input from the outside, set in the mask register 200, and input to the mask circuit 190. This mask circuit 1
The function of 90 is similar to that of the mask circuit 170 described above.

Further, the matching data storage unit 150 and the output data
A match detection circuit unit 210 is provided between the data storage unit 110 and the data storage unit 110.
The match detection circuit section 210 has
Each match detection circuit 210_0, ..., 2 corresponding to the tasset
10_k, ..., 210_n are provided. Above
Thus, the first register set in the data register 160
Search data and first matching data storage area 150_0_
1, ..., 150_k_1, ..., 150_n_1
Each first matching data A₀ ,… A_k ,…, A_n Ratio
Is compared and set in the data register 140
Second search data and each second matching data storage area 15
0_0_2, ..., 150_k_2, ..., 150_n_2
Each second match data B stored in₀ ,… B_k ,…, B
_n And the matching data case
One corresponding to the storage area 150_k (represented by the subscript k)
A match signal is output from the match detection circuit 210_k. this
Output this match signal by outputting the match signal
Output data storage corresponding to the matched match detection circuit 210_k
From the area 110_k, the output data storage area 110_
First output data storage area 110_k_1 forming k
And the second output data storage area 110_k_2, respectively.
The stored first output data C_k And the second output data
TA D _k Is read. This read first output data
Data C_k And the second output data D_k As described above
In response to the select signal C2 input to the force selector 120
Either one is output to the outside and the first output
Data C_k Is also input to the input selector 130,
Second search data for the next search according to the traffic signal C1
Also used as.

When the tree structure data is stored in the semiconductor memory 100 shown in FIG. 1 and is searched, the text data used in the description of the conventionally proposed semiconductor memory (see FIGS. 7 to 9) is changed to the first data. By associating the search data and the node number with the second search data and outputting the second output data D _k from the output selector to the outside, the same as the conventionally proposed semiconductor memory (see FIGS. 7 to 9) can be obtained. You can get the function. Further, when the simple conversion table data is stored and searched in the semiconductor memory 100 shown in FIG. 1, for example, the first matching data storage area 150_0_1, ...
50_k_1, ..., 150_n_1 and the first output data storage areas 110_0_1, ..., 110_k_1, ..., 1
10_n_1 as the first pair, the first matching data storage areas 150_0_1, ..., 150_k_1, ..., 15
Data to be searched (for example, JIS code) is stored in 0_n_1, and the first output data storage areas 110_0_1, ..., 110_k_1 ,.
It is possible to store the data to be searched (eg, a new JIS code) in _1 and input the search data via the data register 160, and obtain the output data corresponding to the input search data. Further, similarly to this, the second matching data storage areas 150_0_2, ..., 150
_K_2, ..., 150_n_2 and the second output data storage areas 110_0_2, ..., 110_k_2, ..., 110
A similar search can be performed with _n_2 as the second pair. Therefore, the semiconductor memory shown in FIG. 1 has the coincidence data storage unit 150 and the output data storage unit 110 even when the simple conversion table data is stored and searched.
There is no useless area, and it is effectively used. As described above, the semiconductor memory 110 shown in FIG. 1 is suitable for searching both tree structure data and simple conversion table data.

FIG. 2 is a circuit diagram showing an example of the selector.
is there. The semiconductor memory 100 shown in FIG.
The input 120 and the input selector 130 are used.
These are the output selector 120 and the input selector 130, respectively.
As such, the selector 300 having the configuration shown in FIG. 2 is adopted.
can do. This selector 300 has
Are two (n + 1) -bit data {A _n , A_n-1 ，
…, A₀ }, {B_n , B_n-1 ,…, B₀ } Is entered
It First data {A_n , A_n-1 ,…, A₀ } Is each
First AND gate 310_n, 310_n-
1, ..., 310_0 and the second data {B
_n , B_{n- 1} ,…, B₀ } Is for each second bit for each second
Gates 320_n, 320_n-1, ..., 320_0
Entered in. In addition, each first AND gate 310_n,
310_n-1, ..., 310_0 have select signals CS
Is also input, and each second AND gate 320_n, 320
The select signal CS is inverted to _n-1, ..., 320_0.
Is entered and entered. When the select signal CS is logic "1"
If the first data {A_n , A_n-1 ,…, A₀ } Is each
AND gate 310_n, 310_n-1, ...
OR_gates 330_n, 3 via 310_0
This selector via 30_n-1, ..., 330_0
It is output from 300. On the other hand, the select signal CS is logical
In case of ‘0’, the second data {B_n , B_n-1 ,…, B
₀ } Is the second AND gate 320_n, 320_n-.
1, ..., 320_0, and OR gate 330
_N, 330_n-1, ..., 330_0
It is output from the selector 300. Thus, the selector
There are two sets of data {A_n, A_n-1 ,…, A₀ },
{B_n , B_n-1 ,…, B₀ } Is input and the selection
The first data {A_n , A_n-1 ，
…, A₀ } Or the second data {B_n , B_n-1 ，… ，
B₀ } Is output from the selector 300.

FIG. 3 is a diagram showing an example of a data register, a mask register, and a mask circuit. In the semiconductor memory 100 shown in FIG. 1, two sets of the circuit configuration shown in FIG. 3 are used as a data register 160, a mask register 180, a mask circuit 170, a data register 140, a microphone register 200, and a mask circuit 190. However, here, the data register 160, the mask register 180, and the mask circuit 170 will be described because of the reference numerals and the like. However, the same applies to the other side.

Data register 160, mask register 1
80 includes (n + 1) D-type flip-flops.
160_n, 160_n-1, ..., 160_0; 18
0_n, 180_n-1, ..., 180_0 are provided
And a D-type flip-flop that constitutes the data register 160.
Of the rops 160_n, 160_n-1, ..., 160_0
Search data {ID_n , ID_n-1 ,…, I
D₀ } Is input bit by bit, and the mask register 180
D-type flip-flops 180_n and 180_
Mask data is input to the D input terminals of n-1, ..., 180_0.
{MD_n , MD _n-1 ,,, MD₀ } Is input bit by bit
To be done. In addition, these D-type flip-flops 160_
n, 160_n-1, ..., 160_0; 180_n, 1
Clock input terminals CL of 80_n-1, ..., 180_0
A clock signal is input to K and the clock signal rises.
Search data and mask entered at the rising timing
Each of the data is a data register 160, a mask register
It is set on the star 180.

Further, the mask circuit 170 has 2 (n + 1)
OR gates 171_n, 171_n-1, ..., 17
1_0; 172_n, 172_n-1, ..., 172_0
Is provided. Each OR gate 171_n, 171_
One input terminal of each of n-1, ..., 171_0 is connected to each D-type flip-flop 16 that constitutes the data register 160.
0_n, 160_n-1, ..., 160_0 are connected to the Q output terminals of the OR gates 172_n, 172_n-.
, ..., 172_0 has one input terminal D-type flip-flop 160_n, 160_n-1, ..., 160_0.
, Which is connected to the Q ^* output terminal that outputs a signal having a logic opposite to that of the Q output terminal. Also, each two OR gates 171_
n, 172_n; 171_n-1,172_n-1;
The other input terminals of 171_0 and 172_0 are the D-type flip-flops 1 that form the mask register 180.
, 80_n, 180_n-1, ..., 180_0 are connected to the Q output terminals. Here, for example, the data register 1
When the search data ID _n of logic “1” is input to the D-type flip-flop 160_n forming the circuit 60 and set at the rising edge of the clock signal, the flip-flop 1
A signal of logic "1" is output from the Q output terminal of 60_n and a signal of logic "0" is output from the Q ^* output terminal, and these logic "1" and logic "0" signals are respectively OR gates 171_n and 17.
It is input from one of the input terminals 2_n. Further, the search data I of logic '1' is stored in the D-type flip-flop 160_n
When the mask data MD _n of logic '0' is set in the D-type flip-flop 180_n forming the mask register 180 when D _n is set, the logic '0' is output from the Q output terminal of the D-type flip-flop 180_n. A signal of "0" is output and the signal of logic "0" is input from the other input terminals of the two OR gates 171_n and 172_n. At this time, the logic "1" is output from the OR gate 171_n.
Signal SD _n , and the OR gate 172_n outputs the signal SD _n ^* of logic “0”. On the contrary, the D-type flip-flop 160_n forming the data register 160.
Is set to the search data ID _n of logic "0", and the mask data MD _n of logic "0" is also set to the D-type flip-flop 180_n which constitutes the mask register 180.
Is set, the OR gate 171_n outputs the signal SD _n of logic "0" and the OR gate 172_n outputs the signal SD _n ^* of logic "1".

Further, D which constitutes the mask register 180
When the mask signal MD _n of logic “1” is set in the type flip-flop 180 — _n, the search data ID _n set in the D-type flip-flop 160 — _n forming the data register 160 is set to logic “1” or logic “0”. Both OR gates 171_n, 172
The signals SD _n and SD _n ^{* of} logic “1” are output from _n. That is, the mask data {MD _n , MD _n-1 , ..., MD in which all bits are logical "0" in the mask register 180.
₀ } is set, the search data set in the data register 160 {ID _n , ID _n-1 , ..., ID ₀ }
However, the signal {SD _n , SD
_n−1 , ..., SD ₀ } is output from the mask circuit 170, and if the mask data {MD _n , MD _n-1 , ..., MD ₀ } includes the data MD _i of logic '1', the data is output. Output signal SD of mask circuit 170 corresponding to MD _{i
Both i} and SD _i ^* are signals of logic “1”.

The OR circuit 17 constituting the mask circuit 170
1_n, 171_n-1, ..., 171_0; 172_
Connection of n, 172_n-1, ..., 172_0 output terminals
The destination will be described later. Here, the mass for each bit is
Apply signal (Signal SD_i , SD _i ^*Both are logical ‘1’
The configuration that can be done is explained.
If it is not necessary to apply a mask for each
Mask circuit, second mask circuit (semiconductor memory shown in FIG.
100 mask circuits 170, 190) as a unit
To mask or unmask
You can also FIG. 4 shows a part of the semiconductor memory shown in FIG.
FIG. No k here to avoid complexity
Only the part of the eye data set is shown. This
The basic configuration of the circuit shown here is shown in Fig. 9.
It is similar to the circuit shown, so its operation is simple here.
Only explain to. Note that for simplicity, the signal line is
The signal transmitted through the signal line
Do not use the same symbol.

A data line S extending from mask circuits 170 and 190 (see FIG. 1) each having the structure shown in FIG.
D _n , SD _n-1 , ..., SD ₀ and data bar line S
D _n ^* , SD _n-1 ^* , ..., SD ₀ ^* extend to the first match data storage area 150_k_1 and the second match data storage area 150_k_2 as shown in the drawing, and these first match data storage areas are stored. The gates of the N-type transistors connected in series, which form the region 150_k_1 and the second match data storage region 150_k_2, are connected to the data lines SD _n and S, respectively.
D _n-1 , ..., SD ₀ or each data bar line SD _n ^* , S
It is connected to _{one of} D _n-1 ^* , ..., SD ₀ ^* .
Connection to either one of the first match data storage area 150_k_1 and the second match data storage area 150_k_2 results in the first match data A _k ,
This corresponds to the storage of the second match data B _k . When the signal of logic '1' is transmitted to both the data line SD _i and the data bar line SD _i ^* , the gate of the transistor corresponding to the transistor is connected to either the data line SD _i or the data bar line SD _i ^* . Even if it is connected, it is in a conductive state.
That is, regarding the bit i, it is considered that the data match.

When the tree structure data is stored and a search is performed, both the first match data storage area 150_k_1 and the second match data storage area 150_k_2 are simultaneously used for the search, and the match detection circuit 210_k When the coincidence signal of logic “1” is output, the first output data C _k
And the second output data D _k are read out, and the first output data C _k is used for the search in the next step, if necessary.

When the simple conversion table data is stored and searched, the first matching data storage area 15 is used.
0_k_1 and second matching data storage area 150_k_2
Mask one of the two and use the other for search,
One of the read first output data C _k or second read data D _{k is} the output selector 1 shown in FIG.
It is output to the outside via 20.

FIG. 5 is a schematic diagram showing an example of the data structure stored in the semiconductor memory shown in FIG. As shown in this figure, both the tree structure data and the simple conversion table data can be stored in one semiconductor memory. Here, in the embodiment shown in FIG. 1, the first output data C _k read from the output data storage unit 110.
The second output data D _k and the second output data D _k may be output without passing through the output selector 120, and thus the output selector is not always necessary. In addition, the data register 16
0 and the mask registers 180 and 200 are not always necessary, and the timing of data input from the outside may be controlled externally.

[0049]

As described above, the semiconductor memory of the present invention comprises the first and second mask circuits in addition to the structure of the conventionally proposed semiconductor memory described with reference to FIGS. Therefore, a semiconductor memory suitable for searching tree-structured data as well as the conventionally proposed semiconductor memory and also suitable for searching simple conversion table data is configured.

[Brief description of drawings]

FIG. 1 is a block diagram showing a structure of a semiconductor memory according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing an example of a selector.

FIG. 3 is a diagram showing an example of a data register, a mask register, and a mask circuit.

FIG. 4 is a circuit diagram showing a part of the semiconductor memory shown in FIG.

5 is a schematic diagram showing an example of a data structure stored in the semiconductor memory shown in FIG.

FIG. 6 is a diagram showing an example of text arranged in a tree structure.

FIG. 7 is a diagram showing an example of a semiconductor memory according to a conventional proposal.

8 is a circuit diagram showing a part of the semiconductor memory shown in FIG.

9 is a circuit diagram in which the circuit shown in FIG. 8 is further embodied.

[Explanation of symbols]

100 semiconductor memory 110_0, ..., 110_k, ..., 110_n output data storage area 110_0_1, ..., 110_k_1, ..., 110_n
_1 First output data storage area 110_0_2, ..., 110_k_2, ..., 110_n
_2 Second output data storage area 130 Input selector 140, 160, 180, 200 Data register 150_0, 150_k, ..., 150_n Matched data storage area 150_0_1, 150_k_1, ..., 150_n_1
First match data storage area 150_0_2, 150_k_2, ..., 150_n_2
Second match data storage area 170, 190 Mask circuit 210 Match detection circuit section 210_0, 210_k, ..., 210_n Match data storage area 300 Selector

Claims (1)

[Claims] 1. A predetermined first constituting the predetermined output data.
And an output data storage unit having a large number of output data storage areas each of which stores first and second output data storage areas, and a first input section for inputting first search data from the outside. An input unit, a register in which second search data is stored, and search data input from the outside and the first output data read from the output data storage unit are selectively used as the second search data. A second input section having an input selector for inputting to the register, storing predetermined first and second matching data,
The first and second match data storage areas for comparing the first and second match data with the first and second search data input from the first and second input units, respectively. A match data storage unit including a plurality of match data storage areas corresponding to the plurality of output data storage areas, respectively, arranged between the corresponding match data storage areas and the output data storage areas, and corresponding to each other. Each of the first and second match data stored in the first and second match data storage areas and each of the first and second search data constituting the match data storage area A coincidence detection unit including a large number of coincidence detection circuits that output a coincidence signal for instructing the reading of the output data stored in the corresponding output data storage area when the coincidence occurs, A plurality of first match data storage areas are matched with the first match data regardless of the first match data attached to the first match data storage area. A first mask circuit for handling as
And a plurality of second matching data storage areas,
A second mask circuit for treating the second match data as a match with the second search data regardless of the second match data attached to the match data storage area. A semiconductor memory characterized in that.