JPH07312091A - Use method for associative memory and associative memory - Google Patents

Abstract

PURPOSE:To retrieve only desired data having desired attribute by forming storage of data of a group structure and structure of a memory suitable for storage. CONSTITUTION:Attribute data is stored in upper 2 bits of each memory word 11-1, 11-2,...11-m. Also, data attached to each attribute is stored in residual m-2 bits. Upper 2 bits of a reference data register 12 are made an attribute data register 12-1 storing attribute data for retrieving. Also, a residual part of the reference data register 12 (data register 12-2) is made a reference data register in the conventional meaning. And attribute data and the reference data in the conventional meaning are stored in the reference data register 12 and retrieving is performed. Thereby, desired stored data to which an attribute indicating attribute data used for retrieving is attached is retrieved. Therefore, retrieving the same stored data having different attributes is excluded.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory word in which each stored data is stored in each of a plurality of memory words, and the reference word input is used to search for a memory word in which a predetermined stored data is stored. Regarding memory.

[0002]

2. Description of the Related Art Conventionally, an associative memory equipped with a search function as described above (Associative Memory)
y, content addressable memory; Content Addr
ESSABLE MEMORY) has been proposed. FIG. 14 is a circuit block diagram showing an example of a conventional associative memory.

In the associative memory 10, a large number of memory words 11_1, 11_2, each of which has m bits as one word, and which are composed of m-bit memory cells arranged in the lateral direction of the drawing.
..., 11_n are provided. Also, this associative memory 1
Reference numeral 0 is provided with a reference data register 12 into which 1-word reference data is input and a mask data register 13 into which mask data for masking the reference data for each bit is stored, and the reference data latched in the reference data register 12 Of all or a predetermined part of the bit pattern not masked by the mask data stored in the mask data register 13 and each memory word 11
, 11_n of the data stored in _1, 11_2, ...
11_2, ..., 11_n corresponding to each of the match lines 14_1, 14_2 ,.
…, Matching lines 14_1, 14_2, ... For 11_n
A match signal of logic "1" is output to 14_n. Other match lines 14_1, 14_2, ..., 14_n remain at logic '0'.

These matching lines 14_1, 14_2, ...,
The signal output to 14_n corresponds to each match flag register 1
5_1, 15_2, ..., 15_n. Here, as an example, as shown in the figure, the match flag registers 15_1, 15_2, ...
It is assumed that "1", "1", "0", ..., "0", "0" are stored. These match flag registers 15_
The signals stored in 1, 15_2, ..., 15_n are input to the address encoder 16, and from the address encoder 16, a match flag register (here, the match flag register 15_2 and the match flag are stored, in which a signal of logic “1” is stored. The address signal corresponding to the match flag register having the highest priority among the registers 15_3) is output. Here, it is assumed that the younger the subscript, the higher the priority. Therefore, here, the match flag register 1
The memory address corresponding to 5_2 is output. Address signal AD output from this address encoder 16
Are input to the decoder 17 as needed. The decoder 17 decodes the input address signal AD and decodes the word lines 18_1 and 18 provided for the memory words 11_1, 11_2, ..., 11_n, respectively.
Input address signal A of _2, ..., 18_n
The access signal is output to any one word line (here, word line 18_2) corresponding to D. As a result, the data stored in the memory word 11_2 corresponding to the word line 18_2 to which the access signal is output is read to the output register 19.

Next, by changing the signal stored in the match flag register 15_2 to "0", this time the memory word 11_ corresponding to the match flag register 15_3 is changed.
3 addresses can be obtained. FIG. 15 is a functional block diagram of a conventional associative memory. Function data FUN_DATA and reference data REF_DATA are input to the associative memory. The function data FUN_DATA is data that defines the function of this associative memory. For example, the function data FUN_D
When ATA is “01”, it means that the reference data REF_DATA input at the same time is mask data, and the data is stored in the mask data register.
Further, for example, when the function data FUN_DATA is “10”, the reference data REF input at the same time is input.
A search using _DATA is performed, and the input reference data REF_DATA is masked by the mask data stored in the mask data register and then supplied to each memory word via the data line drive circuit. .
When the data stored in the memory word matches the input data, the matching signal of logic "1" is stored in the corresponding matching flag register.

As described above, the associative memory 10 searches the contents (data) stored in a large number of memory words 11_1, 11_2, ..., 11_n by using all or a predetermined part of the reference data and matches them. A memory configured to obtain an address of a memory word having data to be read, and to read the entire data stored in the memory word as needed.

[0007]

In performing a search using the associative memory as described above, when the data to be searched has a group structure, that is, a plurality of data forming each group There are some problems that must be solved when each attribute is attached.

The first of these problems is how to retrieve desired data from a large number of data forming a group structure. The first problem will be described below with reference to the drawings. FIG. 16 is a diagram showing an array of data with attributes stored in the associative memory.

A large number of memory words constituting the associative memory are grouped into groups of four, and the first memory word in each group stores, for example, data with "attribute 0" called "name". The second memory word in the set stores, for example, data with "attribute 1" called "date of birth", and so on. Data to which "attribute 2" and "attribute 3" are attached is stored. Here, each data stored in each memory word is represented by the alphabet A,
It is indicated by B, ... In addition, hereinafter, one set of data groups to which each attribute is added as described above is referred to as a “data set”.

Here, the attribute 0 shown at the top of FIG.
There is a case where the data of the same bit pattern is stored even if the attributes are different, such as the data of "A" and the data of the attribute 1 described in the next stage is also "A". . In this case, if you want to search only the data'A '(for example, the person whose name is'A') belonging to the attribute 0, if you input the data'A 'as reference data,
Not only data'A 'belonging to attribute 0, but also other attributes 1,
The data'A 'belonging to the second and third are also searched at the same time, and it is necessary to reselect the data belonging to the attribute 0 from the searched data after the search, and the operation is extremely complicated. Therefore, there is a problem that the selection also takes time.

A second problem in the case where the data (data set) forming the group structure is the search target is how to improve the flexibility of the search. For example, even if it is possible to search for individual data such as the data “A” with the “attribute 0” or the data “B” with the “attribute 2” by some method, for example, the data “A” The problem is how to search for a data set including both "A" with "" and data "B" with "attribute 2."

In this case, it is said that the individual data such as the data "A" with the "attribute 0" and the data "B" with the "attribute 2" can be searched as described above. It is premised that a large number of data sets corresponding to this, including the data “A” with the “attribute 0”, are searched for, and the data “B” with the “attribute 2” is searched. Also, a large number of data sets that normally correspond to this are searched, and from among the searched large number of data sets, data “A” with “attribute 0” and data with “attribute 2” are added. It is necessary to re-select the data set that satisfies both the data “B” and the first data described above.
As in the case of (1), the operation is extremely complicated and takes time.

On the other hand, in the conventional associative memory technology, when the data having a group structure is handled but not the normal data, the data width to be subjected to the match search is set to two words or more. Techniques for expanding to words are known and are described below. Figure 1
FIG. 7 is a block diagram showing an example of an associative memory having a data expansion function. The components corresponding to the components of the associative memory shown in FIG. 14 are denoted by the same reference numerals as those shown in FIG. 14, and the duplicate description of those components will be omitted.

The match lines 14_1, 14_2, ... Extending from the memory words 11_1, 11_2, ... Are connected to one input terminal of each AND gate 20_1, 20_2 ,. In addition, each AND gate 20_1, 20_
The other input terminals of 2, ...
The output terminals of 1_3, ... Are connected, and one input terminal of each OR gate 21_2, 21_3, ... Is connected to the initial search control line 22. However, the OR gate corresponding to the uppermost AND gate 20_1 in the figure is omitted, and the initial search control line 22 is directly connected to the input terminal of the AND gate 20_1.

The output terminals of the AND gates 20_1, 20_2, ... Are connected to the first flag registers 23_1, 23_, respectively.
, ..., and the output terminals of the first flag registers 23_1, 23_2, ... Are connected to the output terminals of the second flag registers 24_1, 24_2 ,. Each second flag register 24_1, 24_
The output terminals of 2, ... Are connected to the priority encoder 16 shown in FIG. 14 (not shown in FIG. 17), and to the input terminals of the OR gates 21_2, 21_3, ... Corresponding to the memory words adjacent to the lower part of FIG. It is connected.

First and second flag registers 23_1, 24_1, 23_2, 24_2, ... Corresponding to each other
14 is associated with each flag register 15_1, 1 shown in FIG.
It corresponds to 5_2, ... First flag register 23_
1, 23_2, ... and the second flag registers 24_1, 24_2
A match result latch signal S1 output to the match result latch control line 25 is input to both 4_2, ..., And the input data input from each data input terminal is latched by the match result latch signal S1. Input data at the rising edge a of the match result latch signal 51 is latched in the first flag registers 23_1, 23_2, ..., And the match result latch signal S1 rises in the second flag registers 24_1, 24_2 ,. The input data at the time of falling b is latched.

In the associative memory configured as described above, a match search is performed as follows. Here, as shown in the figure, each memory word 11_1, 11_
2, 11_3, 11_4, 11_5, 11_6 ...
It is assumed that each reference data A, B, C, D, C, F, ... Is stored. Here, when searching each reference data independently, when inputting the reference data REF_DATA and performing the search, the initial search timing signal S2 is output to the initial search control line 22. Here, the reference data REF_DA
Assuming that the data “B” is input as TA, a match signal of logic “1” is output to the match line 14_2 corresponding to the word memory 11_2 in which the data “B” is stored and is input to the AND gate 20_2. At the same time, since the first search timing signal S2 is input to the AND gate 20_2 via the OR gate 21_2, the AND gate 20_2 outputs a signal of logic "1". At this time, the other match lines 14_1; 14_3, 14_4
Since a signal of logic “0” is output to ..., Other AND gates 20_1; 20_3, 20_4 corresponding thereto are output.
A signal of logic "0" is output from.

The signal of logic '1' output from the AND gate 20_2 is latched in the first flag register 23_2 at the timing of the rising edge a of the match result latch signal S1 output to the match result latch control line 25, and It is latched in the second flag register 24_2 at the timing of the subsequent trailing edge b of the match result latch signal S1.

Further, at each timing when the signal of logic "1" is latched in the first flag register 23_2 and the second flag register 24_2, another first flag register 2
3_1; 23_3, 23_4, ... And the other second flag registers 24_1; 24_3; 24_4, ... Latch a signal of logic '0'. In this way, each second flag register 24_1, 24_2, 24_3, ...
The signals of the logic "0", "1", "0", ... Latched by are input to the priority encoder 16 shown in FIG. 5, and the address signal AD of the word memory 11_2 is obtained.

Next, a case where a search with an expanded data width is performed will be described. Here, a case will be described where 2-word data consisting of data “B” and data “C” expanded to 2 words is searched. In this case, first, data “B” is searched in the same manner as above. As a result, the signal of logic "1" is latched in the first and second flag registers 23_2 and 24_2 corresponding to the word memory 11_2. Next, the data “C” is input as the reference data REF_DATA to perform the search, but at this time, the first search control line 22 does not output the first search timing signal S2, and the first search control line 22 has the logic “0”. Keep the condition. When data “C” is input as the reference data REF_DATA and a search is performed, the matching lines 14 corresponding to the two word memories 11_3 and 11_5 shown in FIG.
A match signal of logic "1" is output to _3 and 14_5, but the second flag register 2 is output to the OR gate 21_3.
Since the signal of logic "1" latched by 4_2 is input, the match signal of the match line 14_3 is AND gate 2
0_3, and the first and second flag registers 23
A signal of logic "1" representing a match is latched at _3 and 24_3. On the other hand, since the signal of logic '0' latched by the second flag register 24_4 is input to the OR gate 21_5, the match signal of the match line 14_5 is blocked by the AND gate 20_5, and the first and second flag registers 23_5 and 24_5 are latched with a signal of logic "0" indicating a mismatch. In this way, coincidence detection of 2-word data composed of a pair of data “B” and data “C” is performed. Matching detection of data of 3 words or more is similarly performed.

Although the associative memory shown in FIG. 17 has a data width expansion function, data expanded to 2 words, 3 words, etc. must be stored in adjacent memory words in a predetermined order. If they are stored in memory words separated from each other or in the reverse order, for example, in the order of data'C 'and data'B', then matching detection combining a plurality of data is performed. I can't. That is, the above-described data width expansion function is not suitable for searching for data having a group structure.

Further, in the case of performing a search using the associative memory, regardless of whether or not group structure data is handled, conventionally, for example, an associative memory (see FIG. 17) having a built-in data width expansion function is used. In some cases, the search purpose may be achieved by performing a series of multiple consecutive searches, such as when performing a search using the data width expansion function. In the same manner, the purpose of the search is achieved by performing a series of searches consisting of a plurality of continuous searches, for example, when searching for a match of a plurality of data in one data set, as described above. May be done. As a third problem that arises in that case, how is the associative memory configured so that it is possible to efficiently perform a plurality of consecutive continuous searches for group-structured data having a more complex data structure than in the past? There is a problem. In other words, nothing has been known about the structure of the associative memory and the method of using it, which searches for data of a group structure that requires random and plural searches at high speed and flexibly.

In view of the above-described various problems in performing group structure data retrieval using an associative memory, the present invention uses a content addressable memory suitable for group structure data retrieval and a group structure data retrieval method. The purpose is to newly provide a structure of an associative memory suitable for data storage and retrieval.

[0024]

A method of using an associative memory according to the present invention for achieving the above object is to store digital data in each of a plurality of arranged memory words, input reference data, and input. In a method of using an associative memory for retrieving a memory word in which digital data having a bit pattern that matches all or a predetermined part of the reference data that has been stored, each memory word is divided into two parts in the associative memory. Digital data is stored in one of the stored first areas, and attribute data representing the attributes of the digital data is stored in the second area of each memory word excluding the first area, and the predetermined value is stored in the associative memory. By associating the set of attribute data and predetermined digital data as the reference data, the association In Mori, it is characterized in that to perform the search of the memory word digital data is stored having a predetermined attribute represented by the attribute data input with corresponding to a predetermined digital data input.

The first associative memory of the associative memory of the present invention stores digital data in each of a plurality of arranged memory words, receives reference data, and receives all the input reference data. Alternatively, in an associative memory that searches for a memory word in which digital data having a bit pattern that matches a predetermined part of the bit pattern is stored, (1) each memory word has a first area in which each digital data is stored; The attribute data representing the attribute of the digital data stored in the first area has a bit pattern which cyclically repeats in a cycle corresponding to the number of attributes in the address order of each memory word.

In the first associative memory, each memory word constitutes attribute data having a bit pattern which cyclically repeats in a cycle corresponding to the number of attributes in the address order of each of the memory words. Second
May be fixedly stored in the area. A second associative memory of the associative memory of the present invention stores digital data in each of a plurality of arranged memory words, receives reference data, and inputs all or predetermined reference data. In an associative memory that searches a memory word in which digital data having a bit pattern that matches a part of a bit pattern is stored, (2) out of the entire range of addresses assigned to each of the plurality of arranged memory words, It is characterized in that a search address range setting circuit for setting an address range of a memory word to be matched and compared with input reference data is provided.

The third associative memory of the present invention which achieves the above object is (3_1) a plurality of memory words (3_2) storing a plurality of stored data belonging to each of a plurality of data groups for each stored data. When a match between the stored data stored in the memory word of and the input reference data is detected,
A first mode in which a match signal representing a match is output to a match line corresponding to the predetermined memory word, and a match is detected in a predetermined memory word during the current search, and the predetermined memory is detected during the previous search. When a match is detected in any of the memory words that respectively store the stored data forming the data group to which the stored data stored in the word belongs, a match signal is output to the match line corresponding to the predetermined memory word. It is characterized in that a coincidence detection circuit having a second mode is provided.

The third associative memory of the present invention is the first one.
As one aspect, it can be configured as follows.
That is, in the third associative memory of the present invention configured as described above, each of (3_3) includes a plurality of storages belonging to a plurality of data groups each including a plurality of stored data sets each including a pair of an attribute and data. A plurality of memory words for storing data for each stored data (3_4) Among reference data composed of an attribute in the stored data stored corresponding to each of the plurality of memory words and an input pair of the attribute and the data (3_5) Attribute match detection circuit for detecting a match / mismatch with the attribute of (3_5) The data in the stored data composed of a pair of the attribute and the data stored corresponding to each of the plurality of memory words, and the input attribute Data coincidence detection circuit (3_6) for detecting coincidence / non-coincidence with data in reference data formed of a pair with data (3_6) (3_7) a register for storing information on whether or not the stored data and the reference data match each other. A data line provided for each memory word group including memory words respectively storing the respective stored data forming the same data group ( 3_8) In response to the matching of the attributes detected at the time of searching by the corresponding attribute matching detection circuit provided corresponding to each of the plurality of memory words, the matching or mismatching search result of the corresponding register is displayed as described above. First switch circuit for transmitting to data line (3_9) Corresponding to each of the plurality of memory words, the corresponding attribute coincidence detection circuit and the corresponding data coincidence detection circuit are used to detect both the attribute and the data at the time of this search. When a match is detected and the information indicating the match from the previous search is output to the above data line Gate circuit for transmitting information indicating a match in the current search to the corresponding register (3_10) Attribute match at the time of the current search by the corresponding attribute match detection circuit provided corresponding to each of the plurality of memory words Is detected, the second switch circuit is provided for transmitting to the corresponding gate circuit the information indicating the match or mismatch at the time of the previous detection, which is output to the data line. To do.

In the third associative memory, an attribute which is provided for each of the plurality of memory words and determines whether the attribute in the stored data stored in the corresponding memory word is a predetermined attribute or not. A series of data lines including a discriminating circuit and the data lines between the memory words which are adjacent to each other across a plurality of memory word groups and which are provided corresponding to the plurality of memory words, respectively. It is preferable to have a configuration connected to.

Further, it is preferable that the third switch circuit is controlled by the attribute discriminating circuit or the data line connection control circuit provided for each memory word. Further, in the fourth associative memory of the present invention which achieves the above object, each stored data is stored in each of a plurality of memory words, and a plurality of reference data are sequentially input. A search auxiliary data sequential output unit that sequentially outputs each search auxiliary data for generating reference data to be compared with each stored data by combining is provided, and a memory word in which predetermined stored data is stored is searched. It is characterized by that.

The retrieval auxiliary data sequential output means is
Retrieval auxiliary data register group for storing a series of retrieval auxiliary data, control means for instructing and controlling the retrieval auxiliary data register group, and the control means, an address is defined, and address data representing the address is input together with reference data. It is preferable that, based on the address data input together with the reference data and the number of searches, the control means designated by the address data sequentially outputs the search assist data.

The search auxiliary data sequential output means includes a search auxiliary data register group for storing a series of search auxiliary data, a control means for indicating and controlling the search auxiliary data register group, and a channel for specifying the control means. Based on the designated data register, the control means designated by the channel setting data stored in the designated data register, and the number of searches by inputting the reference data,
The search assist data may be sequentially output.

Further, the fourth associative memory of the present invention may be provided with a reset terminal for inputting a sequence reset signal for initializing the output order of the search auxiliary data of the search auxiliary data sequential output means. preferable.

[0034]

According to the method of using the associative memory of the present invention, each memory word stores both the respective digital data and the attribute data representing the attribute of the digital data, and the set of the attribute data and the digital data is inputted as the reference data. Since the search is performed by searching, only desired data having a desired attribute can be searched.

The first associative memory of the present invention is a bit pattern in which the attribute data of each memory word is cyclically repeated in a cycle corresponding to the number of attributes in the address order of each memory word. An associative memory suitable for flexible and high-speed data retrieval is realized. Further, since the second associative memory of the present invention is provided with the grinding address range setting circuit for setting the address range of the memory word to be subjected to the coincidence comparison, the data corresponding to each attribute is stored in each address range. Stored in the memory word of, the address range in which the data having the desired attribute is stored is set at the time of search, and only the memory word within the address range is set as the search target, so that the desired attribute is added. Only desired data can be searched.

Further, in the case of the second associative memory, while the hardware configuration remains the same, only how to set the address range corresponding to each attribute is determined before use, and data having a different number of attributes can be stored. An associative memory that can be stored and retrieved and is extremely flexible is constructed. The third associative memory of the present invention has the above-mentioned second mode of the coincidence detection circuit of (3_2), and specifically, stores stored data including a pair of an attribute and data. In addition, in the search, reference data composed of a pair of attribute and data is input to perform the search, and the data line of (3_7) is provided, and the data line is connected to the data line by the first switch circuit of (3_8). It outputs whether the match was detected during the previous search, and the second switch circuit of (3_10) above takes in the signal of the data line to the gate circuit in response to the match of the attributes during the current search. , It is possible to search the stored data stored in the memory words in the same memory word group by an arbitrary combination.

Further, in the third associative memory of the present invention, the length of each data line may be fixedly set in accordance with the number of data constituting one data group (data set). Well, or in the middle of the data line, a large number of switch circuits and a large number of control lines for turning these switch circuits on and off are provided, and the number of switch circuits corresponding to the number of pieces of data forming one data group is set. The length of one data line may be changed by turning on / off the switch circuit of the above. However, the third switch circuit is provided for each memory word and each memory word is provided. If the third switch circuit is turned on and off in accordance with the attribute stored in or the new attribute bit, it is only necessary to store each stored data in each memory word. Automatically data lines are formed in accordance with the number of data constituting one data group. Further, in this case, the data lines are adaptively formed even if the data groups having different numbers of data are mixed.

In the fourth associative memory of the present invention, a plurality of search auxiliary data such as the mask data and the attribute data described above are stored in a writable manner, and when searching, reference data is input and which search auxiliary data is input. Since the data indicating whether or not to use is input, there is no need to rewrite the mask data during a series of searches, and the search procedure is simplified. The search speed of can be improved.

In yet another example, a plurality of search auxiliary data such as the mask data and the attribute data described above are stored in a writable manner. However, the difference from the above is that the search auxiliary data is controlled. Since it has a designated data register that rewritably stores data for designating the control means to be used, it is not necessary to specify which search auxiliary data to use for searching, and it is used for searching. New data need only be input to the designated data register only when the search assist data is changed, and the search procedure can be further simplified.

When performing a series of searches consisting of a plurality of searches, the search pattern, that is, first the first mask data and the first attribute data, is used, and then the same as above. In many cases, the search pattern can be typified in advance, such as using the first mask data and performing a search using the second attribute data different from the above. Therefore, in the fourth associative memory of the present invention, by adopting the concept of the control means for designating the search auxiliary data group and the address designating this control means, it is possible to sequentially input the address data together with the reference data. A search is performed, or a series of searches are performed by only once inputting channel designation data and then sequentially inputting reference data, and the search procedure is further simplified.

Further, if a reset terminal for initializing the search auxiliary data output order of the search auxiliary data sequential output means is provided, it is possible to reset only when necessary after the previous search is completed and start a new search. .

[0042]

EXAMPLES Examples of the present invention will be described below. FIG. 1 is a memory structure diagram of an embodiment of the present invention and corresponds to FIG. 16 in the conventional example. An area (second area referred to in the present invention) for storing attribute data representing the upper k bits (for example, 2 bits) of a memory word, each of which is composed of m bits (for example, 16 bits), which constitutes a general-purpose associative memory. And the remaining m−k bits (for example, 16−2 = 14 bits) are defined as an area (first area in the present invention) in which original data with those attributes is to be stored. , Store both attributes and data in each memory word. In searching, both the attribute and the data are searched. For example, if a search is performed for both "attribute 0" and data "A", the data shown at the top of FIG. 1 will be searched.

FIG. 2 is a block diagram of an associative memory for further explaining the above concept. Note that this associative memory is basically the same as the associative memory shown in FIG. 14 in that the drawing method is slightly different for convenience of description, but some of the blocks unnecessary for the description are omitted. Has been done. Further, the same blocks as the blocks of the associative memory shown in FIG. 14 are given the same numbers as those given in FIG. Each memory word 11_1, 1 consisting of m bits
Attribute data is stored in the upper 2 bits of 1_2, ..., 11_n, and data with each attribute is stored in the remaining m-2 bits. In the search, the upper 2 bits of the reference data register 12 are set as the attribute data register 12_1 in which the search attribute data is stored, and the remaining part of the reference data register 12 (data register 12_2) will be described with reference to FIG. At this time, the reference data register in the conventional meaning is used, and the attribute data and the reference data in the conventional meaning are stored in this reference data register 12 to perform a search. As a result, the desired stored data with the attribute represented by the attribute data used for the search is searched. That is, a search for the same stored data having different attributes is excluded.

Next, an embodiment of the first associative memory of the present invention, which is configured to store the attribute data fixedly, will be described. Although FIG. 2 can be used as it is for the description of one embodiment of the first associative memory of the present invention, the configuration of each memory word 11_1, 11_2, ..., 11_n corresponds to that of a conventional general-purpose associative memory. Is different.

FIG. 3 is a circuit diagram showing the structure of one memory word in one embodiment of the first associative memory of the present invention. This circuit is an example of a circuit configuration based on SRAM and in which a match with reference data is detected by a NAND type match detection circuit. The illustrated memory word includes a first attribute bit cell 120_1 and a second attribute bit cell 120_2.
A bit cell group 120 consisting of
Bit) SRAM structure memory cells 121_1, ...,
A memory cell group 121 including 121_m is formed.

In the first attribute bit cell 120_1, two transistors T1 and T2 serially connected to each other are formed between the bit line Zb1 and the bit bar line Zb1_, and these two transistors T1 and T2 are connected. The gate electrode of the transistor TC1_1 is connected to the point. The gate of the transistor T1 is set to logic "1" and the gate of the transistor T2 is set to logic "0". At this time, when "1" is applied to the bit line Zb1 and the inverted signal "0" is applied to the bit bar line Zb1_, which is connected to the attribute search register 12_1 shown in FIG. 2, the transistor T1 is turned on and the bit Line Zb1
Is applied to the gate of the transistor TC1_1, and this transistor TC1_1 is also turned on. This state is related to the first attribute bit cell 120_1.
This is a state in which the contents fixedly stored in the attribute bit cell 120_1 of “1” and the input attribute data for search match. On the contrary, when "0" is applied to the bit line Zb1 and "1" is applied to the bit bar line Zb1_, the transistor T
The gate of C1_1 becomes "0" and this transistor TC
1_1 is turned off. This is a non-coincident state regarding the first attribute bit cell 120_1.

Similarly, in the example shown in FIG. 3, in the second attribute bit cell 120_2, the data stored therein is the reverse of the data stored in the first attribute bit cell 120_1. Signal is "0" (bit line Zb2 is "0", bit bar line Zb2
When _ is '1'), the match state is obtained. That is, in the example shown in FIG. 3, when 2 of the attribute bits are (1, 0),
It will be in the state of'match '.

Further, the memory cells 121_1, ... 121_
The value m applied to the gates of the transistors T1 and T2 is set by the Q node and Q_node of the SRAM accessed by the decoder 17, and the match detection operation is the same as that of the attribute memory cells 120_1 and 120_2. Is the same. Transistors TC1_1, TC1_2, TC2_1, ..., TC serially connected to each other
In the NAND type match detection circuit 30 including 2_m and the like, a control transistor TC0 is formed at the left end of the figure, and a match detection amplifier 31 is formed at the right end of the figure, which is controlled by the control clock φ. First, the control clock φ is '0'
Then, the input node of the coincidence detection amplifier 31 is precharged by the precharge transistor 31a, whereby the output of the inverter 31b becomes "0". At this time, the control transistor TC0 is kept in the off state.

Each bit line, each bit bar line Zb1, Zb
1_; Zb2, Zb2_: Db1, Db1 _...; Db
Reference data is previously input from the attribute search register 12_1 and the reference data register 12_2 via m and Dbm_, and each of the above-mentioned attribute bit cells 120_1, 1
20_2 and each memory cell 121_1, ..., 121_
A match / mismatch is determined for each of m, and a NAND-type match detection circuit is configured for the matched cells.
Corresponding transistors TC1_1, TC1_2, TC
The gate voltage of 2_1, ..., TC2_m becomes "1",
The transistor turns on.

When the control clock φ becomes "1" in this state, the input node of the inverter 31b of the NAND type match detection circuit 31 corresponding to only the memory word in which all the cells match is discharged, and the inverter 31b outputs "1". A match signal of "1" is output, and "1" is stored in the corresponding match flag register 15. At this time, a match signal cannot be obtained unless there is a match between not only the stored data stored in the memory cells 121_1, ..., 121_m but also the attribute data. Therefore, by defining this attribute data in accordance with the attributes of each data forming each data set, it becomes possible to search for each attribute of each data set. In the associative memory in which the attribute data is preliminarily created in hardware as described above, the attribute data may be set as one of the control data in the attribute search register 12_1 shown in FIG. 2. Therefore, this associative memory should be used. By associative memory 1
It is possible to configure a system capable of accessing the outside without reducing the bit length for words.

FIG. 4 is a memory structure diagram of the second associative memory of the present invention. Here, a large number of memory words are divided into areas of attributes 0, 1, 2, and 3, and each data set is stored in each area separately. For example,
The uppermost data set (A, A, B, C) shown in Fig. 1
4 are distributed and stored in the respective uppermost memory words in the respective areas of attributes 0, 1, 2, and 3.

In the second associative memory embodiment of the present invention to be described below, for example, in order to retrieve the data with the attribute 1, only the area of the memory word corresponding to the attribute 1 is targeted for retrieval. It Specifically, for example, assuming that there are 100 data sets, at this time, the data of attribute 0 of each data set is stored in the address ranges 1 to 100 of the associative memory, and the data of attribute 1 is stored in the address ranges 101 to 200. Stores data, address range 301-400
Store the data of attribute data 2 in the address range 301
The data of the attribute data 3 is stored in 400. At this time, in order to perform the coincidence comparison on the data with the attribute 1, the address ranges 201 to 300 of the memory words in which the data with the attribute 1 are stored are set, and the set address range is set as the search target. It is a thing. This example will be described below with reference to FIG.

FIG. 5 is a partial circuit diagram showing a characteristic portion of one embodiment of the second associative memory of the present invention. In FIG. 5, the lower side of the figure is the upper address side, and the upper side of the figure is the lower address side. A major difference from FIG. 3 in comparison with the circuit shown in FIG. 3 is that the attribute bit cell group 20 of FIG. 3 is a search address range setting circuit in FIG. The mechanism of setting the address range for this search will be described.

First, it is assumed that the decoder 17a connected to the search address range setting circuit 40a is selected by the lowest address of a certain search range, and the word line 18a extending from the decoder 17a becomes "1". At this time, when a positive pulse is input to the lowest address setting control line 46, the pulse causes "1" data of the word line 18a to be input to the lower address flip-flop 43a. at the same time,
Since all the word lines 18 of the other decoder 17 are “0”, this value of “0” is input to the lower address flip-flop 43 of the other search address range setting circuit 40.

However, the search address range setting circuit 40a
The output of the lower address flip-flop 43a is received by the OR circuit 44a, and the output of the OR circuit 44a is the other lower side (the upper side in FIG. 5 is the lower side) input to the OR circuit 44a. ) Outputs "1" regardless of the input "0" from the search address range setting circuit 40. As a result, the transistor TCA2 forming one of the serial connection transistors of the NAND type match detection circuit 30 is turned on. The output of the OR circuit 44a is also input to the OR circuit 44b of the next stage (upper side), and the transistor TCA2 of the next stage is also turned on. Similarly, all the upper transistors TCA2 thereafter are turned on.

Next, it is assumed that the decoder 17b connected to the search address range setting circuit 40b is selected by inputting the highest address of the search. Also in this case, similarly, by applying a positive pulse to the highest address setting control line 45, "1" of the word line 18b is set in the upper address flip-flop 41b, which is the NAND type via the OR circuit 42b. One serial transistor TCA1 forming the match detection circuit 30 is turned on.

Similarly, although the upper address flip-flops 41 of the other search address range setting circuits 40 are all set to "0", the output of the OR circuit 42b lowers them (upper in FIG. 5). The transistors TCA1 of all addresses in the direction) are turned on. That is, in this example, among the serial transistors of the NAND-type coincidence detection circuit 30, the transistors in which both the transistor TCA1 and the transistor TCA2 are turned on are set between the lowest and highest positions of the address range. If the addresses 201 and 300 are now selected, the data of attribute 1 between them will be the search target.

After setting the search address range in this way, the NAND type match detection circuit 30 is precharged as described above, and the reference data is applied to the bit line and the bit bar line of each memory cell to perform the search. As a result, it is possible to perform a search only within the address range to be searched, that is, a content search in which an attribute is designated. By adopting this method, unlike the above-mentioned embodiment, even if the number of attributes of each data set increases, it is not necessary to increase the attribute bit width, and only the setting of the address range needs to be changed. It is possible to add more flexibility to the dataset.

FIG. 6 is a block diagram showing an embodiment of the third associative memory of the present invention. The same components as those of the associative memory shown in FIG. 17 are designated by the same reference numerals as those shown in FIG. 17, and only different points will be described. Each memory word 11_1, 11_2, ... Includes an attribute storage unit 11_1_1, 11_2_1 ,.
And data storage units 11_1_2 and 11_ for storing data
2_2, ... And each memory word 11_
Stored data consisting of pairs of attributes and data corresponding to each other are stored in 1, 11_2 ,.
Here, as shown, each memory word 11_1,1
1_2, 11_3, and 11_4 have attributes 0,
Data'A ', attribute 1, data'B', attribute 2, data'C ', attribute 3, data'D' are stored. Further, in each of the memory words 11_5, 11_6, ..., Attribute 0, data'C ', attribute 1, data'F' ,.
... is stored. Further, in the search, reference data REF_DATA including a pair of attribute and data is input.

In each of the memory words 11_1 and 11_2,
Stored data (both attributes and data) stored there
, In addition to the conventional match lines 14_1, 14_2, ..., which output a match signal when they match the input reference data (both attribute and data), output a match / mismatch signal for only the attribute. Attribute matching lines 30_1, 30_2, ...
Is provided. It should be noted that the matching of only the attributes and the matching of both the attributes and the data are configured in the same manner as the conventional match detection circuit, and the conventional match detection circuit is an extremely common technique in the field of the associative memory. Are not shown and described.

Third flag registers 31_1, 31_2, ... Are provided corresponding to the respective memory words 11_1, 11_2, and the respective attribute match lines 30_1, 30_2, ... Are corresponding third flag registers 31_1, 31_2 ,. …
To the data input terminal of. The associative memory of this embodiment is provided with one data line 32_1, 32_2, ... For each memory word group consisting of memory words in which each data belonging to each data set is stored. 32_1, 32_2, ... and the first switches 33_1, 33_2, ... between the output terminals of the respective second flag registers 31_1, 31_2 ,.
Is provided. These first switches 33_1,
33_2, ... Are specifically configured using transistors or the like. The same applies to other switches described below.
Each of the first switches 33_1, 33_2, ... Is turned on when the corresponding third flag register 33_1, 33_2, ... Is latching the signal of logic “1” and latches the signal of logic “0”. If it is, it will be shut off.
Each of the third flag registers 31_1, 31_2, ... At the timing of the trailing edge b of the match result latch signal S1 of the match result latch control line 25, the corresponding attribute match line 30_.
Latch signals 1, 30_2, ...

Further, the second switches 34_1, 34_2, ... Are provided between the data lines 32_1, 32_2, ... And the input terminals of the OR gates 21_1, 21_2 ,. 34_2, ...
Are controlled by the signals of the corresponding attribute match lines 30_1, 30_2, ... To be in a conductive state when the signal is a logic "1" indicating a match, and to be in a cutoff state when the signal is a logic "0" indicating a mismatch. . Unlike the associative memory shown in FIG. 17, the associative memory shown in FIG. 6 has an AND gate 20_1 corresponding to the uppermost memory word 11_1 in the figure.
The OR gate 21_1 is also provided in the preceding stage.

In the associative memory configured as described above, the matching search is performed as follows. The search for single data for one word and the first search are shown in Fig. 1.
Since it is the same as the case of the conventional associative memory with word expansion function shown in FIG. 7, its explanation is omitted here, and here, in the first search, the reference word REF_DATA consisting of the attribute 1 and the data'B 'is used for the memory word. 11_2
Corresponding to the first and second flag registers 23_2,
It is assumed that the logic '1' is latched in 24_2. At this time, in response to the attribute match, a signal of logic “1” is output to the attribute match line 30_2 corresponding to the memory word 11_2, whereby the corresponding third flag register 31_
2 also latches the signal of logic “1”, the corresponding first switch 33_2 is turned on, and the logic “1” of both the attribute and the data stored in the corresponding second flag register 24_2 is stored. The signal is output to the data line 32_1. Along with this, the corresponding second switch 34
_2 is also turned on, but this is an unnecessary operation in the first search.

Next, it is assumed that the reference data REF_DATA consisting of the attribute 3 and the data'D 'is input to perform the search. At this time, as in the case of the associative memory of FIG. 17, the initial search control line 22 is held at logic '0'. At this time, in response to the attribute match, a signal of logic “1” is output to the attribute match line 30_4 corresponding to the memory word 11_4, whereby the corresponding second switch 34_4 is turned on and is output to the data line 32_1. Further, the signal of logic "1" of the second flag register 24_2 corresponding to the memory word 11_2 is input to the AND gate 20_4 via the OR gate 21_4. Therefore, when a match between the attribute 3 and the data “D” is detected in the memory word 11_4 and a match signal of logic “1” is output to the match line 14_4, the match result latch signal of the match result latch control line 25 is output. By S1, the signal of logic '1' is latched in the corresponding first and second flag registers 23_4, 24_4 at the rising and falling edges of the latch signal S1, respectively. Further, at this time, the signal of logic “1” output to the attribute matching line 30_4 is latched in the corresponding third flag register 31_4 at the falling edge of the latch signal, and the corresponding first switch 33_4 is turned on, The signal of logic “1” of the second flag register 24_4 is output to the data line 32_1. Further, in the second search, since the logic “0” indicating the attribute mismatch is output to the attribute matching line 30_2 corresponding to the memory word 11_2, “0” is stored in the corresponding third flag register 31_2. , The first switch 3 corresponding to memory word 11_2
3_2 turns off at the timing of the fall of the latch signal S1. However, the second search result is already the first
Stored in the flag register 23_1.

Regarding the encoding of the hit address, the signal of logic "1" of the second flag register 24_4 corresponding to the memory word 11_4 is input to the priority encoder 16 (see FIG. 14), and the address of the memory word 11_4 is changed. Although it will be obtained, it is known in advance that the attribute 3 is stored in the memory word 11_4, and when it is desired to read, for example, the data of the attribute 2 in the same group, subtract 1 from the obtained address. It suffices to obtain the address of the memory word 11_3, input the address to the address decoder 17, and read the contents of the memory word 11_3.

In the second search, when the reference data including the attribute 3 and the data “B” is searched instead of the reference data including the attribute 3 and the data “D”, the memory word 11_4. 2), since the attributes match, the second switch 34_4 is turned on and the data line 32_
The signal of logic "1" output to 1 is taken in, but since the data is different, the logic "0" indicating mismatch is output to the match line 14_4, and the first and second flag registers 23_4 and 24_4 are output. A logic '0' is latched indicating that no match was found. In addition, the attribute does not match for the memory word 11_2 with which the data'B 'matches, and therefore both the attribute and the data do not match.

As described above, in the embodiment shown in FIG. 6, in the same group, even if the data are stored in memory words separated from each other, or the order of the stored data is irrelevant. Even, a search can be done. Here, the data line 32_ in the above embodiment
, 32_2, ... have fixed lengths, assuming that the number of data belonging to one group is predetermined, but if such fixed length data lines are provided, 1
It is necessary to estimate the maximum number of data belonging to one group and provide a data line with a length corresponding to the maximum number of data.
In this case, useless memory words are generated when a data group is composed of a smaller number of data than the maximum. Therefore, it is preferable to make the data line variable length according to the number of data belonging to one group, but there is a problem how to make the data line length variable.

FIG. 7 is a schematic diagram showing one method for realizing a variable length data line. A data line 32 extends over a plurality of memory words 11_1, 11_2, 11_3, ...
Other memory words 11_2, 11_3, except 1_1, ...
Each switch 40_1, 40_2, 4 corresponding to each
0_3, ... Are arranged in series with each other. Each of these switches 40_2, 40_3, 40_4, ... Corresponds to the corresponding memory word 11_2, 11_3, 11_4 ,.
And the memory words 11_1 and 1 immediately adjacent to the upper row.
It is arranged between 1_2, 11_3, .... Every other switch 40_2, 40_3, 40_4, ... Of these switches 40_2, 40_4, 40_6 ,.
Are turned on by the first switch control signal of the first control line 41, and every third switch 40_3, 40_7, ...
The control signal is turned on by the second switch control signal on the control line 42, and every other eight switches 40_5, ... Of the remaining switches are turned on by the third switch control signal on the third control line 43.

The number of pieces of data constituting one data group is 2
In this case, by outputting the first switch control signal to the first control line 41, every other switch 40_2, 40
Turn on _4, 40_6, .... As a result, each two memory words 11_1, 11_2; 11_3, 11_
4; 11_5, 11_6; ... The data lines cut off are formed. Further, when the number of data forming one data group is four, the first switch control signal is output to the first control line 41 and the second switch control signal is output to the second control line 42. Then, each of the four memory words 11_1, 11_2, 11_3, 11_4; 11_5
A disconnected data line is formed every 11_6 .... Similarly, when the number of pieces of data forming one data group is 8, while outputting the first and second switch control signals to the first control line 41 and the second control line 42, respectively,
The third switch control signal is output to the third control line 43.
As a result, each of the eight memory words 11_1, ..., 11_
8; 11_9 ... A disconnected data line is formed.

According to this method, when the number of data constituting one data group is a multiple of 2, no vacancy occurs in the memory word, but in the case of a number other than a multiple of 2, such as 3, 5, 9 or the like. There will be free memory words. If a large number of switches 40_2, 40_3, ... Can be arbitrarily turned on and off so as not to generate this empty memory word, the number of control lines becomes large, and a switch control signal is output to those control lines. The control circuit to operate becomes complicated. Therefore, the method shown in FIG. 7 is not suitable for arbitrarily controlling the length of the data line.

FIG. 8 is a schematic diagram showing another method for realizing a variable data line. A data line 32 extends over a large number of memory words, and each switch 40_ corresponding to each of the other memory words except the uppermost memory word connected in series to the data line 32.
FIG. 7 shows that 2, 40_3, 40_4, ... Are provided.
Is the same as in. Each memory word is provided with each attribute storage unit 11_1_1, 11_2_1, 11_3_1, ..., And these attribute storage units 11_1_1, 11_
2_1, 11_3_1, ... Indicate the respective attributes 0, 1,
2 and 3 are stored respectively. In this example, depending on whether the attribute stored in the attribute storage unit 11_1_1, 11_2_1, 11_3_1, ... Is attribute 0 or the other attributes 1, 2, and 3, when the attribute is 0, the corresponding switch is kept off. For other attributes 1, 2, and 3, the corresponding switches are turned on. With this configuration, no matter how many pieces of data make up one data group, or even if data groups with different numbers of data are mixed, the data of attribute 0 is placed at the beginning of each data group. By doing so, a data line is automatically formed for each memory word of a sufficient number.

FIG. 9 is a circuit diagram showing an example of an attribute judging circuit for judging whether the attribute is "0" or not. Here, "000" is assigned to the attribute 0, and the attribute stored in the attribute storage unit 11_i_1 is the attribute 0 ('000').
In this case, "0" is output from the OR gate, so that the switch 40 'composed of the transistor 40 is turned off, and the data lines on both sides of the transistor 40' are electrically disconnected. When the attribute stored in the attribute storage unit 11_i_1 is an attribute other than the attribute I, "1" is output from the OR gate, the transistor 40 is turned on, and the data lines on both sides of the transistor are connected.

Thus, in the embodiment shown in FIG.
It is also possible to adjust the lengths of the data lines 32_1, 32_2, ... According to the number of pieces of data forming one data group. Needless to say, the length of the data line may be adjusted by controlling the switch with a dedicated control line or a new attribute bit instead of using the attribute data.

FIG. 10 is a functional block diagram of an embodiment of the fourth associative memory of the present invention, and FIG. 11 is a functional block showing a control data designating method in the fourth associative memory of the present invention. It is a figure. Both the segment data corresponding to the above-mentioned attribute data and normal data are stored in each of a large number of memory words forming this associative memory. Further, this associative memory is provided with N segment registers which are an example of the search auxiliary data register according to the present invention, and N mask registers which are another example of the search auxiliary data register according to the present invention. It is equipped.

Any of these segment registers,
Alternatively, when writing segment data or mask data to any of the mask registers, the data A to be written is input and the function data FUN is input.
By specifying the register to be written with _DATA (see FIG. 15) and further inputting the WRITE signal, the desired data A is written in the desired register.

Further, this associative memory is provided with a plurality of channels (control data register group referred to in the present invention) including a plurality of control data registers each storing control data. The control data stored in each control data register is for designating one of the segment registers and one of the mask registers at the time of search.

When each control data is written in each control data register, the data A to be written is input, the channel to be written is designated, and the WRITE signal is input. Then, the data A becomes the control data
It is stored in the lowest-numbered control data register of the free control data registers of the specified channel.
For example, after initialization, when channel 1 is designated for the first time, control data is stored in the control data register (1) of channel 1, and when channel 1 is designated for the second time, channel 1 ( The control data is stored in the control data register of 2). On the other hand, in the search, as shown in FIG. 11, the address data indicating the channel 1 is input, and the desired data A is input as the first reference data in synchronization with the WRITE signal instructing the search. At this time, assuming that each channel is reset by the reset signal, (1) of this channel 1 designated by the address
The control data stored in the control data register of No. 1 designates, for example, the segment register # 2 of the N segment registers and also designates, for example, the mask register # 3 of the N mask registers. If it is, the input data A is masked by the mask register stored in the mask register # 3, and the generated data and the segment data stored in the segment register # 2 are both masked. The reference data and the stored data stored in each memory word are compared and compared.

Next, as the address data, the same address data as the previous time (address data specifying channel 1)
When a new data B is input as reference data and a search is instructed together with this, the control data stored in the control data register (2) of channel 1 causes the N segment registers to be selected. , And one of the N mask registers are designated.
For example, when the control data stored in the control data register (2) of channel 1 specifies the segment register # 1 and the mask register # 1, the mask stored in the mask register # 1 for the input data B The data is masked and the reference data consisting of both the data generated thereby and the segment data stored in the segment register # 1 is compared with the stored data stored in each memory word. .

As described above, FIG. 10 and FIG.
In the associative memory shown in 1, control data for specifying a segment register and a mask register for each channel, or
By storing a plurality of segment data and mask data directly, that is, by storing each search mode in each channel and specifying a channel for search, the search mode stored in the specified channel is followed. The search is done. In the associative memory shown in FIG. 10 and FIG. 11, it is not necessary to input segment data or mask data from outside every search, and the search mode (search channel) is used.
A series of searches can be performed a plurality of times simply by sequentially inputting the address data and the reference data indicating the search, the search procedure is simplified, and the series of searches is performed at high speed.

That is, regarding the retrieval of the data forming the group structure, the retrieval data is stored by using the associative memory as in the present invention, and the retrieval auxiliary data is stored in advance in the order of use for a plurality of consecutive retrievals. By having a programmable sequence register for outputting, search auxiliary data is automatically sequentially selected by sequentially inputting only reference data from the outside. In the present embodiment, the tenth and eleventh methods of configuring the sequence register are described.
This is described with reference to FIG. 13 and FIG. 13 (described later).

In the associative memory shown in FIGS. 10 and 11, m search modes can be stored at the same time, and the search modes can be rewritten, so that an associative memory having a large degree of freedom can be obtained. To be realized. FIG. 12 is a diagram showing an example of a data structure of data handled by the associative memory shown in FIGS. 10 and 11.

It is assumed that, for example, m-bit parallel data as shown in the drawing is sequentially input in the arrow direction. The series of data sets is referred to as a data packet here. At the beginning of each data packet, a protocol indicating the procedure of data communication and the like is arranged, and in this associative memory, data retrieval is performed for the protocol portion. When the data retrieval of the protocol portion of a certain data packet is completed, the channel used for the data retrieval (eg, channel 1; FIG. 10,
(See FIG. 11) shows that the last control data register that makes up channel 1 is in the specified state, and therefore the first control data that makes up channel 1 before the next search using that channel 1 The registers need to be reset as specified. However, in the case of handling the data as shown in FIG. 12, if the protocol portion of a certain data packet is automatically reset when the retrieval is completed, the retrieval operation is performed up to the portion of the data packet following the protocol. It will be. Therefore, as shown in FIG. 11, the reset signal is inputted from the outside, and the inconvenience as described above can be avoided by resetting the data packet at the end time or the input start time of the next data packet.

In the above embodiment, both the segment register and the mask register are designated by the control data, but only the segment register may be designated, or only the mask register is designated. May be designated, and as the search auxiliary data register according to the present invention, a register for storing search auxiliary data other than the segment data and the mask data for assisting the search may be provided. .

FIG. 13 shows the fifth associative memory of the present invention.
FIG. 12 is a functional block diagram of a portion corresponding to FIG. 11, showing a difference from the fourth associative memory shown in FIGS. 10 and 11. The associative memory shown in FIG. 13 is provided with a designated data register that stores channel designation data for designating any one of a plurality of channels.

Therefore, in searching, it is sufficient to store the channel specifying data in the specifying data register once, and thereafter, a series of searching can be performed by only sequentially inputting the reference data, as shown in FIGS. 10 and 11. The procedure for searching is further simplified than the associative memory. It goes without saying that the channel may be designated by a dedicated control terminal or a combination thereof instead of using a register or an address.

The search simplifying means using these programmable sequencers plays an extremely important role in performing flexible and high-speed search of group data according to the present invention.

[0087]

As described above, according to the present invention,
It is possible to efficiently store and retrieve group structure data.

[Brief description of drawings]

FIG. 1 is a memory structure diagram of an embodiment of the present invention.

FIG. 2 is a block diagram of an associative memory.

FIG. 3 is a circuit diagram showing the configuration of one memory word in one embodiment of the first associative memory of the present invention.

FIG. 4 is a memory structure diagram of a second associative memory of the present invention.

FIG. 5 is a partial circuit diagram showing a characteristic part of an embodiment of a second associative memory of the present invention.

FIG. 6 is a block diagram showing an embodiment of a third associative memory of the present invention.

FIG. 7 is a schematic diagram showing one method for realizing a variable-length data line.

FIG. 8 is a schematic diagram showing another method for realizing variable data lines.

FIG. 9 is a circuit diagram of an example of an attribute determination circuit that determines whether an attribute is 0 or not.

FIG. 10 is a functional block diagram of an embodiment of an associative memory of the fourth present invention.

FIG. 11 is a functional block diagram showing a method of specifying control data at the time of search in the fourth associative memory of the present invention.

FIG. 12 is a diagram showing an example of a data structure of data handled in an associative memory.

FIG. 13 is a diagram showing a difference between the fifth associative memory of the present invention and the fourth associative memory shown in FIGS. 10 and 11, and FIG.
2 is a functional block diagram of a portion corresponding to 1. FIG.

FIG. 14 is a circuit block diagram showing an example of a conventional associative memory.

FIG. 15 is a functional block diagram of a conventional associative memory.

FIG. 16 is a diagram showing an array of data with attributes stored in an associative memory.

FIG. 17 is a block diagram showing an example of an associative memory having a data expansion function.

[Explanation of symbols]

10 associative memory 11_1, 11_2, ..., 11_n Memory word 11_1_1, 11_2_1, ... Attribute storage section 11_1_2, 11_2_2, ... Data storage section 12 Reference data register 13 Mask data register 14_1, 14_2, ... Matching line 15_1, 15_2, ..., 15_n Match flag register 16 Priority encoder 17, 17a, 17b, 17_1, 17_2, ... Address decoder 18_1, 18_2, ... Word line 19 Output data register 20_1, 20_2, ... AND gate 21_1, 21_2, ... OR gate 23_1, 23_2, ... 1st Flag register 24_1, 24_2, ... First flag register 25 Match result latch control line 30 Match detection circuit 30_1, 30_2, ... Attribute match line 31 Match detection un 31_1, 31_2, ... Third flag register 32_1, 32_2, ... Data line 33_1, 33_2, ... First switch 34_1, 34_2, ... Second switch 40, 40a, 40b Search address range setting circuit 120 Attribute bit cell group

 ─────────────────────────────────────────────────── ─── Continuation of the front page (31) Priority claim number Japanese Patent Application No. 6-54140 (32) Priority date Hei 6 (1994) March 24 (33) Priority claim country Japan (JP)

Claims (12)

[Claims] 1. A bit pattern in which digital data is stored in each of a plurality of arranged memory words, reference data is input, and all or a predetermined part of the input reference data matches a bit pattern. In a method of using an associative memory for retrieving a memory word in which digital data having is stored, the associative memory stores digital data in one of the first areas into which each memory word is divided, Attribute data representing an attribute of the digital data is stored in a second area of the word excluding the first area, and a set of predetermined attribute data and predetermined digital data is input to the associative memory as the reference data. By doing so, corresponding to the input predetermined digital data to the associative memory and input Using associative memory, wherein a digital data having a predetermined attribute data represents attributes that causes the search of the stored memory word. 2. A bit pattern in which digital data is stored in each of a plurality of arranged memory words, reference data is input, and all or a predetermined part of the input reference data matches a bit pattern. In an associative memory for searching a memory word in which digital data having is stored, each memory word represents a first area for storing each digital data and an attribute of the digital data stored in the first area. An associative memory, wherein the attribute data has a bit pattern which is cyclically repeated in a cycle according to the number of attributes in the address order of each memory word. 3. Attribute data having a bit pattern in which each memory word cyclically repeats at a cycle corresponding to the number of attributes in the address order of each memory word, and each second area forming each memory word. The associative memory according to claim 2, wherein the associative memory is fixedly stored in. 4. A bit pattern in which digital data is stored in each of a plurality of arranged memory words, reference data is input, and all or a predetermined part of the input reference data matches a bit pattern. In an associative memory that searches for a memory word in which digital data having is stored, is selected as a target for comparison with the input reference data in the entire range of addresses assigned to each of the plurality of arranged memory words. An associative memory having a search address range setting circuit for setting an address range of a memory word. 5. A plurality of memory words storing a plurality of stored data belonging to each of a plurality of data groups for each stored data, and a match between the stored data stored in a predetermined memory word and input reference data When detected, the first mode in which a match signal indicating a match is output to the match line corresponding to the predetermined memory word, and the match is detected in the predetermined memory word during the current search, and At the time of search, when a match is detected in any memory word that stores each of the stored data that constitutes the data group to which the stored data stored in the predetermined memory word belongs, a match that corresponds to the predetermined memory word An associative memory comprising a match detection circuit having a second mode for outputting a match signal to a line. 6. A plurality of memory words, each storing a plurality of stored data belonging to each of a plurality of data groups each consisting of a plurality of stored data sets each consisting of a pair of attribute and data, said plurality of memory words Attribute match detection circuit for detecting a match / mismatch between the attribute in the stored data stored corresponding to each of the memory words and the attribute in the input reference data consisting of a pair of the attribute and the data, Detects a match / mismatch between the data in the stored data consisting of a pair of attribute and data stored corresponding to each memory word and the input data in the reference data consisting of a pair of attribute and data. A data coincidence detection circuit, which stores information on coincidence / non-coincidence between the stored data and the reference data, which is provided corresponding to each of the plurality of memory words. A register, a data line provided for each memory word group consisting of memory words that respectively store the respective stored data forming the same data group, a corresponding attribute provided for each of the plurality of memory words A first switch circuit, which transmits a matching or mismatching search result of the corresponding register to the data line in response to a match of an attribute being detected by the match detection circuit, corresponding to each of the plurality of memory words Information corresponding to both the attribute and the data is detected by the corresponding attribute match detection circuit and the data match detection circuit, which are provided in the same time, and information indicating the match in the previous search on the data line. Is output, the information indicating the match in this search is transmitted to the corresponding register. The circuit and the corresponding attribute match detection circuit provided corresponding to each of the plurality of memory words detect that the attribute match is detected at the time of the current search, and the previous output to the data line is performed. An associative memory comprising a second switch circuit for transmitting information indicating a match or a mismatch at the time of detection to the corresponding gate circuit. 7. An attribute discriminating circuit provided for each of the plurality of memory words and discriminating whether or not the attribute in the stored data stored in the corresponding memory word is a predetermined attribute. And the data lines are connected in series between the memory words adjacent to each other across the plurality of memory word groups via a third switch circuit provided corresponding to each of the plurality of memory words. The associative memory according to claim 6, further comprising: 8. The associative memory according to claim 7, wherein the third switch circuit is controlled by the attribute determination circuit or a data line connection control circuit provided for each memory word. 9. A reference in which each stored data is stored in each of a plurality of memory words, a plurality of reference data are sequentially input, and the reference data is compared with each stored data by combining with the sequentially input reference data. An associative memory comprising search auxiliary data sequential output means for sequentially outputting each search auxiliary data for generating data, and searching a memory word in which predetermined stored data is stored. 10. The search auxiliary data sequential output unit has a search auxiliary data register group for storing a series of search auxiliary data, and a control unit for instructing and controlling the search auxiliary data register, and the control unit includes: An address is defined, address data representing the address is input together with the reference data, and the search is performed by the control means specified by the address data based on the address data input together with the reference data and the number of searches. 10. The associative memory according to claim 9, wherein the auxiliary data is sequentially output. 11. The search auxiliary data sequential output means includes a search auxiliary data register group for storing a series of search auxiliary data, a control means for instructing and controlling the search auxiliary data register group, and a channel for designating the control means. And a designated data register, and sequentially outputs the search auxiliary data based on the control means designated by the channel designated data register stored in the designated register and the number of times of the search by inputting reference data. The associative memory according to claim 9, wherein: 12. The associative memory according to claim 9, further comprising a reset terminal for inputting a sequence reset signal for initializing an output order of the search auxiliary data of the search auxiliary data sequential output means.