JPH07287718A - Associative memory - Google Patents

Abstract

PURPOSE:To activate only a necessary part and to reduce power consumption by providing this associative memory with a bit line driving circuit for driving a bit line in a prescribed memory block at the time of executing current retrieval in accordance with the state of a coincidence flag stored in a flag register at the time of preceding retrieval. CONSTITUTION:Many memory words are divided into plural memory blocks 51-1 to 51-N. At the time of 2nd retrieval or after, a control signal of logic '0' is impressed to a control line 54B. Thereby only when coincidence is detected in any one of memory words in the block 51-i at the preceding retrieval, retrieving data inputted through a retrieving data line 53 at the time of current retrieval are impressed to bit lines 56-i-1, 56-i-2. When no coincidence is detected in any memory word in the memory block 51-i at the preceding retrieval, an intra-block coincidence line 55-i is held at logic '0' and power consumption is suppressed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention has a function of expanding the data width of a match search to a plurality of words, that is, when a match is detected in a plurality of consecutive searches, a match is detected as a whole. The present invention relates to an associative memory having a function to be performed.

[0002]

2. Description of the Related Art Conventionally, digital data is stored in each of a plurality of arranged memory words, search data is input, and all or a predetermined part of the input search data is matched with a bit pattern. Associative memory for searching a memory word in which digital data having a bit pattern to be stored is searched.
memory, content addressable memory; Content A
(Addressable Memory) has been proposed.

FIG. 1 is a circuit block diagram showing an example of an associative memory.

The associative memory 10 has a large number of memory words 11_1, 11_2, each of which has m bits as one word and is composed of m-bit memory cells arranged in the lateral direction of the drawing.
..., 11_n are provided. Also, this associative memory 1
0 is provided with a search data register 12 into which search data of 1 word is input and latched.
All or a predetermined part of the bit pattern of the search data latched in the memory words 11_1 and 11_
Of the stored data stored in 2, ..., 11_n, the match / mismatch of the bit pattern of the portion corresponding to the above bit pattern is compared, and each memory word 11_1, 11_ is compared.
, ..., 11_n provided in correspondence with the match lines 14_1, 14_2, ..., 14_n, the memory words 11_1, 11_2, the bit patterns of which match.
…, Matching lines 14_1, 14_2 corresponding to 11_n
.., 14_n, a coincidence signal of logic '1' (5 V here) is output. Other match lines 14_1, 14
_2, ..., 14_n stays at logic '0' (here, 0 V).

These matching lines 14_1, 14_2, ...,
The signal output to 14_n is the flag register 15_
1, 15_2, ..., 15_n. here,
As an example, each flag register 15_
1, 15_2, ..., 15_n are respectively “0”,
It is assumed that "1", "1", "0", ..., "0", "0" are stored. These flag registers 15_1, 1
The signals stored in 5_2, ..., 15_n are input to the priority encoder 16. The encode pulse EP is input to the priority encoder 16, and each time the encode pulse EP is input, a flag register (here, flag register 15_2 and flag The address signal AD corresponding to the flag register having the higher priority of the two registers 15_3) is sequentially output. Here, the younger the subscript, the higher the priority. Therefore, when only one encode pulse EP is input, the memory address corresponding to the flag register 15_2 is output. The address signal AD output from the priority encoder 16 is input to the address decoder 17 as needed. The address decoder 17 decodes the input address signal AD, and word lines 18_1, 18_2, ..., 1 provided corresponding to the memory words 11_1, 11_2, ..., 11_n, respectively.
Any one of the word lines 8_n corresponding to the input address signal AD (here, the word line 18_n
An access signal (here, a signal of logic "1") is output to 2). As a result, the storage data stored in the memory word 11_2 corresponding to the word line 18_2 to which the access signal is output is read to the output register 19.

Next, when another encode pulse EP is input, the address of the memory word 11_3 corresponding to the flag register 15_3 can be obtained this time.

As described above, the associative memory 10 searches the stored data stored in a large number of memory words 11_1, 11_2, ..., 11_n by using all or a predetermined part of the search data and matches them. The memory is configured so that the address of the memory word having the stored data to be obtained can be obtained, and the entire data stored in the memory word can be read out if necessary.

In the associative memory having the basic structure as described above, there has been proposed a technique for expanding the data width to be a match search target to a plurality of words of two words or more.

FIG. 2 is a block diagram showing an example of an associative memory having a data expansion function. The components corresponding to the components of the associative memory shown in FIG. 1 are designated by the same reference numerals as those shown in FIG. 1, and duplicate description of those components will be omitted.

The match lines 14_1, 14_2, ... Extending from the memory words 11_1, 11_2, ... Are connected to one input terminal of each AND gate 20_1, 20_2 ,. In addition, each AND gate 20_1, 20_
The other input terminals of 2, ...
The output terminals of 21_3, ... Are connected, and one input terminal of each OR gate 21_2, 21_3, ... Is connected to the initial search control line 22. However, the OR gate corresponding to the uppermost AND gate 20_1 in the figure is omitted, and the initial search control line 22 is directly connected to the input terminal of the AND gate 20_1.

The output terminals of the AND gates 20_1, 20_2, ... Are connected to the first flag registers 23_1, 23_, respectively.
, ..., and the output terminals of the first flag registers 23_1, 23_2, ... Are connected to the input terminals of the second flag registers 24_1, 24_2 ,. Each second flag register 24_1, 24
The output terminals of _2, ... Are connected to the priority encoder 16 (not shown in FIG. 2) shown in FIG.
2 are connected to the input terminals of the OR gates 21_2, 21_3, ... Corresponding to the memory words adjacent to the lower part of FIG.

Each pair of first and second flag registers 23_1, 24_1, 23_2, 24_2, ... Corresponding to each other corresponds to each flag register 15_1, 15 shown in FIG.
Corresponds to _2, ...

First flag registers 23_1 and 23_
2, ... and the second flag registers 24_1, 24_2 ,.
, The match result latch signal S1 output to the match result latch control line 25 is input, and the input data input from each data input terminal is latched by the match result latch signal S1. Flag register 23_
1, 23_2, ... Latches the input data at the time of the rising edge a of the match result latch signal S1,
The input data at the time of the falling edge b of the match result latch signal S1 is latched in the flag registers 24_1, 24_2 ,.

In the associative memory configured as described above, a match search is performed as follows. Here, as shown in the drawing, each memory word 11_1, 11_
2, 11_3, 11_4, 11_5, 11_6 ...
It is assumed that the stored data A, B, C, D, C, F, ... Are stored.

Here, when individually searching each stored data, when the search data REF_DATA is input to perform the search, the first search timing signal S is applied to the first search control line 22.
2 is output. Here, the search data REF_DATA
Assuming that the data “B” is input as, the match signal of logic “1” is output to the match line 14_2 corresponding to the memory word 11_2 in which the data “B” is stored and is input to the AND gate 20_2, and At the same time, the first search timing signal S2 is input to the AND gate 20_2 via the OR gate 21_2.
A signal of logic “1” is output from 0_2. Further, at this time, since the logic "0" signal is output to the other match lines 14_1; 14_3, 14_4, ..., The logic "0" is output from the other AND gates 20_1; 20_3, 20_4 ,. Signal is output.

The signal of logic '1' output from the AND gate 20_2 is latched in the first flag register 23_2 at the rising edge a of the match result latch signal S1 output to the match result latch control line 25. It is latched in the second flag register 24_2 at the timing of the subsequent falling edge b of the match result latch signal S1.

Further, at each timing when the signal of logic "1" is latched in the first flag register 23_2 and the second flag register 24_2, another first flag register 23 is provided.
.. and 23_3, 23_4, ..., and other second flag registers 24_1; 24_3, 24_4 ,.

In this way, each second flag register 2
The signals of logic "0", "1", "0", ... Latched by 4_1, 24_2, 24_3, ... Are input to the priority encoder 16 shown in FIG.
An address signal AD of 1_2 is obtained.

Next, a case where a search with an expanded data width is performed will be described. Here, a case will be described where 2-word data consisting of data “B” and data “C” expanded to 2 words is searched.

In this case, first, the data'B 'is searched in the same manner as described above. This causes memory word 11_
2 corresponding to the first and second flag registers 23_2,
At 24_2, the signal of logic "1" is latched. Next, data “C” is input as the search data REF_DATA to perform a search, but at this time, the initial search control line 22 does not output the initial search timing signal S2, and the initial search control line 22 has a logic “0”. Keep the condition. Search data R
When data “C” is input as EF_DATA and a search is performed, a match signal of logic “1” is output to the match lines 14_3 and 14_5 corresponding to the two memory words 11_3 and 11_5 illustrated, respectively.
Since the signal of logic “1” latched in the second flag register 24_2 is input to the
The match signal of _3 passes through the AND gate 20_3 and
A signal of logic "1" indicating a match is latched in the second flag registers 23_3 and 24_3. On the other hand, since the signal of logic “0” latched by the second flag register 24_4 is input to the OR gate 21_5, the match signal of the match line 14_5 is the AND gate 20_5.
Is blocked by the first and second flag registers 23_5,
In 24_5, a signal of logic "0" indicating a mismatch will be latched. In this way, coincidence detection of 2-word data composed of a pair of data “B” and data “C” is performed. Matching detection of data of 3 words or more is similarly performed.

However, although the associative memory shown in FIG. 2 has a data width expanding function, the data expanded to 2 words, 3 words, etc. is stored in adjacent memory words in a predetermined order. If a plurality of data to be searched are stored in memory words separated from each other, or in the reverse order, for example, in the order of data'C 'and data'B', , It is not possible to perform coincidence detection by combining multiple data.

FIG. 3 shows an example of the data structure when such a search is required. In FIG. 3, attributes I,
A data structure is shown in which four pieces of data labeled II, III, and IV constitute a single data group as a set. For example, in order to clarify the concept of the data group and the attribute, for example, each data group for each group number 1, 2, 3, 4, ... Is data belonging to each individual, and the attribute I
Is the name of the person, attribute II is the date of birth of the person, attribute I
II indicates an address, ...

In this way, each attribute I, II, III, IV
In the case of storing a data group consisting of a plurality of data to which data is attached in the associative memory and performing a search, for example, a case of searching a data group with a group number of 1 will be described. Search for data'B 'in this order,
Not only the remaining data'C 'and'D' of the matching data group are read out, but the remaining data'B 'and'C' are searched by searching for the data'A 'and the data'D', for example.
There is a case where it is desired to read out the data or a case where the data “B” is searched first and then the data “A” is searched.

However, such a search is impossible in the associative memory (see FIG. 2) having the above-mentioned word width expansion function. Further, in the above-mentioned associative memory, the data'A '
And the data'B 'are searched, the data'A' and the attribute I with the attribute I in the column of the group number 1 shown in FIG. 3 are added.
Distinguish between a pair with data'B 'with I and a pair with data'A' with attribute II and data'B 'with attribute III in the column of group number 4. It is not possible, for example, based on the information of the attribute I of “name” and the attribute II of “date of birth”, even if the information of the attributes III and IV of a specific individual with which they match is known, the attribute II
A noise other than the necessary information will be mixed in, such as a match being detected even in the pair of and attribute III.

An associative memory that solves such a problem is
Proposed by the present applicant (Japanese Patent Application No. 5-2481)
21). Although this has not been published, the associative memory according to this proposal will be described below as a related technique.

FIG. 4 is a block diagram showing an example of the associative memory according to the above proposal. The same constituent elements as those of the associative memory shown in FIG. 2 are designated by the same reference numerals as those shown in FIG. 2, and only different points will be described.

Each memory word 11_1, 11_2, ...
Are attribute storage units 11_1_1 and 11_2 that store attributes.
, Data storage unit 11_1_ for storing data
2, 11_2_2, ..., Each of the memory words 11_1, 11_2, ... Stores stored data consisting of a pair of an attribute and data corresponding to each other. Here, as shown, each memory word 1
Numerals 1_1, 11_2, 11_3, 11_4 respectively belong to the group number 1 shown in FIG. 3 and are attribute I data'A ', attribute II data'B', attribute III data'C ', and attribute IV data. "D" is stored.
The memory words 11_5, 11_6, ... Store the data'C 'of the attribute I, the data'F' of the attribute II, ... Which belong to the group number 2 shown in FIG. Further, in the search, search data REF_DATA including a pair of attribute and data is input.

In each memory word 11_1 and 11_2,
Stored data (both attributes and data) stored there
Matches the input search data (both the attribute and the data), a match signal is output.
In addition to 1, 14_2, ..., Attribute matching lines 30_1, 30_2 ,. The circuit that detects the matching of only the attributes or the matching of both the attributes and the data is configured similarly to the conventional matching detection circuit. Since the conventional coincidence detection circuit is a very general technique in the field of associative memory, its illustration and description are omitted here.

Third flag registers 31_1, 31_2, ... Are provided corresponding to the respective memory words 11_1, 11_2, and the respective attribute match lines 30_1, 30_2 ,.
Is the corresponding third flag register 31_1, 31_
2, extending to the data input terminals. Further, in the associative memory, one data line 32_1, 32_2, ... Is provided for each memory word group consisting of a plurality of memory words storing data belonging to each data group shown in FIG.
And data lines 32_1, 32_2,
... and the output terminals of the second flag registers 24_1, 24_2, ... Between the first switches 33_1, 33, respectively.
_2, ... are provided. These first switches 3
3_1, 33_2, ... Are specifically configured using transistors or the like. The same applies to other switches described below. Each of the first switches 33_1, 33_2, ...
Is the corresponding third flag register 31_1, 31_
When the logic "1" signal is latched to 2, ..., It is conducted, and when the logic "0" signal is latched, it is cut off. Each third flag register 31_1, 31_
2, ... Latch the signals of the corresponding attribute match lines 30_1, 30_2, ... At the falling edge b of the match result latch signal S1 output to the match result latch control line 25.

Further, the second switches 34_1, 34_2, ... Are provided between the data lines 32_1, 32_2, ... And the input terminals of the OR gates 21_1, 21_2 ,. 34_1, 34_
2, ... Corresponding attribute matching lines 30_1, 30_2, ...
The signal is controlled so that the signal is in a conductive state when the signal is a logic "1" indicating a match and is in a cutoff state when the signal is a logic "0" indicating a mismatch. The associative memory shown in FIG. 4 is different from the associative memory shown in FIG. 2 in that an OR gate 21_1 is also provided before the AND gate 20_1 corresponding to the highest memory word 11_1 shown in the figure.

In the associative memory configured as described above, the matching search is performed as follows.

Since a single data search for one word and a first search among a plurality of continuous words are the same as those in the conventional associative memory with word expansion function shown in FIG. The description is omitted here. In the first search, the memory word 11 is searched by the search data REF_DATA including the attribute II and the data “B”.
_2 corresponding to the first and second flag registers 23_
It is assumed that the logic "1" is latched in 2, 24_2.
At this time, in response to the matching of the attributes, the memory word 11_2
A signal of logic "1" is output to the attribute matching line 30_2 corresponding to the third flag register 3
The signal of logic “1” is also latched in 1_2, the corresponding first switch 33_2 is turned on, and the logic “1” of both the attribute and the data stored in the corresponding second flag register 24_2 is stored. The signal is output to the data line 32_1. Along with this, the corresponding second switch 3
Although 4_2 is also turned on, it is an unnecessary operation in the first search.

Next, it is assumed that the search data REF_DATA consisting of the attribute IV and the data'D 'is input to perform the search. At this time, as in the case of the associative memory of FIG. 2, the initial search control line 22 is held at logic “0”. At this time, in response to the attribute match, a signal of logic “1” is output to the attribute match line 30_4 corresponding to the memory word 11_4, whereby the corresponding second switch 34_4 is turned on and is output to the data line 32_1. Further, the signal of logic "1" of the second flag register 24_2 corresponding to the memory word 11_2 is input to the AND gate 20_4 via the OR gate 21_4. Therefore, a match between the attribute IV and the data “D” is detected in the memory word 11_4, a match signal of logic “1” is output to the match line 14_4, and the match result latch is output to the match result latch control line 25. The signal S1 causes the corresponding first and second flag registers 23_4 and 24_4 to latch the signal of logic “1”. Further, at this time, the signal of logic “1” output to the attribute matching line 30_4 is latched in the corresponding third flag register 31_4, and the corresponding first switch 33.
_4 is turned on, and the signal of logic “1” of the second flag register 24_4 is output to the data line 32_1. Further, in the second search, the logic "0" representing the attribute mismatch is output to the attribute match line 30_2 corresponding to the memory word 11_2, and thus "0" is output to the corresponding third flag register 31_2. Is stored in memory word 11_
The first switch 33_2 corresponding to 2 is turned off.

As a result, the signal of logic "1" of the second flag register 24_4 corresponding to the memory word 11_4 is input to the priority encoder 16 (see FIG. 1), and the address of the memory word 11_4 is obtained. , It is known in advance that the attribute IV is stored in the memory word 11_4, and when it is desired to read, for example, the data of the attribute III in the same group, 1 is subtracted from the obtained address to obtain the address of the memory word 11_3. It is sufficient to obtain the address, input the address to the address decoder 17, and read the content of the memory word 11_3.

On the other hand, at the time of the second search, instead of the search data consisting of the attribute IV and the data'D ', for example, the attribute I
When the search is performed using the search data including V and the data “B”, the attributes of the memory word 11_4 match, so that the second switch 34_4 is turned on and the data line 3
The signal of logic '1' output to 2_1 is taken in, but since the data is different, logic '0' indicating mismatch is output to the match line 14_4, and the first and second flag registers 23_4, 24_4. Is latched with a logic '0' indicating that no match was found. In addition, the attribute does not match for the memory word 11_2 with which the data'B 'matches, and therefore both the attribute and the data do not match.

As described above, in the associative memory shown in FIG. 4, even if data stored in memory words separated from each other in the same group, or when data are searched in the reverse order. Even, a search can be done.

Here, the data lines 32_1, 32_2, ... In the associative memory shown in FIG. 4 have fixed lengths on the assumption that the number of data belonging to one group is predetermined. When the fixed-length data line is provided in this way, it is necessary to estimate the maximum number of data belonging to one group and to provide the data line with the length corresponding to the maximum number of data. In this case, when a data group is composed of a number of data smaller than the maximum, useless memory words are generated. Therefore, it is preferable that the data line has a variable length according to the number of data belonging to one group.

FIG. 5 is a schematic diagram showing one method for realizing a variable length data line.

The data line 32 has a plurality of memory words 11_.
1, 11_2, 11_3, ..., On the data line 32, switches 40_1, 40_2, 40_3, ... Corresponding to the other memory words 11_2, 11_3, ... They are connected in series with each other. Each of these switches 40_
2, 40_3, 40_4, ... Corresponding memory words 11_2, 11_3, 11_4, ... And memory words 11_1, 11_2, 11_3, which are adjacent immediately above them.
It is located between ... Those switches 40_
Every other switch 40_2, 40_4, 40_6, ... Of the switches 2, 40_3, 40_4, ...
1 is turned on by the first switch control signal output to 1,
The third switch 40_3, 40_7, ... Are turned on by the second switch control signal output to the second control line 42, and the eighth switch 40_ of the remaining switches.
5, ... Are turned on by the third switch control signal output to the third control line 43.

The number of data constituting one data group is 2
In this case, by outputting the first switch control signal to the first control line 41, every other switch 40_2, 4
Turn on 0_4, 40_6, ... As a result, each two memory words 11_1, 11_2; 11_3, 11_
4; 11_5, 11_6; ... The data lines cut off are formed. Further, when the number of data forming one data group is 4, the first switch control signal is output to the first control line 41 and the second switch control signal is output to the second control line 42. . Then 4 memory words 1 each
1_1, 11_2, 11_3, 11_4; 11_5, 1
A data line that is cut is formed every 1_6, .... Similarly, when the number of data forming one data group is 8, the first and second switch control signals are output to the first control line 41 and the second control line 42, respectively, and the third control line is output.
The third switch control signal is output to the control line 43. As a result, each of the eight memory words 11_1, ..., 11_
8; 11_9, ..., A disconnected data line is formed.

According to this method, when the number of data constituting one data group is 2 ⁿ , no vacancy occurs in the memory word, but when it is other than 2 ⁿ , for example, 3, 5, 9 etc., it is vacant. A memory word will result. To prevent this empty memory word from occurring, a large number of switches 40_
If 2, 40_3, ... Can be arbitrarily turned on and off, the number of control lines becomes large, and the control circuit that outputs the switch control signal to these control lines becomes complicated. Therefore, the method shown in FIG. 5 is not suitable for completely arbitrarily controlling the length of the data line.

FIG. 6 is a schematic diagram showing another method for realizing variable data lines.

The data line 32 spans multiple memory words.
Connected to the data line 32 in series with each other,
The switches 40_2, 40_3, 40_4 corresponding to the respective memory words other than the uppermost memory word.
Is provided in the same manner as in the case of FIG. In each memory word, each attribute storage unit 11_1_1, 11_2
_1, 11_3_1, ... Are provided, and these attribute storage units 11_1_1, 11_2_1, 11_3_1 ,.
Each of the illustrated attributes I, II, III, IV is stored in. In this example, the attribute storage unit 11_1_1,
The attributes stored in 11_2_1, 11_3_1, ...
Depending on whether the attribute is I or the other attributes II, III, and IV, the corresponding switch is kept off for the attribute I, and the corresponding switch is turned on for the other attributes II, III, and IV. It is configured to do. According to this structure, the data of the attribute I is arranged at the head of each data group regardless of the number of data constituting one data group or the data groups having different data numbers are mixed. By doing so, a data line is automatically formed for each memory word of a sufficient number.

FIG. 7 is a circuit diagram showing an example of an attribute judging circuit for judging whether the attribute is I or not.

Here, "000" is assigned to the attribute I, and when the attribute stored in the attribute storage unit 11_i_1 is the attribute I ('000'), "0" is output from the OR gate, and therefore the transistor 40 The switch constituted by is turned off, and the data lines on both sides of the transistor 40 'are electrically disconnected. Attribute storage unit 11_i
When the attribute stored in _1 is an attribute other than the attribute I, "1" is output from the OR gate, the transistor 40 is turned on, and the data lines on both sides of the transistor are connected.

As described above, in the associative memory shown in FIG. 4, the lengths of the data lines 32_1, 32_2, ... Can be adjusted in accordance with the number of data constituting one data group. Of course, the length of the data line may be adjusted by controlling the switch with a dedicated control line instead of using the attribute data.

[0047]

In the associative memory, it is required to reduce the power consumption like other general RAM memories. In a general RAM memory, an address is input and a memory word at that address is accessed. Therefore, a large number of memory words are divided into a large number of blocks, and the address is designated according to the input address. Power consumption is reduced by activating only a block including a memory word.

However, since the associative memory searches the memory word in which the search data is input and the stored data that matches the search data is stored, even if it is divided into blocks, any memory of the block is searched. Since it is not known whether a match is detected in a word, it is necessary to activate all the blocks, and it is not possible to reduce the power consumption by simply dividing the blocks.

In Japanese Patent Laid-Open No. 3-212896, a block selecting means for selecting one of the blocks by dividing the associative memory array into a plurality of unidirectional arrays is provided. It is described that the current consumption of the associative memory is reduced by comparing only the block selected by the selection means with the search data.

However, in the technique described in Japanese Patent Laid-Open No. 3-212896, it is necessary to previously enter the memory block selection information into a part of the input address at the time of retrieval.
Further, there is a problem that extra hardware and processing time are required for the interpretation.

In view of the above circumstances, it is an object of the present invention to provide an associative memory in which only the necessary part is activated under the condition that the entire circuit does not need to be activated, thereby reducing the power consumption. And

[0052]

The associative memory of the present invention for achieving the above object stores a large number of stored data,
In an associative memory for inputting search data and searching for stored data corresponding to the input search data, (1) At least one memory word group including a plurality of memory words in which each stored data is stored is included. A large number of memory words divided into a plurality of memory blocks (2) A plurality of memory words corresponding to a large number of memory words are stored in the corresponding memory words at the time of search, corresponding to the input search data. A flag register that stores a match flag indicating that the stored data corresponding to the input search data was stored when it was detected that the data was stored (3) The flag in the previous search The bit that drives the bit line of the specified memory block during this search, depending on the state of the match flag stored in the register. Characterized by comprising a drive circuit.

[0053]

In the associative memory of the present invention, as described with reference to FIG. 4, for example, when data of a plurality of words are continuously searched, the first search activates all the blocks, but At the time of the subsequent searches, the previous search result is reflected in the current search, and the memory block including the memory word in which the match is detected last time and / or the same memory word group is divided and stored. Only other memory blocks (for example, adjacent blocks) that have a possibility are activated, and power consumption is reduced.

[0054]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 8 is a block diagram of a first embodiment of the associative memory of the present invention.

In this associative memory, a large number of memory words are divided into a plurality of memory blocks, and a plurality of (N in the embodiment) memory blocks 51_ are formed as in a normal large capacity memory.
1, 51_2, ..., 51_N. Each of the memory blocks 51_1, 51_2, ..., 51_N is configured by at least one memory block group including a plurality of memory blocks, which is a unit for performing a search across a plurality of words.

Each block 51_1, 51_2, ..., 51
_N are bit line drive circuits 52_1 and 52_, respectively.
, ..., 52_N, and each bit line drive circuit 52_1, 52_2, ..., 52_N has a search data line 53, control lines 54A and 54B, and an intra-block matching line 5
5_1, 55_2, ..., 55_N are connected.

Search data line (also referred to as bit line)
In 53, search data for reading / writing the memory or performing a search is input.

The control line 54A is activated when performing a search operation.

The control line 54B is activated when the first search data is input in the search over a plurality of words, and invalidates the search results up to the previous time.

Intra-block matching lines 55_1, 55_
2, ..., 55_N are activated when at least one of the plurality of words included in each memory block is matched.

The intra-block coincidence line and a circuit (not shown) for generating the coincidence line are provided in a general associative memory for prioritizing a plurality of divided memory blocks, and the present invention This is not new hardware required for implementation of.

The bit line drive circuits 52_1 and 52_
2, ..., 52_N are their respective lines 53, 54A, 54
According to the signal states of B, 55_1, 55_2, ... 55_N, as a result of the search, a match occurs in itself, and when the corresponding in-block match line is activated, the bit line (including the bit bar line is activated). ) 56_1, 56_2, ..., 56
_N is driven to activate only the corresponding memory block to perform the search operation.

FIG. 9 is a circuit diagram showing the i-th bit line drive circuit of FIG.

In FIG. 9, 60_i is an OR gate for outputting the logical sum of the signal on the initial search control line 54B and the intra-block matching line 55_i, and 61_i is the memory block 51.
_I for activating the bit line 56_i_1, the transfer gate is turned on / off by the output of the OR gate 60_i, 62_i is an inverter for inverting the output of the OR gate 60_i, and 63_i is for inverting the output of the transfer gate 61_i. The bit bar line 56_i_ connected to the memory block 51_i.
2 is an inverter for activating 2.

First, in the first search, the first search control line 5
A control signal of logic '1' is applied to 4B, and the control signal is transmitted to the transfer gate 61_i via the OR gate 60_i and transferred to the transfer gate 61_i.
i is turned on, and the search data input via the search data line 53 is applied to the bit line 56_i_1 and the bit bar line 56_i_2. In this first search, all memory blocks 51_
A search is performed at 1, 51_2, ..., 51_N.

The flag register in the memory block 51_i (the second flag register 24_1, 24_2, FIG. 4)
When a logical "1" is stored in any one of the blocks (see ...), the OR gate 64_i that performs the logical sum operation of the storage states of the flag registers in the block, the logical "1" is stored in the intra-block match line 55_i. 'Is output.

During the second and subsequent searches, a control signal of logic "0" is applied to the control line 54B. Therefore, only when a match is detected in any of the memory words of the block 51_i in the previous search, the search data input via the search data line 53 in the current search is changed to the bit line 56_i_1. , Bit bar line 56_i_2. If no match is detected in any of the memory words of the memory block 51_i during the previous search, the in-block match line 55_i remains at logic “0”, and the output of the OR gate 60_i is at logic “0”. 'Because the transfer gate 61_i is in the "off" state, and the search data input via the search data line 53 in this search is the bit line 56_i_1,
The bit line 56_i_2 is not applied to the bit line 56_i_2.
Power consumption due to charging / discharging of the _i_1 and the bit bar line 56_i_2 is suppressed.

As an example, consider the case where four consecutive search data are searched. When the first search data is input, the control line 54B is activated and the bit line drive circuit 5
, 52_N, all bit lines (including bit bar lines) are activated, and all N blocks 51_1, 51_2, ..., 51_N are activated.

When a match is detected in p blocks (p ≦ N; N is the total number of blocks) in the first search,
The p in-block match lines are activated, and the second search operation is performed only on p memory blocks. As a result, when a match is detected in q (q ≦ p) blocks, q in-block match lines are activated this time. It is assumed that a match is detected in r (r ≦ q) memory blocks in the third and s (s ≦ r) memory blocks in the fourth.

The memory blocks activated in this way are sequentially reduced, and the power consumption of a circuit which does not have a bit line drive circuit and always searches all memory words is (p / N) × ( q / N) × (r / N) × (s / N) <<
Power consumption of 1 will suffice.

Normally, p, q, r, and s << N, and it is possible to achieve a great reduction in power consumption for a plurality of continuous search operations.

Next, the second embodiment of the present invention will be described in detail.

FIG. 10 shows the overall construction of the second embodiment.
FIG. 11 shows a detailed configuration.

In the memory block 51_i of FIG. 11, 70_1_i to 70_k_i are each memory word 1
The register 71_i for storing the match flag output from 1_1_i to 11_k_i is a switch element 72_1 corresponding to the register 71_i when the match flag is stored in any of the match flag storage registers 70_1_i to 70_k_i.
Wired NOR including a wire grounded by _i to 72_k_i, 73_i is a switch element for connecting the wire to a power source to precharge and maintaining the state, 74_i is the wired NOR 71_i
Is an inverter for inverting the output of the above-mentioned and making it an in-block coincidence signal (hit flag). The combination of the wired NOR 71_i and the inverter 74_i corresponds to the OR gate 64_i in FIG.

In the bit line drive circuit 52_i of FIG. 11, 80_i is the corresponding memory block 51_i and the preceding and following memory blocks 51_i-1 (not shown), 51.
_I + 1 is a register for storing the in-block hit flag, 81_i is an OR gate that outputs the logical sum of the output of the in-block hit flag storage register 80_i and the output of the initial search control line 54B (corresponding to the OR gate 60_i of FIG. 9). ), 82_i is the OR gate 81_i.
And an output of a search control line 54A (omitted in FIG. 9) and an AND gate (omitted in FIG. 9), 83_
i is a transfer gate (corresponding to the transfer gate 61_i in FIG. 9) whose ON / OFF state is controlled by the output of the AND gate 82_i for activating the bit line 56_i_1, and 84_i is the bit bar line 56_i.
The AND gate 82_i for activating i_2
An ON-OFF state is controlled by the output of the transfer gate with an inverter (corresponding to a combination of the transfer gate 61_i and the inverter 63_i in FIG. 9),
85_i and 86_i are bit lines 56_i_, respectively.
A switch element for precharging 1,56_i_2.

When the search data belonging to the same word group is input across two memory blocks, even if the block in which no match is detected in the above search is activated in the current search, Need to be converted. For this reason, in this second embodiment, the bit line drive circuit also receives the in-block match lines on both sides thereof.

It is possible that search data belonging to the same word group is input over three blocks, but in general, it is unlikely that certain related data will extend over three or more blocks. It is sufficient to consider the data over two blocks. If it can be assumed that the data spans three blocks, it is sufficient to input not only the adjacent blocks but also the intra-block matching lines of the blocks next to the blocks to the block line driving circuit.

The effect of the second embodiment will be described along with the search operation.

As an example, consider a case where a search for a word group including three words is performed three times in a row. In the first search, the first search control line 54B is activated, the search data is applied to the bit line, and the search operation is started.
Activate 4A. Since the control line 54B is activated,
In the first search, all 1 memory blocks are activated, and the search is performed on all memory areas.

When the control line 54A is activated, the precharge of the bit line drive circuit and the precharge of the memory block are released, the search data is applied to the memory, and the search result is detected.

The result is stored in the match flag storage register 70_i in the memory block and the in-block hit flag storage register 80_i of the bit line drive circuit 52_i. As a whole, p pieces (p ≦ N;
When a match is detected in N memory blocks (the total number of blocks), 3p (3p ≦ N) memory blocks are activated in the worst case where the match detection blocks are not at both end positions in the second search. To be done. As a result, if a match is detected in q memory blocks, in the third search,
At the worst, 3q memory blocks are activated. As a result, the power consumption is (N / N) × (3p / N) × (3q / N) << 1 times the power consumption of the circuit that does not have the configuration of this embodiment.

Usually, p and q << N, and a significant reduction in power consumption is achieved.

FIG. 12 shows a third embodiment of the present invention.

The present embodiment is effective when the number of data words between memory blocks can be estimated in advance.

That is, the memory blocks on both sides must be activated only when the word in which the match occurs constitutes the same word group as the word in the adjacent memory block. When the word group exists in a single memory block, even if a match occurs, only its own memory block needs to be activated.

Therefore, in the memory block, the intra-block coincidence signal goes to only the bit line driving circuit of its own, the bit line driving circuit of its own and the left adjacent bit line driving, and the bit line driving of its own and right adjacent bit lines. Although it goes to the circuit, it is classified and output in three ways.

By adopting this configuration, the probability of activated blocks is lower than in the second embodiment, and a significant reduction in power consumption is achieved.

In each of the above embodiments,
All the memory blocks are activated at the time of the initial search, but it is also possible to limit the number of memory blocks activated at the time of the initial search, for example, by the technique described in Japanese Patent Laid-Open No. 3-212896. Is.

[0090]

As described above, in the associative memory of the present invention, when a plurality of continuous searches are performed, the memory blocks that matched in the previous search and / or the same memory word group are divided and stored. Since only other memory blocks (for example, adjacent blocks) that may be present are activated, the power consumption is greatly reduced.

[Brief description of drawings]

FIG. 1 is a circuit block diagram showing an example of a conventional associative memory.

FIG. 2 is a block diagram showing an example of a conventional associative memory having a data expansion function.

FIG. 3 is a diagram showing an example of group structure data.

FIG. 4 is a block diagram showing a comparative example of an associative memory.

FIG. 5 is a schematic diagram showing one method for realizing a variable length data line.

FIG. 6 is a schematic diagram showing another method for realizing a variable length data line.

FIG. 7 is a circuit diagram showing an example of an attribute determination circuit.

FIG. 8 is a block diagram of a first embodiment of an associative memory according to the present invention.

FIG. 9 is a circuit diagram of a bit line drive circuit used in the first embodiment.

FIG. 10 is a block diagram of a second embodiment of the associative memory of the present invention.

FIG. 11 is a circuit diagram of a bit line drive circuit used in the second embodiment.

FIG. 12 is a block diagram of a third embodiment of an associative memory according to the present invention.

[Explanation of symbols]

11_1, 11_2, ... Memory word 11_1_1, 11_2_1, ... Attribute storage section 11_1_2, 11_2_2, ... Data storage section 14_1, 14_2, ... Matching line 16 Priority encoder 17 Address decoder 18_1, 18_2, ... Word line 20_1, 20_2, ... And gate 21_1, 21_2, ... OR gate 23_1, 23_2, ... First flag register 24_1, 24_2, ... Second flag register 25 Match result latch control line 30_1, 30_2, ... Attribute match line 31_1, 31_2, ... Third flag register 32_1, 32_2, ... Data lines 33_1, 33_2, ... First switches 34_1, 34_2, ... Second switches 51_1, 51_2, ... Memory blocks 52_1, 52_2, ... Bit line drive control Circuit 53 Search data line 54A Search control line 54B First search control line 55_1, 55_2, ... In-block match line 56_1, 56_2, ... Bit line (including bit bar line) 70_1_i, 70_2_i, ... Match flag storage register 80_i In-block hit flag Storage register

Claims (9)

[Claims] 1. An associative memory for storing a large number of stored data, inputting search data, and searching for stored data corresponding to the input search data. A plurality of memory words each of which is divided into a plurality of memory blocks so as to include at least one memory word group, and a corresponding memory provided at the time of searching When it is detected that the stored data corresponding to the input search data is stored in the word, a match flag indicating that the stored data corresponding to the input search data is stored is stored. According to the state of the flag register and the match flag stored in the flag register at the time of the previous search, at the time of the current search, Associative memory to the bit line drive circuit for driving the bit line constant in the memory block, further comprising a said. 2. The associative memory according to claim 1, wherein the bit line drive circuit is adapted to drive a bit line of a memory block including a memory word corresponding to a flag register in which the match flag is stored. 3. The bit line driving circuit according to claim 2, further driving bit lines of another memory block in which the memory word group may be divided and stored. Associative memory. 4. The association according to claim 3, wherein the other memory block to which the bit line is driven is a memory block adjacent to a memory block including a memory word corresponding to a flag register in which the match flag is stored. memory. 5. The associative device according to claim 2, wherein the bit line driving circuit drives a bit line of a corresponding memory block in accordance with a division state of the memory word group into other memory blocks. memory. 6. The associative memory according to claim 1, wherein the bit lines of all the memory blocks are driven in the first search for the memory word group. 7. The associative memory according to claim 1, wherein only the bit line of a predetermined memory block is driven even when the memory word group is searched for the first time. 8. The associative memory according to claim 1, wherein the match flag is generated from an output of a circuit for prioritizing memory blocks. 9. The memory word group according to claim 1, further comprising a memory word corresponding to the flag register in response to the match flag being stored in the flag register in the previous search. , Associative memory with multiple continuous search control circuits to execute this search.