JPH0548498B2 - - Google Patents

Info

Publication number
JPH0548498B2
JPH0548498B2 JP62112964A JP11296487A JPH0548498B2 JP H0548498 B2 JPH0548498 B2 JP H0548498B2 JP 62112964 A JP62112964 A JP 62112964A JP 11296487 A JP11296487 A JP 11296487A JP H0548498 B2 JPH0548498 B2 JP H0548498B2
Authority
JP
Japan
Prior art keywords
processor
buffer
storage
processing device
invalidation processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP62112964A
Other languages
English (en)
Japanese (ja)
Other versions
JPS63278160A (ja
Inventor
Motoyoshi Hirose
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP62112964A priority Critical patent/JPS63278160A/ja
Publication of JPS63278160A publication Critical patent/JPS63278160A/ja
Publication of JPH0548498B2 publication Critical patent/JPH0548498B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP62112964A 1987-05-09 1987-05-09 バッファ無効化処理装置試験方式 Granted JPS63278160A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62112964A JPS63278160A (ja) 1987-05-09 1987-05-09 バッファ無効化処理装置試験方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62112964A JPS63278160A (ja) 1987-05-09 1987-05-09 バッファ無効化処理装置試験方式

Publications (2)

Publication Number Publication Date
JPS63278160A JPS63278160A (ja) 1988-11-15
JPH0548498B2 true JPH0548498B2 (cs) 1993-07-21

Family

ID=14599946

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62112964A Granted JPS63278160A (ja) 1987-05-09 1987-05-09 バッファ無効化処理装置試験方式

Country Status (1)

Country Link
JP (1) JPS63278160A (cs)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01181138A (ja) * 1988-01-13 1989-07-19 Nec Corp キャッシュ・メモリ内蔵マイクロコンピュータ

Also Published As

Publication number Publication date
JPS63278160A (ja) 1988-11-15

Similar Documents

Publication Publication Date Title
EP0090575B1 (en) Memory system
JPH0668735B2 (ja) キヤツシユメモリ−
JPH0552968B2 (cs)
EP0303648B1 (en) Central processor unit for digital data processing system including cache management mechanism
JPH0532775B2 (cs)
JP4047281B2 (ja) キャッシュメモリをメインメモリに同期させる方法
JPS60124754A (ja) バッファ記憶制御装置
JPH0548498B2 (cs)
GB2037466A (en) Computer with cache memory
JPS6232508B2 (cs)
JP3061818B2 (ja) マイクロ・プロセッサ用アクセス・モニタ装置
KR100201671B1 (ko) 컴퓨팅 시스템 및 컴퓨팅 시스템의 캐시 메모리 이용방법
JP2588547B2 (ja) マルチｃｐｕシステム
JPH04302044A (ja) マルチプロセッサシステム
JPS6129070Y2 (cs)
JPH0258648B2 (cs)
JPH087663B2 (ja) コンピユータ・システムおよびその記憶装置アクセス方法
JPS62174846A (ja) ストアチエツク方式
JPS62248049A (ja) バツフア記憶装置
JPH0320834A (ja) 情報処理装置の初期診断方法
JPS63143659A (ja) ロ−カルメモリ制御方式
JPS6258350A (ja) キヤシユメモリ無効化処理方式
JPH0414147A (ja) 中央演算処理装置
JPH01280851A (ja) キャッシュ・ストア制御方式
JPH0484242A (ja) データ処理装置

Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees