JPH0548449A - Digital pll circuit - Google Patents

Abstract

PURPOSE:To allow the circuit to follow-up a frequency shift of an input signal or the like by widening a width of a lock range without increasing the frequency of a master clock signal. CONSTITUTION:When a counter circuit 4 is not in over-running by a frequency control circuit 2, the period of the counter circuit 4 is controlled for the setting period and when the counter circuit 4 is in the over-running state, the setting period is increased/decreased to control the period of the counter circuit 4 thereby widening the width of a lock range without increasing the frequency of the master clock signal and allowing the PLL circuit to follow-up a frequency shift of the input signal or the like.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital PLL circuit used when receiving and demodulating an AES / EBU digital audio signal or the like.

[0002]

2. Description of the Related Art A digital PLL used for receiving and demodulating AES / EBU digital audio signals and the like.
As a circuit, the circuit shown in FIG. 3 is conventionally known. The digital PLL circuit shown in this figure includes a transient extraction circuit 101, a frequency control circuit 102, and a phase control circuit 1.
03 and a counter circuit 104, when an input signal is supplied, the transient (edge portion) of the input signal is extracted and a clock signal of a predetermined frequency, for example, 128 fs, synchronized with the transient is generated. Then, this is output to the next stage circuit (not shown).

The transient extraction circuit 101 comprises two D-type flip-flops 105, 1 connected in cascade.
06 and these D-type flip-flops 105 and 106
4A includes an exclusive OR circuit 107 that calculates an exclusive OR of the signals output from FIG. 4A and the master clock signal illustrated in FIG. 4B is input.
When an input signal as shown in FIG. 4 is input, the D-type flip-flop 105 in the first stage shifts the input signal to generate the signal shown in FIG. The signal output from the first-stage D-type flip-flop 105 is further shifted by 106 to generate the signal (reference signal) shown in FIG. 4D, which is supplied to the phase control circuit 103, and
The exclusive OR circuit 107 generates the transient signal shown in FIG. 2E based on the signals output from the D-type flip-flops 105 and 106, and outputs the transient signal to the frequency control circuit 102 and the counter circuit 104. Supply.

The frequency control circuit 102 is transient-
A timer 108 that generates a clock signal for measuring the length between transients, and the transient extraction circuit 10 based on the clock signal output from the timer 108.
Cycle switch 109 for measuring the length of the transient output from 1 and generating a frequency control signal for designating the number of bits of the counter circuit 104.
And a low-pass filter circuit 110 that cuts high-frequency components of the frequency control signal output from the cycle switch 109, and the transient extraction circuit 1
The transient-transient length is measured on the basis of the transient signal output from 01, and a frequency control signal designating the number of bits of the counter circuit 104 is generated based on the measurement result. The high frequency component of the signal is cut and supplied to the counter circuit 104.

The phase control circuit 103 compares the phase of the reference signal output from the transient extraction circuit 101 with the phase of the 128 fs clock signal output from the counter circuit 104, and a value necessary for matching them. Phase comparison circuit 11 for generating the phase control signal of
1 and a low-pass filter circuit 1 for cutting high frequency components of the phase control signal output from the phase comparison circuit 111.
12 and the transient extraction circuit 10
The reference signal output from 1 and the phase of the 128 fs clock signal output from the counter circuit 104 are compared to generate a phase control signal having a value required to match them, and the phase control signal The high frequency component is cut and supplied to the counter circuit 104. The counter circuit 104 is the transient signal generation circuit 10
Each time a transient signal is output from 1, the number to be added is increased or decreased based on the phase control signal output from the phase control circuit 103, and the phase of the output signal is synchronized with the phase of the transient signal to input the input signal. A constant adder 113 for adding the signal, the number determined by the increase / decrease operation, and the cumulative addition data input to the data input terminal, and the data (cumulative addition data) obtained by the addition operation of the constant adder 113 are fetched. The signal is supplied to the input terminal of the constant adder 113 while holding, and the output is inverted each time the count-up frequency reaches the value indicated by the frequency control signal output from the frequency control circuit 102, and this is inverted to a clock signal of 128 fs. Is output to the next-stage circuit as well as the phase comparison circuit 11 And a D-type flip-flop of the "n" bits to be supplied to.

Each time a transient signal is output from the transient signal generation circuit 101, the number of additions is increased or decreased based on the phase control signal output from the phase control circuit 103, and the phase of the output signal is changed to the transient. The constant adder 113 is operated at a timing synchronized with the phase of the signal to cyclically add the cumulative addition data held in the D-type flip-flop 114 and the number determined by the increase / decrease operation, and the count-up count is the above-mentioned. Frequency control circuit 102
When the value indicated by the frequency control signal output from, for example, "2" is reached, the output is inverted as shown in FIG. 4 (f), and the signal obtained by this inversion operation is used as the 128 fs clock signal to perform the phase comparison. Output to the circuit 103 and the next stage circuit.

As described above, in the digital PLL circuit, when the input signal is supplied, the transient signal of the input signal is extracted, and the value to be added is increased or decreased according to the phase of the transient signal while the counter is being increased or decreased. A cumulative addition operation is performed by the circuit 104, and the output is inverted each time the number of count-ups reaches the value indicated by the frequency control signal output from the frequency control circuit, and the signal obtained by this inversion operation is changed to 128.
It is output to the next stage circuit as a clock signal of fs.

[0008]

However, in the above-described conventional digital PLL circuit, the counter circuit 104 is configured to free run when the transient signal is not output from the transient circuit 101, as shown in FIG. 4 (f). Therefore, the lock range becomes the strictest in the 3T section of the input signal, that is, in the longest cycle period. Therefore, for example, the frequency control circuit 102
When the value of the frequency control signal output from the device indicates 2 bits, "+1/12 (8.3%)" and "-2/12
Only the lock range of (16.6%) ”can be secured.

In addition, the frequency control circuit 1 according to the input signal
The value of the frequency control signal output from the cycle switch 109 of 02 is "2" bit to "2.5" bit, "3"
Even if a plurality of lock ranges are provided by switching to bits as shown in FIG. 5, the range of the lock range cannot be set finely, and it is difficult to follow the frequency shift of the input signal. It was

Therefore, the value of the frequency control signal output from the cycle switch 109 of the frequency control circuit 102 can be switched to "4" bits or more so that the range of the lock range can be set more finely. Although conceivable, such a method is not very realistic because the frequency of the master clock signal must be increased as the number of bits is increased.

In view of the above circumstances, it is an object of the present invention to provide a digital PLL circuit which can widen the lock range and follow the frequency shift of an input signal without increasing the frequency of the master clock signal. I am trying.

[0012]

In order to achieve the above object, a digital PLL circuit according to the present invention extracts a synchronization target portion of an input signal and controls the operation of a counter circuit to correspond to the synchronization target portion. In a digital PLL circuit that generates a clock signal of a frequency, when the counter circuit is not overrunning, the cycle of the counter circuit is controlled at a set cycle, and when the counter circuit is overrunning, the set cycle is set. A cycle switching circuit for controlling the cycle of the counter circuit by increasing or decreasing is provided.

[0013]

In the above structure, when the counter circuit is not overrunning by the cycle switching circuit,
When the cycle of the counter circuit is controlled by the set cycle and the counter circuit is overrunning, the set cycle is increased or decreased to control the cycle of the counter circuit, thereby increasing the frequency of the master clock signal. The width of the lock range is widened to follow the frequency shift of the input signal.

[0014]

1 is a block diagram showing an embodiment of a digital PLL circuit according to the present invention. The digital PLL circuit shown in this figure includes a transient extraction circuit 1, a frequency control circuit 2, a phase control circuit 3, and a counter circuit 4. When an input signal is supplied, the transient signal of this input signal is supplied. And the transient-to-transient length is measured based on this transient signal, and the value of the number of bits indicated by the frequency control signal is dynamically changed according to the measurement result and synchronized with the transient signal. A clock signal having a predetermined frequency, for example 128 fs, is generated and output to a next stage circuit (not shown).

The transient extraction circuit 1 has two D-type flip-flops 5 and 6 connected in cascade and an exclusive OR for calculating an exclusive OR of the signals output from the D-type flip-flops 5 and 6, respectively. With the circuit 7 and the master clock signal is input,
When an input signal is input, the D-type flip-flop 5 in the first stage shifts the input signal and
The D-type flip-flop 6 in the second stage further shifts the signal output from the D-type flip-flop 5 in the first stage to generate a reference signal, which is supplied to the phase control circuit 3 and the exclusive OR circuit. A transient signal is generated by 7 based on the signals output from the D-type flip-flops 5 and 6, and is supplied to the frequency control circuit 2 and the counter circuit 4.

The frequency control circuit 2 outputs a transient signal from the transient extracting circuit 1 based on the timer 8 for generating a clock signal for measuring the length between transients and the clock signal output from the timer 8. Every time, a period switch 9 for measuring the length between the transients based on the transient signal and generating a frequency control signal for designating the number of bits of the counter circuit 4, and a period switch 9 for outputting the same. When the carry signal is not output from the low-pass filter circuit 10 that cuts off the high-frequency component of the frequency control signal, and the counter circuit 4 outputs the frequency control signal output from the low-pass filter circuit 10 and outputs it as it is. When the carry signal is output, , The number of bits indicated by the frequency control signal output from the low-pass filter circuit 10 is dynamically increased or decreased and output, and thereafter, when the transient signal is output from the transient extraction circuit 1, before the carry signal is output. And a dynamic controller 11 for returning to the state of FIG.

Then, the length between transients is measured based on the transient signal output from the transient extraction circuit 1, and a frequency control signal designating the number of bits of the counter circuit 4 is determined based on the measurement result. The high frequency component of the frequency control signal is generated and cut and supplied to the counter circuit 4.
After that, when the carry signal is output from the counter circuit 4, the number of bits of the frequency control signal output from the low-pass filter circuit 10 is dynamically changed until the next transient signal is output from the transient extraction circuit 1. And the frequency control signal obtained by this increase / decrease operation is supplied to the counter circuit 4.

Further, the phase control circuit 3 compares the phase of the reference signal output from the transient extraction circuit 1 with the phase of the 128 fs clock signal output from the counter circuit 4, and a value necessary for matching them. And a low-pass filter circuit 13 for cutting high-frequency components of the phase control signal output from the phase comparison circuit 12, and the transient extraction circuit 1 outputs the phase control signal. Reference signal and 12 output from the counter circuit 4
The phase of the 8 fs clock signal is compared with each other to generate a phase control signal having a value necessary for matching them, and the high frequency component of the phase control signal is cut and supplied to the counter circuit 4.

The counter circuit 4 increases / decreases the number of additions based on the phase control signal output from the phase control circuit 3 each time the transient signal generation circuit 1 outputs a transient signal, and changes the phase of the output signal. The constant adder 14 adds the input signal, the number determined by the increase / decrease operation, and the cumulative addition data input to the data input terminal in synchronization with the phase of the transient signal, and the constant adder 14 performs the addition operation. The obtained data (cumulative addition data) is taken in and held and supplied to the input terminal of the constant adder 14, and each time the count-up frequency reaches the value indicated by the frequency control signal output from the frequency control circuit. Invert the output and use it as the 128fs clock signal for the next stage circuit. As well as the force, the supplies to the phase comparator 12, at the start of the after overrunning, and supplies it to the frequency control circuit 2 generates a carry signal "n" bits of D-type flip-flop 15
It has and.

Each time the transient signal generation circuit 1 outputs a transient signal, the number of additions is increased or decreased based on the phase control signal output from the phase control circuit 3, while the phase of the output signal is changed. The constant adder 14 is operated at a timing synchronized with the phase of the transient signal to drive the D-type flip-flop 15
The cumulative addition data held in the above and the number determined by the increase / decrease operation are cyclically added, and the number of count-ups becomes a value indicated by the frequency control signal output from the frequency control circuit 2, for example, 2 bits. The output is inverted every time, and the signal obtained by this inversion operation is set to 1
The clock signal of 28 fs is supplied to the phase comparison circuit 3 and is output to the next stage circuit. After that, if an overrunning state occurs, a carry signal is generated and supplied to the frequency control circuit 2.

In this case, when the carry signal is output from the D-type flip-flop 15, the period controller 9 is switched by the dynamic controller 11 of the frequency control circuit 2.
Since the value indicated by the frequency control signal output from is dynamically increased or decreased, the value of the frequency control signal output from the frequency control circuit 2 is incremented from "2" bit to "0.5" bit as shown in FIG. , It is possible to continuously change, and thereby, the "2" bit, the "2.5" bit, and the "3" bit can be overlapped to secure one wide lock range as a whole.
At this time, the lock range is "+1" of "2" bits.
/ 12 "is the upper limit, and" -3/18 "of" 3 "bit
Is the lower limit.

As described above, in this embodiment, when the input signal is supplied, the transient signal of the input signal is extracted, and the value to be added is increased / decreased in synchronization with the transient signal while the counter circuit is being increased / decreased. 4 performs an accumulative addition operation, and inverts the output each time the number of count-ups reaches the value indicated by the frequency control signal output from the frequency control circuit 2, and outputs the signal obtained by this inversion operation at 128 fs. When the counter circuit 4 is output as a clock signal to the next stage circuit and the counter circuit 4 is in the free running state in this state, the value of the frequency control signal output from the frequency control circuit 2 is increased or decreased to change the number of bits of the counter circuit 4. Since it is dynamically increased and decreased, it can be locked without increasing the frequency of the master clock signal. The width of the range wide to be able to follow the frequency shift of the input signal.

[0023]

As described above, according to the present invention, the width of the lock range can be widened to follow the frequency shift of the input signal without increasing the frequency of the master clock signal.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a digital PLL circuit according to the present invention.

FIG. 2 is a table showing an operation example of the digital PLL circuit shown in FIG.

FIG. 3 is a block diagram showing an example of a conventionally known digital PLL circuit.

FIG. 4 is a timing diagram showing an operation example of the digital PLL circuit shown in FIG.

5 is a table showing an operation example of the digital PLL circuit shown in FIG.

[Explanation of symbols]

 1 Transient extraction circuit 2 Frequency control circuit (cycle switching circuit) 3 Phase control circuit 4 Counter circuit 9 Cycle switching device 11 Dynamic controller

Claims (1)

[Claims] 1. A digital PLL circuit for extracting a synchronization target portion of an input signal to control the operation of a counter circuit to generate a clock signal having a frequency corresponding to the synchronization target portion, wherein the counter circuit is overrunning. When not present, the cycle of the counter circuit is controlled by a set cycle, and when the counter circuit is overrunning, the cycle switching circuit that controls the cycle of the counter circuit by increasing or decreasing the set cycle is provided. Characteristic digital PLL circuit.