JPH0548097A - Thin film transistor - Google Patents

Abstract

PURPOSE:To provide a thin film transistor which realizes a large size display screen and high definition display of a display apparatus through cost reduction by improving a method of forming Ta which is mainly used as the electrode wiring material. CONSTITUTION:A gate electrode 2 of TFT 15 to be provided on a glass substrate 1 is formed in a double-layer structure where a second Ta layer not mixing N2 is laminated on a first Ta layer 4 mixing N2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor used for driving a liquid crystal of an active matrix display device.

[0002]

2. Description of the Related Art Liquid crystal display devices, which have the features of thinness and low power consumption, have been attracting attention as display devices that replace CRTs. Among them, an active matrix driving type liquid crystal display device using a thin film transistor (hereinafter abbreviated as TFT) as a switching element has advantages such as a high response speed of liquid crystal and a high display quality. In particular,
Since a TFT using amorphous silicon (hereinafter abbreviated as a-Si) can be formed at a low temperature, it is considered that the display device can have a large screen, high definition, and low cost.
The technological development is active.

5 and 6 show an example of a conventional TFT. Gate wirings 23 and source wirings 30 are arranged in a grid pattern on the glass substrate 21, and picture element electrodes 32 are arranged in a region surrounded by both wirings 23 and 30. A part of the gate wiring 23 becomes the gate electrode 22, and the TFT 35 is formed at the position of the gate electrode 22.

The manufacturing process will be described below. First, a Ta film is deposited on the glass substrate 21 by sputtering to form a gate electrode 22 and a gate wiring 23, and the surfaces of these are anodized to form a first gate insulating film 24. Further, a silicon nitride (hereinafter referred to as “S”) is formed by a plasma CVD method so as to cover the gate insulating film 24 and the glass substrate 21.
A second gate insulating film 25 is formed by depositing iNx).

Next, the amorphous silicon layer 2 is formed on a portion of the second gate insulating film 25 corresponding to the gate electrode 22.
A third insulating film 27 made of 6 and SiNx is sequentially formed by plasma CVD. Then, the third insulating film 2
An a-Si layer 28 doped with P (phosphorus) is deposited so as to make ohmic contact so as to cover both ends of 7 and the a-Si layer 26. Finally, the above P-doped a
A metal such as Mo or Ti is deposited so as to cover the -Si layer 28 and a part of the second gate insulating film 25, and the source electrode 29.
And the source wiring 30 and the drain electrode 31 connected to this
Is formed, and thereby the TFT 35 is manufactured. And
A transparent pixel electrode 32 is formed by depositing indium oxide or the like on the second gate insulating film 25 so as to be in contact with the drain electrode 31.

[0006]

In the liquid crystal display device, one of the important factors in considering the large screen and high definition of the liquid crystal display device.
One is to reduce the resistance of the gate electrode wiring. That is, in the liquid crystal display device, the lower the resistivity of the gate electrode wiring material is, the finer and longer the gate wiring can be made, and thereby the larger screen and the higher definition can be achieved.
In addition, a method of forming an anodic oxide film is mainly used at present in order to enhance the insulation between the gate wiring and the source and drain electrodes and prevent the occurrence of leakage. Conventionally, various metal films such as Ta and Ti have been used as a gate wiring material satisfying these two requirements. However, in order to further increase the screen size and the definition, it is possible to have a lower specific resistance and anodic oxidation. A metal film is needed.

The present invention has been made to meet such a demand, and its object is to reduce the resistance by improving the Ta film forming method which is mainly used as an electrode wiring material. The present invention provides a thin film transistor capable of increasing the screen size and the definition of a display device.

[0008]

In a thin film transistor of the present invention, an insulating film and a semiconductor layer are sequentially deposited on a gate electrode provided on an insulating substrate, and a source electrode and a drain electrode are provided on the semiconductor layer. In the thin film transistor, the gate electrode has a first Ta layer in which impurities are mixed in order from the insulating substrate side, and a second Ta layer in which impurities are not mixed.
The Ta layer is formed of a two-layer structure, and thereby the above-mentioned object is achieved.

[0009]

The thin film transistor of the present invention has a conventional Ta
Its specific resistance is smaller than that of a gate electrode material made of a film. The reason is as follows.

Ta has two types of crystal structures.
One is a square lattice and the other is a body-centered cubic lattice.
The Ta of the square lattice structure is called β-Ta, the resistivity of the thin film is 170 to 200 μΩcm, while the Ta of the body-centered cubic lattice structure is called α-Ta, and the bulk resistivity thereof is 13 ˜15 μΩcm. Therefore, it is important to form the α-Ta layer in order to reduce the resistance of Ta. Generally, most of the thin film Ta is β
It becomes −Ta, but it is known that α-Ta can be formed by mixing a trace amount of impurities such as N ₂ during film formation. However, the mixed N ₂ acts as an impurity at the same time, which naturally limits the lowering of Ta resistance, and the specific resistance was 60 to 100 μΩcm.

Therefore, in the present invention, Ta mixed with N ₂ is used.
It was decided to form a two-layer structure in which a Ta film in which N ₂ is not mixed is laminated on the upper layer of the film. As a result, Ta in the upper layer becomes α-Ta as in the lower layer by epitaxial growth, and since it does not contain impurities, it is possible to obtain a film having a low specific resistance of about 20 μΩcm.

[0012]

EXAMPLES Examples of the present invention will be described below.

As shown in FIG. 1 and FIG.
The FT has a glass substrate 1 as an insulating substrate, a gate electrode 2 arranged on the glass substrate 1, a gate wiring 3 and a source wiring 12 arranged on the gate electrode 2 in a grid pattern. A part of the gate wiring 3 becomes the gate electrode 2 of the TFT 15. The gate electrode 2 and the gate wiring 3 have a two-layer structure of a first Ta layer 4 made of Ta mixed with impurities and a second Ta layer 5 made of Ta not mixed with impurities. A first insulating film 6 formed by anodizing the surfaces of the gate electrode 2 and the gate wiring 3 is formed, and a second insulating film 6 and a second insulating film 6 coated with SiNx are formed on the glass substrate 1. The insulating film 7 is formed.

Further, a semiconductor layer 8 formed by depositing a-Si is formed so as to cover the insulating film 7 protruding at the position of the gate electrode 2, and SiNx is deposited at the center of the upper surface of the semiconductor layer 8. The third insulating film 9 is formed. Further, a semiconductor layer 10 formed by depositing a-Si doped with P so as to cover both sides of the third insulating film 9 and the semiconductor layer 8.
10 'is formed. The semiconductor layers 10 and 10 ′ are a semiconductor layer 8 and a source electrode 11 and a drain electrode 13 described next.
It is formed to make ohmic contact with. A source electrode 11 formed by depositing Mo on one semiconductor layer 10 and a source wiring 1 branching the source electrode 11
2 is formed. Further, the drain electrode 13 formed by depositing Mo is formed on the other semiconductor layer 10 ′, and the TFT 15 is thus manufactured. Then, a pixel electrode 14 is formed by depositing indium oxide on the second insulating film 7 so as to partially overlap the drain electrode 13. The TFTs 15 are pixel electrodes 14 arranged in a matrix in a region surrounded by the gate wiring 3 and the source wiring 12.
Are arranged in a number corresponding to, and an active matrix substrate is manufactured.

A specific method of manufacturing the TFT having the above structure will be described with reference to FIGS. 3 and 4.

As shown in FIG. 3A, first, a first Ta layer 4 containing N ₂ having a thickness of several nm to several tens nm and a second Ta layer 4 having no N ₂ having a thickness of 300 nm are mixed on a glass substrate 1. After continuously depositing the Ta layer 5 on the entire surface by sputtering, etching is performed by covering the surface of the Ta layers 4 and 5 in a necessary portion with a mask made of a photoresist film, and etching is performed with a gate having a pattern shown by a broken line in FIG. Electrode 2 and gate wiring 3
To form. Thus, if the gate wiring 3 is formed of Ta alone, the subsequent steps will not be complicated.

Next, as shown in FIG. 3B, the surfaces of the gate electrode 2 and the gate wiring 3 are anodized to form Ta ₂ O ₅
Forming a first insulating film 6 made of, and then forming a second insulating film 7 by sputtering or plasma CVD method 30.
A 0 nm thick SiNx film is continuously deposited over the entire surface.

Next, as shown in FIG. 3C, plasma C
By the VD method, a 30 nm-thick a-Si which becomes the semiconductor layer 8
Layer and 200 nm thick SiN to be the third insulating film 9
After the x film is continuously deposited over the entire surface, the third insulating film 9 is formed into a pattern as shown by photoetching.

Next, as shown in FIG. 4A, plasma C
After the P-doped a-Si layers 10 and 10 'having a thickness of 100 nm are deposited over the entire surface by the VD method, the a-Si layers 10 and 10' and the semiconductor layer 8 are photoetched.
Both side portions of are removed to form a pattern as shown.

Then, as shown in FIG. 4B, the Mo layers 11 and 13 are formed to a thickness of 300 nm by sputtering.
After being deposited on the -Si layers 10 and 10 ', the Mo layers 11 and 13 and the a-Si layers 10 and 1 are formed by photoetching.
By removing the central part of 0 ', etc., the source electrode 11, the source wiring 12 (see FIG. 1) and the drain electrode 13 having the pattern as shown are formed. As a result, the TFT 15 is manufactured.

Finally, as shown in FIG. 4 (c), an indium oxide film is deposited on the second insulating film 7 by sputtering so as to partially overlap the drain electrode 13, and this is photoetched to form a picture. The element electrode 14 is formed.

In the above embodiment, the semiconductor layer 8 made of a-Si, the source electrode 11 made of Mo, and the drain electrode 1 are made.
Semiconductor layer 1 made of a-Si doped with P between
Since 0 and 10 'are provided, there is an advantage that ohmic contact can be established between them.

[0023] If a two-layer structure of the second Ta layer 5 is not mixed with the first Ta layer 4 and N ₂ to the gate line 3 and the gate electrode 2 was mixed with N ₂ as described above, section above action For the reason described above, there is an advantage that the specific resistance of the gate wiring 3 and the gate electrode 2 can be significantly reduced.

At least one TFT 15 having the above structure may be formed on the active matrix substrate.

The manufacturing process is not limited to the method of the above embodiment.

[0026]

As described above, in the thin film transistor of the present invention, the gate electrode is formed of a two-layer structure in which the Ta layer containing no impurities is stacked on the Ta layer containing no impurities, and therefore, the thin film transistor of the present invention has a two-layer structure. The specific resistance of the gate electrode can be significantly reduced. Further, since both layers are made of Ta, the process involved in the stacking does not become complicated, and improvement in manufacturing efficiency can be expected.
Further, since the anodic oxidation can be performed as usual, the insulating property can be improved and the leak generation efficiency can be reduced. Therefore, according to the thin film transistor array in which even one such thin film transistor is provided, it is possible to increase the screen size and the definition of the liquid crystal display device.

[Brief description of drawings]

FIG. 1 is a partial plan view showing an embodiment of a thin film transistor of the present invention.

FIG. 2 is a sectional view taken along line AA of FIG.

FIG. 3 is a cross-sectional view showing the manufacturing process of the thin film transistor of the invention.

FIG. 4 is a cross-sectional view showing the manufacturing process of the thin film transistor of the invention.

FIG. 5 is a partial plan view of a conventional thin film transistor.

6 is a cross-sectional view taken along the line BB of FIG.

[Explanation of symbols]

1 first Ta layer 5 N ₂ second not mixed with the Ta layer 6 first insulating film 7 and the second insulating film 8 semiconductor layer obtained by mixing a glass substrate 2 gate electrode 3 gate wiring 4 N ₂ (a-Si ) 9 third insulating film 10, 10 'semiconductor layer 11 source electrode 12 source wiring 13 drain electrode 14 picture element electrode 15 TFT

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification number Internal reference number FI Technical indication H01L 29/40 A 7738-4M 29/46 R 7738-4M

Claims (1)

[Claims] 1. In a thin film transistor in which an insulating film and a semiconductor layer are sequentially deposited on a gate electrode provided on an insulating substrate, and a source electrode and a drain electrode are provided on the semiconductor layer, the gate electrode is A thin film transistor having a two-layer structure of a first Ta layer in which impurities are mixed in order from the insulating substrate side and a second Ta layer in which impurities are not mixed.