JPH0548073A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0548073A JPH0548073A JP20430291A JP20430291A JPH0548073A JP H0548073 A JPH0548073 A JP H0548073A JP 20430291 A JP20430291 A JP 20430291A JP 20430291 A JP20430291 A JP 20430291A JP H0548073 A JPH0548073 A JP H0548073A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- semiconductor device
- optical waveguide
- substrate
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/24—Coupling light guides
- G02B6/42—Coupling light guides with opto-electronic elements
-
- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/24—Coupling light guides
- G02B6/42—Coupling light guides with opto-electronic elements
- G02B6/43—Arrangements comprising a plurality of opto-electronic elements and associated optical interconnections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12043—Photo diode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、大型計算機の中央演算
処理部（ＣＰＵ）等に用いられるマルチチップ方式の半
導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-chip type semiconductor device used in a central processing unit (CPU) of a large-scale computer.
【０００２】[0002]
【従来の技術】従来の大型計算機のＣＰＵ等に用いられ
るマルチチップ方式の半導体装置については、例えば
「超高速バイポーラデバイス」（培風館、昭和６０年）
２４０頁に記載されており、図５に示すような構造であ
る。すなわち、金属配線１４が形成されたＳｉ基板１上
に、Ｓｉ集積回路チップ１９がはんだバンプを介して貼
り付けられた構造となっている。また、金属配線１４は
ボンディングワイヤ６によってリードフレーム７を有す
るＳｉＣ基板８と電気的に接続する。2. Description of the Related Art A conventional multi-chip type semiconductor device used for a CPU or the like of a large-scale computer is, for example, "Ultra High Speed Bipolar Device" (Baifukan, 1985).
It is described on page 240 and has a structure as shown in FIG. That is, it has a structure in which the Si integrated circuit chip 19 is attached via the solder bumps onto the Si substrate 1 on which the metal wiring 14 is formed. The metal wiring 14 is electrically connected to the SiC substrate 8 having the lead frame 7 by the bonding wire 6.
【０００３】[0003]
【発明が解決しようとする課題】上記従来技術における
半導体装置内のＳｉ集積回路チップ１９間の信号伝送は
金属配線１４によって行われている。システムの処理速
度を決める要因としては、Ｓｉ集積回路チップ自体の演
算速度のほかに、Ｓｉ集積回路チップ間配線の抵抗、容
量、インダクタンスによって信号伝達が遅れるいわゆる
配線遅延がある。システムの規模が大きくなってＳｉ集
積回路チップ数が多くなると配線の数、長さが増加する
ため、システム全体の遅延の中でこの配線遅延が占める
割合が増大するという問題があった。本発明の目的は、
配線遅延を減少させたマルチチップ方式の半導体装置を
提供することにある。The signal transmission between the Si integrated circuit chips 19 in the semiconductor device in the above-mentioned prior art is performed by the metal wiring 14. Factors that determine the processing speed of the system include so-called wiring delay in which signal transmission is delayed due to resistance, capacitance, and inductance of wiring between Si integrated circuit chips in addition to the calculation speed of the Si integrated circuit chips themselves. When the system scale becomes large and the number of Si integrated circuit chips increases, the number and length of wirings increase, so that there is a problem that the wiring delay accounts for a large proportion of the delay of the entire system. The purpose of the present invention is to
An object of the present invention is to provide a multi-chip semiconductor device with reduced wiring delay.
【０００４】[0004]
【課題を解決するための手段】上記目的は、（１）電子
素子集積回路と光素子とが同一基板上に設けられた光電
子集積回路のチップの複数個が配置され、かつ光導波路
が設けられた支持基板を有し、該チップは、該光素子と
該光導波路とが光学的に接続する位置に配置されたこと
を特徴とする半導体装置、（２）上記１記載の半導体装
置において、上記支持基板の光導波路の上層又は下層
に、配線層を有することを特徴とする半導体装置、
（３）上記２記載の半導体装置において、上記配線層は
上記チップの電極と電気的に接続されることを特徴とす
る半導体装置、（４）上記１、２又は３記載の半導体装
置において、上記支持基板は、上記光導波路の複数の層
を有することを特徴とする半導体装置、（５）支持基板
上に、（ｉ）電子素子集積回路と光素子とが同一基板上
に設けられた光電子集積回路のチップの複数個、（ｉ
ｉ）所望のパターンの光導波路及び（ｉｉｉ）所望のパ
ターンの配線層が配置され、かつ、該チップの光素子と
該光導波路とが光学的に接続され、該チップの配線と該
配線層とは電気的に接続されることを特徴とする半導体
装置、（６）上記５記載の半導体装置において、上記支
持基板は、上記光導波路の複数の層を有することを特徴
とする半導体装置にとって達成される。The above objects are (1) a plurality of optoelectronic integrated circuit chips in which an electronic element integrated circuit and an optical element are provided on the same substrate, and an optical waveguide is provided. A semiconductor device having a supporting substrate, and the chip is disposed at a position where the optical element and the optical waveguide are optically connected to each other, A semiconductor device having a wiring layer as an upper layer or a lower layer of the optical waveguide of the supporting substrate,
(3) In the semiconductor device described in 2 above, the wiring layer is electrically connected to an electrode of the chip, (4) In the semiconductor device described in 1) or 2), A supporting substrate has a plurality of layers of the above-mentioned optical waveguide, and (5) a supporting substrate, and (i) an optoelectronic integrated device in which an electronic element integrated circuit and an optical element are provided on the same substrate. A plurality of circuit chips, (i
i) An optical waveguide having a desired pattern and (iii) a wiring layer having a desired pattern are arranged, and an optical element of the chip and the optical waveguide are optically connected, and wiring of the chip and the wiring layer Is electrically connected to the semiconductor device, (6) In the semiconductor device according to the above item 5, the support substrate has a plurality of layers of the optical waveguide. It
【０００５】[0005]
【作用】本発明は、電子素子が集積された半導体基板上
にレーザーダイオード、ホトダイオード等の光素子を配
置した光電子集積回路のチップを用い、チップ間の信号
伝送を電気配線で行なう代りに光信号を光導波路に通し
て行なうため、チップ間配線の抵抗、容量、インダクタ
ンスに起因する遅延がなくなる。また光信号を伝送する
光導波路は従来の電気配線と同様にフォトリソグラフィ
によってパターニングされるため製造歩留まり及び信頼
度に優れている。The present invention uses a chip of an optoelectronic integrated circuit in which optical elements such as laser diodes and photodiodes are arranged on a semiconductor substrate on which electronic elements are integrated, and instead of performing signal transmission between chips by electrical wiring, optical signals are used. Is conducted through the optical waveguide, the delay due to the resistance, capacitance and inductance of the inter-chip wiring is eliminated. Further, the optical waveguide for transmitting an optical signal is patterned by photolithography similarly to the conventional electric wiring, so that the manufacturing yield and reliability are excellent.
【０００６】[0006]
【実施例】実施例１ 本発明の第１の実施例の半導体装置を図１により説明す
る。図１（ａ）はこの半導体装置の全体図で、図１
（ｂ）はその断面図である。Ｓｉ基板１の表面に、Ｓｉ
Ｏ2膜１５、その上に金属配線１４が形成されており、
さらにその上に誘電体の窒化Ｓｉ（ＳｉＮ）膜の細線よ
りなる光導波路３がＳｉＯ2膜１６とＳｉＯ２膜２の間
に挾み込まれて設けられている。この光導波路３等の層
が除去された領域に、Ｓｉ集積回路と光素子が同一基板
上に形成された光電子集積回路のチップ４が貼り付けら
れ、光導波路３とチップ４上のホトダイオード１２ａ、
レーザーダイオード１２ｂとは光学的に接続するように
位置合わせされている。またチップ４上の電気配線は、
ボンディングパッド上に形成されたはんだバンプ１３を
介してＳｉ基板１上の金属配線１４と電気的に接続され
ている。Embodiment 1 A semiconductor device according to a first embodiment of the present invention will be described with reference to FIG. FIG. 1A is an overall view of this semiconductor device.
(B) is the sectional drawing. On the surface of the Si substrate 1, Si
The O 2 film 15 and the metal wiring 14 formed thereon are
Further thereon, an optical waveguide 3 made of a thin wire of a dielectric Si nitride (SiN) film is provided sandwiched between the SiO 2 film 16 and the SiO 2 film 2. A chip 4 of an optoelectronic integrated circuit in which a Si integrated circuit and an optical element are formed on the same substrate is attached to the region where the layers such as the optical waveguide 3 are removed, and the optical waveguide 3 and the photodiode 12a on the chip 4 are attached.
The laser diode 12b is aligned so as to be optically connected. The electrical wiring on the chip 4 is
It is electrically connected to the metal wiring 14 on the Si substrate 1 through the solder bumps 13 formed on the bonding pads.
【０００７】光導波路３はＳｉ基板１の端まで達してそ
こで光ファイバー５と結合し、その光ファイバー５はパ
ッケージのキャップ１１に設けられた孔を通ってパッケ
ージ外に出ている。Ｓｉ基板１上の金属配線１４はＳｉ
基板１に設けられたボンディングパッドまで達し、そこ
からボンディングワイヤ６によってリードフレーム７に
接続されている。なお、図において、８はＳｉＣ基板、
９はムライト枠、１０は放熱フィンである。The optical waveguide 3 reaches the end of the Si substrate 1 and is coupled with the optical fiber 5 there, and the optical fiber 5 goes out of the package through a hole provided in a cap 11 of the package. The metal wiring 14 on the Si substrate 1 is made of Si
It reaches a bonding pad provided on the substrate 1 and is connected to a lead frame 7 by a bonding wire 6 from there. In the figure, 8 is a SiC substrate,
Reference numeral 9 is a mullite frame, and 10 is a radiation fin.
【０００８】次に本実施例の半導体装置の動作を説明す
る。まず外部から光信号が光ファイバー５とそれに結合
した光導波路３を通ってパッケージ内のあるチップ４の
入力用のホトダイオード１２ａに送られ、そこで電気信
号に変換される。次にその信号はそのチップ内で演算処
理され、その結果が出力用のレーザーダイオード１２ｂ
に送られそこで再び光信号に変換される。さらにその光
信号は光導波路３を通って他のチップ４の入力用のホト
ダイオード１２ａに送られる。そのチップにおいてまた
演算処理が行なわれて、その結果が出力用のレーザーダ
イオード１２ｂと光導波路３を通ってさらに別のチップ
（図示せず）に送られる。最後にチップから出た光信号
は、光導波路３と接続した光ファイバー５を通ってパッ
ケージ外に出ていく。Next, the operation of the semiconductor device of this embodiment will be described. First, an optical signal is sent from the outside through the optical fiber 5 and the optical waveguide 3 coupled thereto to the input photodiode 12a of the chip 4 in the package, where it is converted into an electric signal. Next, the signal is processed in the chip, and the result is the laser diode 12b for output.
To be converted into an optical signal again. Further, the optical signal is sent through the optical waveguide 3 to the input photodiode 12a of the other chip 4. In that chip, arithmetic processing is performed again, and the result is sent to another chip (not shown) through the laser diode 12b for output and the optical waveguide 3. Finally, the optical signal emitted from the chip goes out of the package through the optical fiber 5 connected to the optical waveguide 3.
【０００９】次に本実施例の半導体装置の製造方法につ
いて、特にチップ４とＳｉ基板１上の光導波路３及び金
属配線１４との接続部分に関して、その部分の断面を拡
大した図２により説明する。本半導体装置のその他の部
分の製造方法は、従来の方法と基本的に同じである。ま
ずＳｉＯ２膜１５が形成されたＳｉ基板１上に金属膜を
蒸着法により堆積し、ホトリソグラフィとエッチングに
より金属配線１４を形成した後、プラズマ気相成長法に
よりＳｉＯ2膜１６を堆積する（図２（ｂ））。次に誘
電体の窒化Ｓｉ（ＳｉＮ）膜をプラズマ気相成長法によ
り堆積し、ホトリソグラフィとエッチングによりパター
ニングして光導波路３を形成する（図２（ｃ））。Next, a method of manufacturing the semiconductor device according to the present embodiment will be described with reference to FIG. 2 which is an enlarged sectional view of a connection portion between the chip 4 and the optical waveguide 3 and the metal wiring 14 on the Si substrate 1. .. The method of manufacturing the other parts of the semiconductor device is basically the same as the conventional method. First, a metal film is deposited on the Si substrate 1 on which the SiO 2 film 15 is formed by a vapor deposition method, a metal wiring 14 is formed by photolithography and etching, and then a SiO 2 film 16 is deposited by a plasma vapor deposition method ( FIG. 2B). Next, a dielectric silicon nitride (SiN) film is deposited by plasma vapor deposition and patterned by photolithography and etching to form the optical waveguide 3 (FIG. 2C).
【００１０】さらに、プラズマ気相成長法によりＳｉＯ
2膜２を堆積した後、チップ４が貼り付けられる部分の
ＳｉＯ2膜２をホトリソグラフィとエッチングにより選
択的に除去する。さらにボンディングパッドが形成され
ている部分のＳｉＯ2膜１６をホトリソグラフィとエッ
チングにより選択的に除去し、ボンディングパッド上に
通常の方法によりはんだバンプ１３を形成する（図２
（ｄ））。Further, SiO is formed by plasma vapor deposition.
After depositing the 2 film 2, the portion of the SiO 2 film 2 to which the chip 4 is attached is selectively removed by photolithography and etching. Further, the SiO 2 film 16 in the portion where the bonding pad is formed is selectively removed by photolithography and etching, and the solder bump 13 is formed on the bonding pad by a normal method (FIG. 2).
(D)).
【００１１】最後に、表面にホトダイオード１２ａ、レ
ーザーダイオード１２ｂとはんだバンプ１３が形成され
たチップ４をＳｉ基板１上にバンプ同士の結合によって
取付ける。その場合、ホトダイオード１２ａ、レーザー
ダイオード１２ｂが光導波路３に光学的に接続するよう
に、またチップ４上のはんだバンプ１３がＳｉ基板１上
のはんだバンプ１３と電気的に接続するように位置合わ
せし固定する（図２（ｅ））。以下通常の方法によっ
て、（図２（ａ））に示した半導体装置が製造できた。Finally, the chip 4 having the photodiode 12a, the laser diode 12b, and the solder bump 13 formed on the surface thereof is mounted on the Si substrate 1 by bonding the bumps. In that case, the photodiode 12a and the laser diode 12b are aligned so that they are optically connected to the optical waveguide 3 and that the solder bumps 13 on the chip 4 are electrically connected to the solder bumps 13 on the Si substrate 1. Fix it (Fig. 2 (e)). The semiconductor device shown in FIG. 2A could be manufactured by the usual method.
【００１２】本半導体装置ではチップ間の信号のやりと
りが光導波路を通して光信号によって行なわれるため、
電気信号による場合の配線の抵抗、容量、インダクタン
スによる信号伝達遅延がなくなり、システムの演算処理
速度が向上するという効果がある。また光信号を伝送す
る光導波路は従来の電気配線と同様にフォトリソグラフ
ィによってパターニングされるため、電気配線と同等の
製造歩留まり及び信頼度が得られた。In this semiconductor device, since signals are exchanged between chips by optical signals through the optical waveguide,
There is an effect that signal transmission delay due to wiring resistance, capacitance, and inductance in the case of using an electric signal is eliminated, and the processing speed of the system is improved. Further, since the optical waveguide for transmitting an optical signal is patterned by photolithography like the conventional electric wiring, the manufacturing yield and reliability equivalent to those of the electric wiring can be obtained.
【００１３】実施例２ 次に本発明の第２の実施例の半導体装置及びその製造方
法を図３により説明する。図３は本実施例の半導体装置
の主要部分の断面図及びその製造工程を説明する断面図
である。図３（ａ）において、１はＳｉ基板、１８はＬ
ｉＮｂＯ3基板、３はＬｉＮｂＯ3基板に選択的にＴｉを
拡散することにより形成した光導波路である。１６はＳ
ｉＯ2膜、４はＳｉ集積回路とホトダイオード１２ａ、
レーザーダイオード１２ｂが同一基板上に形成されたチ
ップ、１４は金属配線である。本半導体装置においても
第１の実施例と同様、ホトダイオード１２ａ、レーザー
ダイオード１２ｂと光導波路３は光学的に接続してお
り、またチップ４上の電極パッドと金属配線１４は電気
的に接続している。Second Embodiment Next, a semiconductor device and a method of manufacturing the same according to a second embodiment of the present invention will be described with reference to FIG. 3A and 3B are a cross-sectional view of a main part of the semiconductor device of this embodiment and a cross-sectional view illustrating the manufacturing process thereof. In FIG. 3A, 1 is a Si substrate, 18 is L
The iNbO 3 substrate and 3 are optical waveguides formed by selectively diffusing Ti into the LiNbO 3 substrate. 16 is S
iO 2 film, 4 are Si integrated circuit and photodiode 12a,
The laser diode 12b is a chip formed on the same substrate, and 14 is a metal wiring. Also in this semiconductor device, as in the first embodiment, the photodiode 12a, the laser diode 12b and the optical waveguide 3 are optically connected, and the electrode pad on the chip 4 and the metal wiring 14 are electrically connected. There is.
【００１４】次に本半導体装置の製造方法を説明する。
まずＬｉＮｂＯ3基板１８上にホトリソグラフィ及びＴ
ｉの熱拡散により光導波路３を形成する。すなわちＬｉ
ＮｂＯ3基板１８上にＳｉＯ2膜を形成し、ホトレジスト
パターンを用いてＳｉＯ2膜をエッチングしてパターン
とし、ホトレジストを除き、表面にＴｉを蒸着してさら
に熱拡散し、次にＳｉＯ2膜パターンとＴｉを除き、拡
散したＴｉにより光導波路３を形成する。次にＳｉ基板
１と、光導波路３が形成されたＬｉＮｂＯ3基板１８を
はんだを接着剤として貼り合わせる（図３（ｂ））。Next, a method of manufacturing the present semiconductor device will be described.
First, on the LiNbO 3 substrate 18, photolithography and T
The optical waveguide 3 is formed by thermal diffusion of i. That is, Li
A SiO 2 film is formed on the NbO 3 substrate 18, the SiO 2 film is etched into a pattern using a photoresist pattern, the photoresist is removed, and Ti is vapor-deposited on the surface to further diffuse heat, and then the SiO 2 film pattern is formed. Except for Ti and Ti, the optical waveguide 3 is formed of diffused Ti. Next, the Si substrate 1 and the LiNbO 3 substrate 18 on which the optical waveguide 3 is formed are bonded together by using solder as an adhesive (FIG. 3B).
【００１５】次にホトリソグラフィとＳｉＯ2膜１６を
マスクにしたエッチングによりＬｉＮｂＯ3基板１８の
一部を選択的に除去した後、その凹部にはんだを接着材
料として、光電子集積回路のチップ４を、光素子１２と
光導波路３が光学的に接続するように位置合わせしてＳ
ｉ基板１に貼り付ける（図３（ｃ））。Next, a portion of the LiNbO 3 substrate 18 is selectively removed by photolithography and etching using the SiO 2 film 16 as a mask, and then the chip 4 of the optoelectronic integrated circuit is bonded to the recess with solder as an adhesive material. The optical element 12 and the optical waveguide 3 are aligned so that they are optically connected, and S
It is attached to the i substrate 1 (FIG. 3C).
【００１６】次にチップ４とＬｉＮｂＯ3基板１８の隙
間に透明な樹脂であるポリイミドを埋め込んだ後金属膜
を蒸着法により堆積し、ホトリソグラフィとエッチング
によりチップ４上の電極パッドからＬｉＮｂＯ3基板１
８上に延びる金属配線１４を形成する（図３（ａ））。
本実施例の半導体装置の動作及び効果は本発明の第１の
実施例の半導体装置と基本的に同じであった。Next, polyimide, which is a transparent resin, is embedded in the gap between the chip 4 and the LiNbO 3 substrate 18, and then a metal film is deposited by the vapor deposition method, and the LiNbO 3 substrate 1 is deposited from the electrode pads on the chip 4 by photolithography and etching.
The metal wiring 14 extending over the wiring 8 is formed (FIG. 3A).
The operation and effect of the semiconductor device of this example were basically the same as those of the semiconductor device of the first example of the present invention.
【００１７】実施例３ 次に、本発明の第３の実施例の半導体装置を図４を用い
て説明する。図４（ａ）はその主要部分の断面図、図４
（ｂ）はそのＡ部分の拡大斜視図である。本半導体装置
の構造及び動作は、本発明の第２の実施例の半導体装置
と基本的に同じであるが、光導波路３の構造が異なって
いる。すなわち、ＳｉＯ2膜２中にＳｉＮ膜よりなる光
導波路３が２層に形成されている。ただしホトダイオー
ド１２ａ、レーザーダイオード１２ｂと光学的に接続す
る部分の光導波路３の端面はホトダイオード１２ａ、レ
ーザーダイオード１２ｂと同じ高さに揃えられている。Third Embodiment Next, a semiconductor device according to a third embodiment of the present invention will be described with reference to FIG. FIG. 4A is a cross-sectional view of the main part of FIG.
(B) is an enlarged perspective view of the portion A. The structure and operation of this semiconductor device are basically the same as those of the semiconductor device of the second embodiment of the present invention, but the structure of the optical waveguide 3 is different. That is, the optical waveguide 3 made of a SiN film is formed in two layers in the SiO 2 film 2. However, the end surface of the optical waveguide 3 in a portion optically connected to the photodiode 12a and the laser diode 12b is arranged at the same height as the photodiode 12a and the laser diode 12b.
【００１８】この２層の光導波路３も単層の場合と同様
にプラズマ気相成長による薄膜堆積とホトリソグラフィ
及びエッチングを用いたパターニングにより形成され
る。すなわち、まず、ＳｉＯ2膜２の一部を下層の光導
波路３の下の位置まで形成する。ついで下層の光導波路
３となるＳｉＮ膜のパターンを形成し、ＳｉＯ2膜２の
一部分を形成し、上層の光導波路３となるＳｉＮ膜のパ
ターンを形成し、さらに光導波路３の間にＳｉＯ2膜２
を設ける。本実施例の半導体装置によれば光導波路３が
２層構造であるため交差及び積層が可能となり、配線の
ための自由度が増加してより複雑なチップ間の接続が容
易にできるようになった。This two-layer optical waveguide 3 is also formed by thin film deposition by plasma vapor deposition and patterning using photolithography and etching, as in the case of a single layer. That is, first, a part of the SiO 2 film 2 is formed to a position below the lower optical waveguide 3. Then forming a pattern of the SiN film serving as the lower layer of the optical waveguide 3, forms a portion of the SiO 2 film 2, to form a pattern of the SiN film serving as the upper layer of the optical waveguide 3, SiO 2 further between the optical waveguide 3 Membrane 2
To provide. According to the semiconductor device of this embodiment, since the optical waveguide 3 has a two-layer structure, crossing and stacking are possible, the degree of freedom for wiring is increased, and more complicated connection between chips can be facilitated. It was
【００１９】[0019]
【発明の効果】本発明によれば、マルチチップ方式の半
導体装置のチップ間の電気配線の抵抗、容量、インダク
タンスによる遅れがなくなるため、パッケージ内のシス
テムの演算処理速度が約５０パーセント向上した。また
光信号を伝送する光導波路は従来の電気配線と同様にフ
ォトリソグラフィによってパターニングされるため、電
気配線と同等の製造歩留まり及び信頼度が得られた。According to the present invention, the delay due to the resistance, capacitance and inductance of the electric wiring between the chips of the multi-chip type semiconductor device is eliminated, so that the processing speed of the system in the package is improved by about 50%. Further, since the optical waveguide for transmitting an optical signal is patterned by photolithography like the conventional electric wiring, the manufacturing yield and reliability equivalent to those of the electric wiring can be obtained.
【図１】本発明の第１の実施例の半導体装置の全体図及
び縦断面図である。FIG. 1 is an overall view and a vertical sectional view of a semiconductor device according to a first embodiment of the present invention.
【図２】本発明の第１の実施例の半導体装置の主要部分
の縦断面図及びその製造方法を示す工程図である。2A and 2B are a longitudinal sectional view of a main part of a semiconductor device of a first embodiment of the present invention and process drawings showing a manufacturing method thereof.
【図３】本発明の第２の実施例の半導体装置の主要部分
の縦断面図及びその製造方法を示す工程図である。3A and 3B are a longitudinal sectional view of a main part of a semiconductor device of a second embodiment of the present invention and a process drawing showing the manufacturing method thereof.
【図４】本発明の第３の実施例の半導体装置の主要部分
の縦断面図と部分拡大斜視図である。FIG. 4 is a longitudinal sectional view and a partially enlarged perspective view of a main part of a semiconductor device according to a third embodiment of the present invention.
【図５】従来のマルチチップ方式の半導体装置の全体図
である。FIG. 5 is an overall view of a conventional multi-chip semiconductor device.
１ Ｓｉ基板 ２、１５、１６ ＳｉＯ2膜 ３ 光導波路 ４ チップ ５ 光ファイバー ６ ボンディングワイヤ ７ リードフレーム ８ ＳｉＣ基板 ９ ムライト枠 １０ 放熱フィン １１ キャップ １２ａ ホトダイオード １２ｂ レーザーダイオード １３ はんだバンプ １４ 金属配線 １７ ポリイミド １８ ＬｉＮｂＯ3基板 １９ Ｓｉ集積回路チップ1 Si substrate 2, 15, 16 SiO 2 film 3 Optical waveguide 4 Chip 5 Optical fiber 6 Bonding wire 7 Lead frame 8 SiC substrate 9 Mullite frame 10 Heat radiation fin 11 Cap 12a Photo diode 12b Laser diode 13 Solder bump 14 Metal wiring 17 Polyimide 18 LiNbO 3 substrate 19 Si integrated circuit chip
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 23/538 25/04 25/16 Ａ 7220−4Ｍ 25/18 27/14 31/12 Ｊ 7210−4Ｍ 33/00 Ｊ 8934−4Ｍ Ｈ０１Ｓ 3/18 9170−4Ｍ Ｈ０３Ｋ 3/42 Ａ 7328−5Ｊ 8223−4Ｍ Ｈ０１Ｌ 27/14 Ｚ ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification code Office reference number FI technical display location H01L 23/538 25/04 25/16 A 7220-4M 25/18 27/14 31/12 J 7210 -4M 33/00 J 8934-4M H01S 3/18 9170-4M H03K 3/42 A 7328-5J 8223-4M H01L 27/14 Z
Claims (6)
に設けられた光電子集積回路のチップの複数個が配置さ
れ、かつ光導波路が設けられた支持基板を有し、該チッ
プは、該光素子と該光導波路とが光学的に接続する位置
に配置されたことを特徴とする半導体装置。1. A support substrate having a plurality of optoelectronic integrated circuit chips in which an electronic device integrated circuit and an optical device are provided on the same substrate, and an optical waveguide is provided, the chip comprising: A semiconductor device, wherein the optical element and the optical waveguide are arranged at a position where they are optically connected.
支持基板の光導波路の上層又は下層に、配線層を有する
ことを特徴とする半導体装置。2. The semiconductor device according to claim 1, further comprising a wiring layer above or below the optical waveguide of the supporting substrate.
配線層は上記チップの電極と電気的に接続されることを
特徴とする半導体装置。3. The semiconductor device according to claim 2, wherein the wiring layer is electrically connected to an electrode of the chip.
いて、上記支持基板は、上記光導波路の複数の層を有す
ることを特徴とする半導体装置。4. The semiconductor device according to claim 1, wherein the support substrate has a plurality of layers of the optical waveguide.
光素子とが同一基板上に設けられた光電子集積回路のチ
ップの複数個、（２）所望のパターンの光導波路及び
（３）所望のパターンの配線層が配置され、かつ、該チ
ップの光素子と該光導波路とが光学的に接続され、該チ
ップの配線と該配線層とは電気的に接続されることを特
徴とする半導体装置。5. A plurality of chips of an optoelectronic integrated circuit in which an electronic device integrated circuit and an optical device are provided on the same substrate on a supporting substrate, (2) an optical waveguide having a desired pattern, and (3) ) A wiring layer having a desired pattern is arranged, the optical element of the chip and the optical waveguide are optically connected, and the wiring of the chip and the wiring layer are electrically connected. Semiconductor device.
支持基板は、上記光導波路の複数の層を有することを特
徴とする半導体装置。6. The semiconductor device according to claim 5, wherein the supporting substrate has a plurality of layers of the optical waveguide.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20430291A JPH0548073A (en) | 1991-08-14 | 1991-08-14 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20430291A JPH0548073A (en) | 1991-08-14 | 1991-08-14 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0548073A true JPH0548073A (en) | 1993-02-26 |
Family
ID=16488234
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20430291A Pending JPH0548073A (en) | 1991-08-14 | 1991-08-14 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0548073A (en) |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07183570A (en) * | 1993-12-24 | 1995-07-21 | Nec Corp | Multichip module |
| JP2000133793A (en) * | 1998-10-27 | 2000-05-12 | Sony Corp | Light transmission path and method of forming the same |
| JP2000188418A (en) * | 1998-10-13 | 2000-07-04 | Sony Corp | Optoelectronic integrated circuit device |
| JP2002009379A (en) * | 2000-06-19 | 2002-01-11 | Sony Corp | Optical wiring module and method for manufacturing the same |
| WO2002086972A1 (en) * | 2001-04-23 | 2002-10-31 | Plasma Ireland Limited | Illuminator |
| EP1605525A2 (en) * | 2004-06-10 | 2005-12-14 | LG Electronics Inc. | High power LED package |
| JP2007079283A (en) * | 2005-09-15 | 2007-03-29 | Sony Corp | Optical integrated circuit |
| WO2011129415A1 (en) * | 2010-04-15 | 2011-10-20 | 株式会社リキッド・デザイン・システムズ | Three-dimensional led substrate and led lighting device |
| JP2012199259A (en) * | 2012-07-27 | 2012-10-18 | Liquid Design Systems:Kk | Led lighting system |
| WO2013191175A1 (en) * | 2012-06-19 | 2013-12-27 | 住友ベークライト株式会社 | Optical waveguide, optical interconnection component, optical module, opto-electric hybrid board, and electronic device |
| JP2014026268A (en) * | 2012-06-19 | 2014-02-06 | Sumitomo Bakelite Co Ltd | Optical waveguide, optical wiring component, optical module, photoelectric hybrid board, and electronic apparatus |
| US9720171B2 (en) | 2012-06-19 | 2017-08-01 | Sumitomo Bakelite Co., Ltd. | Optical waveguide, optical interconnection component, optical module, opto-electric hybrid board, and electronic device |
-
1991
- 1991-08-14 JP JP20430291A patent/JPH0548073A/en active Pending
Cited By (21)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07183570A (en) * | 1993-12-24 | 1995-07-21 | Nec Corp | Multichip module |
| JP2000188418A (en) * | 1998-10-13 | 2000-07-04 | Sony Corp | Optoelectronic integrated circuit device |
| JP4529194B2 (en) * | 1998-10-13 | 2010-08-25 | ソニー株式会社 | Optoelectronic integrated circuit device |
| JP2000133793A (en) * | 1998-10-27 | 2000-05-12 | Sony Corp | Light transmission path and method of forming the same |
| JP4529193B2 (en) * | 1998-10-27 | 2010-08-25 | ソニー株式会社 | Method for forming optical transmission line |
| JP4517461B2 (en) * | 2000-06-19 | 2010-08-04 | ソニー株式会社 | Manufacturing method of optical wiring module |
| JP2002009379A (en) * | 2000-06-19 | 2002-01-11 | Sony Corp | Optical wiring module and method for manufacturing the same |
| WO2002086972A1 (en) * | 2001-04-23 | 2002-10-31 | Plasma Ireland Limited | Illuminator |
| US6995405B2 (en) | 2001-04-23 | 2006-02-07 | Plasma Ireland Limited | Illuminator |
| EP1605525A2 (en) * | 2004-06-10 | 2005-12-14 | LG Electronics Inc. | High power LED package |
| EP1605525A3 (en) * | 2004-06-10 | 2006-10-04 | LG Electronics Inc. | High power LED package |
| JP2007079283A (en) * | 2005-09-15 | 2007-03-29 | Sony Corp | Optical integrated circuit |
| WO2011129415A1 (en) * | 2010-04-15 | 2011-10-20 | 株式会社リキッド・デザイン・システムズ | Three-dimensional led substrate and led lighting device |
| JP2011228367A (en) * | 2010-04-15 | 2011-11-10 | Liquid Design Systems Inc | Three dimensional (3d) light emitting diode (led) substrate and led luminaire |
| CN102844898A (en) * | 2010-04-15 | 2012-12-26 | 株式会社理技独设计系统 | Three-dimensional led substrate and led lighting device |
| US8610141B2 (en) | 2010-04-15 | 2013-12-17 | Liquid Design Systems, Inc. | Three-dimensional LED substrate and LED lighting device |
| CN103925492A (en) * | 2010-04-15 | 2014-07-16 | 株式会社理技独设计系统 | Led Lighting Device |
| WO2013191175A1 (en) * | 2012-06-19 | 2013-12-27 | 住友ベークライト株式会社 | Optical waveguide, optical interconnection component, optical module, opto-electric hybrid board, and electronic device |
| JP2014026268A (en) * | 2012-06-19 | 2014-02-06 | Sumitomo Bakelite Co Ltd | Optical waveguide, optical wiring component, optical module, photoelectric hybrid board, and electronic apparatus |
| US9720171B2 (en) | 2012-06-19 | 2017-08-01 | Sumitomo Bakelite Co., Ltd. | Optical waveguide, optical interconnection component, optical module, opto-electric hybrid board, and electronic device |
| JP2012199259A (en) * | 2012-07-27 | 2012-10-18 | Liquid Design Systems:Kk | Led lighting system |
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