JPH0547994B2 - - Google Patents
Info
- Publication number
- JPH0547994B2 JPH0547994B2 JP7821883A JP7821883A JPH0547994B2 JP H0547994 B2 JPH0547994 B2 JP H0547994B2 JP 7821883 A JP7821883 A JP 7821883A JP 7821883 A JP7821883 A JP 7821883A JP H0547994 B2 JPH0547994 B2 JP H0547994B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- cdse
- chromium
- thin film
- film transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000010408 film Substances 0.000 claims description 44
- UHYPYGJEEGLRJD-UHFFFAOYSA-N cadmium(2+);selenium(2-) Chemical compound [Se-2].[Cd+2] UHYPYGJEEGLRJD-UHFFFAOYSA-N 0.000 claims description 37
- 239000011651 chromium Substances 0.000 claims description 36
- 229910052804 chromium Inorganic materials 0.000 claims description 27
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims description 26
- 239000010409 thin film Substances 0.000 claims description 22
- 239000004065 semiconductor Substances 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 4
- 230000002123 temporal effect Effects 0.000 description 6
- 230000000694 effects Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000000137 annealing Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78681—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising AIIIBV or AIIBVI or AIVBVI semiconductor materials, or Se or Te
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thin Film Transistor (AREA)
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は、薄膜トランジスタ、特に半導体膜と
してセレン化カドミウム膜（以下、CdSe膜と称
する）を用いた薄膜トランジスタに関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a thin film transistor, and particularly to a thin film transistor using a cadmium selenide film (hereinafter referred to as a CdSe film) as a semiconductor film.
従来、CdSe薄膜トランジスタとしては種々の
構造のものがあるが、その基本構造は、絶縁基板
上に形成される半導体膜としてのCdSe膜と、こ
のCdSe膜に対し所定の間隔をおいて形成される
ソースおよびドレイン電極と、このソース、ドレ
イン電極間にゲート絶縁膜を介して形成されるゲ
ート電極とから構成されている。
Conventionally, CdSe thin film transistors have various structures, but their basic structure is a CdSe film as a semiconductor film formed on an insulating substrate, and a source formed at a predetermined distance from this CdSe film. and a drain electrode, and a gate electrode formed between the source and drain electrodes with a gate insulating film interposed therebetween.
しかしながら、このような従来のCdSe薄膜ト
ランジスタでは、CdSeの膜中に高密度の電荷ト
ラツピング準位が存在するために、キヤリヤ移動
度が実効的に小さくなり、相互コンダクタンスが
小さくなつたり、ドレイン電流の時間的減衰が大
きくなつたりして、素子の特性が損なわれるとい
う問題があつた。 However, in such conventional CdSe thin film transistors, due to the presence of a high density of charge trapping levels in the CdSe film, the effective carrier mobility becomes small, the mutual conductance becomes small, and the drain current time increases. There was a problem in that the optical attenuation increased and the characteristics of the element were impaired.
本発明は以上の点に鑑みてなされたもので、そ
の目的は、CdSe膜中に所定量のクロム（Cr）を
含有させることにより、そのCdSe膜中の電荷ト
ラツピング準位を減少せしめてCdSe薄膜トラン
ジスタにおけるドレイン電流の時間的減衰を低減
するとともに、相互コンダクタンスを増大させる
ことにある。
The present invention has been made in view of the above points, and its purpose is to reduce the charge trapping level in the CdSe film by containing a predetermined amount of chromium (Cr) in the CdSe film, thereby improving the CdSe thin film transistor. The object of the invention is to reduce the temporal attenuation of the drain current and increase the mutual conductance.
すなわち、本発明は、クロムがCdSe膜に対し
ｎ型の不純物として作用することに着目し、
CdSe膜に生じる電荷トラツピング準位を埋め尽
くすに足りる量のクロムをCdSe膜中に含有させ
ることにより、ドレイン電流の時間的な減衰を少
なくし、しかもキヤリア移動度を実効的に大きく
することのできる薄膜トランジスタを提供するも
のである。以下、図面を用いて本発明の実施例を
説明する。 That is, the present invention focuses on the fact that chromium acts as an n-type impurity on the CdSe film,
By incorporating enough chromium into the CdSe film to fill the charge trapping levels generated in the CdSe film, it is possible to reduce the temporal decay of drain current and effectively increase carrier mobility. The present invention provides a thin film transistor. Embodiments of the present invention will be described below with reference to the drawings.
第１図は本発明の一実施例による薄膜トランジ
スタの基本的な断面図であり、ガラスよりなる絶
縁基板１上にはＡからなるゲート電極２が形成
されるとともに、このゲート電極２を含む全面に
Ａ2O3からなるゲート絶縁膜３が形成されてい
る。そして、このゲート絶縁膜３上の前記ゲート
電極２と対向する部分には半導体膜としての
CdSe膜４が所定の大きさを有して形成され、さ
らに、このCdSe膜４上には前記ゲート電極２に
相当する間隔をおいてクロムからなるソースおよ
びドレイン電極５，６が形成されているもので、
構造的には従来と同様のものである。
FIG. 1 is a basic cross-sectional view of a thin film transistor according to an embodiment of the present invention, in which a gate electrode 2 made of A is formed on an insulating substrate 1 made of glass, and the entire surface including this gate electrode 2 is A gate insulating film 3 made of A 2 O 3 is formed. A semiconductor film is formed on the gate insulating film 3 in a portion facing the gate electrode 2.
A CdSe film 4 is formed to have a predetermined size, and source and drain electrodes 5 and 6 made of chromium are further formed on this CdSe film 4 at intervals corresponding to the gate electrode 2. Something,
Structurally, it is the same as the conventional one.
すなわち、本発明では、第１図に示す構造の薄
膜トランジスタにおいてそのCdSe膜４にクロム
を含有させる際に、上記目的を達成し得るに足り
るクロムの最適量を見出したもので、その考案結
果について述べる。前記CdSe膜４中へのクロム
の導入量は、クロムよりなるソースおよびドレイ
ン電極５，６を備えた上記薄膜トランジスタを雰
囲気および温度を変えてアニールすることによ
り、制御した。第２図はCdSe膜４中のクロム
（Cr）の濃度と薄膜トランジスタのドレイン電流
の時間的減衰の関係を示し、横軸に時間（Ｔ）
を、縦軸にドレイン電流（ID）をとつてある。ク
ロムを含有しないかあるいはその量が1at.％未満
のCdSe膜を用いた薄膜トランジスタにおいては、
第２図の特性１０（Cr＜1at.％の代表例としてCr
＝0.8at.％を記載）に示すように、ドレイン電流
の減少が著しく、Cr量を０〜0.8at.％の間で変化
させた数点の特性も略特性１０に類似のものであ
つた。これに対して、CdSe膜４中に、含有量と
して１〜3at.％のクロムを含有させた薄膜トラン
ジスタでは、第２図の特性１１（Cr＝１〜3at.％
の代表例としてCr＝2.8at.％を記載）に示すよう
に、ドレイン電流の時間的減少は僅かで十分に実
用出来得る特性であつた。なお、クロム量が3at.
％を越えると本特性は徐々に低下することが認め
られた。 That is, in the present invention, when incorporating chromium into the CdSe film 4 of the thin film transistor having the structure shown in FIG. . The amount of chromium introduced into the CdSe film 4 was controlled by annealing the thin film transistor provided with source and drain electrodes 5 and 6 made of chromium under different atmospheres and temperatures. Figure 2 shows the relationship between the concentration of chromium (Cr) in the CdSe film 4 and the temporal attenuation of the drain current of a thin film transistor, with the horizontal axis representing time (T).
, and the drain current (I D ) is plotted on the vertical axis. In thin film transistors using CdSe films that do not contain chromium or contain less than 1 at.%,
Characteristic 10 in Figure 2 (Cr
= 0.8 at.%), the drain current decreased significantly, and the characteristics at several points where the Cr content was varied between 0 and 0.8 at.% were also approximately similar to characteristic 10. . On the other hand, in a thin film transistor in which the CdSe film 4 contains 1 to 3 at.% chromium, characteristic 11 (Cr=1 to 3 at.%) shown in FIG.
As shown in Cr = 2.8 at.% as a representative example), the temporal decrease in drain current was small and was sufficient for practical use. In addition, the amount of chromium is 3at.
%, this property was found to gradually deteriorate.
また、第３図乃至第５図はCdSe膜中のクロム
濃度に対する薄膜トランジスタのドレイン電圧
（VD）に対するドレイン電流（ID）の特性をゲー
トバイアスVGをパラメータとして示すもので、
横軸にドレイン電圧（VD）が、縦軸にドレイン
電流（ID）がとつてある。第３図はCdSe膜のク
ロム含有量が1at.％未満のとき（Cr＜1at.％の代
表例としてCr＝0.8at.％を記載）のゲートバイア
スVGが20V（VG1）と0V（VG2）に対するVD−ID特
性を示し、VG2，VG1それぞれに対するIDの比即ち
電流のオン／オフ比が小さいため、良好なトラン
ジスタ特性でないことが確認できる。次に、第４
図はCdSe膜のクロム含有量が１〜3at.％のとき
（Cr＝１〜3at.％の代表例としてCr＝2.8at.％を記
載）の第３図と同様の特性を示すもので、VG2，
VG1それぞれに対するIDの比即ち電流のオン／オ
フ比が十分に大きく、良好なトランジスタ特性が
得られていることが確認できる。なお、CdSe膜
のクロム含有量が１〜3at.％のときには略第４図
に近い特性となるが、クロム含有量が3at.％を越
えるにつれてリーク電流（VG2のときのID）の増
加傾向が認められた。 Furthermore, FIGS. 3 to 5 show the characteristics of the drain current (I D ) with respect to the drain voltage (V D ) of the thin film transistor with respect to the chromium concentration in the CdSe film, using the gate bias V G as a parameter.
The horizontal axis shows the drain voltage (V D ), and the vertical axis shows the drain current (I D ). Figure 3 shows that the gate bias V G is 20 V (V G1 ) and 0 V ( It can be confirmed that the transistor characteristics are not good because the ratio of ID to each of V G2 and V G1 , that is, the on/off ratio of the current is small. Next, the fourth
The figure shows the same characteristics as in Figure 3 when the chromium content of the CdSe film is 1 to 3 at.% (Cr = 2.8 at.% is shown as a typical example of Cr = 1 to 3 at.%). V G2 ,
It can be confirmed that the ratio of ID to each of V G1 , that is, the on/off ratio of current, is sufficiently large, and good transistor characteristics are obtained. Note that when the chromium content of the CdSe film is 1 to 3 at.%, the characteristics are approximately similar to those shown in Figure 4, but as the chromium content exceeds 3 at.%, the leakage current (I D at V G2 ) increases. A trend was observed.
また、第５図はCdSe膜のクロム含有量が5at.
％以上のとき（Cr＞5at.％の代表例としてCr＝
5.6at.％を記載）の第３図、第４図と同様の特性
を示すもので、リーク電流（VG2のときのID）が
VG1のときのIDに略等しくなる即ちオフ特性が得
られないことが確認できる。これら素子の相互コ
ンダクタンスは、CdSe膜へのクロムの含有量が
適量である場合（第４図参照）、クロムを含有し
ないかもしくはその量が1at.％未満のもの（第３
図参照）に比べて相当の改善がなされていること
がわかる。しかし、CdSe膜中へのクロムが過剰
である場合は、相互コンダクタンスは零となり、
増幅作用を持たなくなる。 Also, Figure 5 shows that the chromium content of the CdSe film is 5at.
% or more (as a typical example of Cr>5at.%, Cr=
5.6at.%) shows the same characteristics as Figures 3 and 4, and the leakage current (I D at V G2 ) is
It can be confirmed that the voltage is approximately equal to ID at V G1 , that is, an off characteristic cannot be obtained. The mutual conductance of these elements is as follows: when the content of chromium in the CdSe film is appropriate (see Figure 4), when the CdSe film does not contain chromium or when the amount of chromium is less than 1 at.
It can be seen that a considerable improvement has been made compared to the previous version (see figure). However, if there is too much chromium in the CdSe film, the mutual conductance becomes zero,
It no longer has an amplifying effect.
以上のことから、薄膜トランジスタを作製する
にあたつて、CdSe膜中へのクロム含有量の最小
制御量および含有量の検出精度はそれぞれ約
0.5at.％，0.2at.％程度であつたので、再現可能性
並びに前記特性よりCdSe膜中へのクロム含有量
は１〜5at.％が最適であると判断した。なお、薄
膜トランジスタの構造は、上記実施例以外のもの
であつても、同様に適用できることはいうまでも
ない。 From the above, when manufacturing thin film transistors, the minimum control amount of chromium content in the CdSe film and the detection accuracy of the content are approximately
Since the values were approximately 0.5 at.% and 0.2 at.%, it was determined that the optimum chromium content in the CdSe film was 1 to 5 at.% based on reproducibility and the above characteristics. Note that it goes without saying that structures of thin film transistors other than those of the above-mentioned embodiments can also be applied in the same manner.
以上説明したように、本発明によれば、CdSe
膜中に１〜5at.％のクロムを含有させることによ
り、CdSe薄膜トランジスタにおけるドレイン電
流の時間的減衰を低減できるとともに、相互コン
ダクタンスを増大させることができ、したがつ
て、特性の安定した良好な薄膜トランジスタが得
られる効果がある。
As explained above, according to the present invention, CdSe
By containing 1 to 5 at.% chromium in the film, it is possible to reduce the temporal attenuation of the drain current in a CdSe thin film transistor, and to increase the mutual conductance, resulting in a good thin film transistor with stable characteristics. There is an effect that can be obtained.
第１図は本発明の一実施例による薄膜トランジ
スタの構造を示す断面図、第２図は第１図の
CdSe膜へのクロムの濃度と薄膜トランジスタの
ドレイン電流の時間的減衰の関係を示す特性図、
第３図乃至第５図はCdSe膜中のクロム濃度と薄
膜トランジスタのドレイン電圧・ドレイン電流特
性との関係を示す特性図である。
１……絶縁基板、２……ゲート電極、３……ゲ
ート絶縁膜、４……CdSe膜、５……ソース電極、
６……ドレイン電極。
FIG. 1 is a cross-sectional view showing the structure of a thin film transistor according to an embodiment of the present invention, and FIG.
Characteristic diagram showing the relationship between the concentration of chromium in the CdSe film and the temporal decay of the drain current of a thin film transistor,
3 to 5 are characteristic diagrams showing the relationship between the chromium concentration in the CdSe film and the drain voltage/drain current characteristics of the thin film transistor. 1... Insulating substrate, 2... Gate electrode, 3... Gate insulating film, 4... CdSe film, 5... Source electrode,
6...Drain electrode.
Claims (1)
導体膜に対し所定の間隔をおいて形成されるソー
スおよびドレイン電極と、このソース、ドレイン
電極間にゲート絶縁膜を介して形成されるゲート
電極とを備え、前記半導体膜としてセレン化カド
ミウム膜を用いてなる薄膜トランジスタにおい
て、前記セレン化カドミウム膜に１〜5at.％のク
ロムを含有させることにより、前記セレン化カド
ミウム膜に生じる電荷トラツピング準位を埋めつ
くしたことを特徴とする薄膜トランジスタ。1. A semiconductor film formed on an insulating substrate, a source and drain electrode formed at a predetermined distance from the semiconductor film, and a gate electrode formed between the source and drain electrodes with a gate insulating film interposed therebetween. In a thin film transistor using a cadmium selenide film as the semiconductor film, the charge trapping level generated in the cadmium selenide film is reduced by containing 1 to 5 at.% chromium in the cadmium selenide film. A thin film transistor characterized by being completely filled.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7821883A JPS59204273A (en) | 1983-05-06 | 1983-05-06 | Thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7821883A JPS59204273A (en) | 1983-05-06 | 1983-05-06 | Thin film transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59204273A JPS59204273A (en) | 1984-11-19 |
| JPH0547994B2 true JPH0547994B2 (en) | 1993-07-20 |
Family
ID=13655904
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7821883A Granted JPS59204273A (en) | 1983-05-06 | 1983-05-06 | Thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59204273A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1560691B (en) * | 1992-08-27 | 2010-05-26 | 株式会社半导体能源研究所 | Semiconductor device and its manufacture method and active matrix display |
| TWI221341B (en) * | 2003-09-18 | 2004-09-21 | Ind Tech Res Inst | Method and material for forming active layer of thin film transistor |
-
1983
- 1983-05-06 JP JP7821883A patent/JPS59204273A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59204273A (en) | 1984-11-19 |
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