JPH0547833A - Substrate for mounting tab chip - Google Patents

Substrate for mounting tab chip

Info

Publication number
JPH0547833A
JPH0547833A JP20167491A JP20167491A JPH0547833A JP H0547833 A JPH0547833 A JP H0547833A JP 20167491 A JP20167491 A JP 20167491A JP 20167491 A JP20167491 A JP 20167491A JP H0547833 A JPH0547833 A JP H0547833A
Authority
JP
Japan
Prior art keywords
leads
substrate
electrode parts
electrode
parts
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20167491A
Other languages
Japanese (ja)
Inventor
Yasuto Onizuka
安登 鬼塚
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP20167491A priority Critical patent/JPH0547833A/en
Publication of JPH0547833A publication Critical patent/JPH0547833A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10152—Auxiliary members for bump connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/10165—Alignment aids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/81138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • H01L2224/8114—Guiding structures outside the body
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3421—Leaded components

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE:To push leads against the electrode parts by suitably push-up force of a thermocompression bonder in order to obtain good bonding by saliently providing spacers controlling a fall limit of the thermocompression bonder near the electrode parts of a substrate. CONSTITUTION:Spacers 5 are saliently provided on the corner parts near the electrode parts 2 of a substrate 1. A height of a spacer 5 is to be slightly higher than that of an electrode part 2 while being equal or almost equal to that of a lead L to be bonded on the electrode part 2. In order to bond the leads L, the leads L are matched with the electrode parts 2 so as to make the leads L to land on the electrode parts 2, next, a thermocompression bonder 13 is made to fall so as to press the leads L on the electrode parts 2 for being heat- deposited. In this case, the fall limit of the thermocompression bonder 13 is controlled by the spacers 5 so as to prevent the leads L from sliding down from solder parts 4 while being pressed against the electrode parts 2 with suitable force for being bonded thus to dissolve extrusion of solder due to excessive press force.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明はＴＡＢチップの搭載用基
板に係り、詳しくは、ＴＡＢチップのリードを基板の電
極部に確実にボンディングできる基板の構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a substrate for mounting a TAB chip, and more particularly to a structure of a substrate capable of surely bonding a lead of the TAB chip to an electrode portion of the substrate.

【０００２】[0002]

【従来の技術】合成樹脂から成るフィルムキャリヤに半
導体チップをボンディングし、次いでフィルムキャリヤ
のリード部を打抜き装置により打抜いてデバイスを得る
ことは、ＴＡＢ法として知られている。2. Description of the Related Art It is known as a TAB method to bond a semiconductor chip to a film carrier made of a synthetic resin and then punch the lead portion of the film carrier with a punching device to obtain a device.

【０００３】図３及び図４は、ＴＡＢ法により製造され
たデバイス（ＴＡＢチップ）を、従来の基板に搭載して
いる様子を示している。図中、１は基板であり、その上
面には電極部２が形成されている。図４に示すように、
この電極部２は、基板１の上面に銅エッチング手段など
により回路パターン３を形成し、この回路パターン３上
に半田部４を半田レベラ手段などにより積層して形成さ
れている。3 and 4 show a state in which a device (TAB chip) manufactured by the TAB method is mounted on a conventional substrate. In the figure, 1 is a substrate, and an electrode portion 2 is formed on the upper surface thereof. As shown in FIG.
The electrode portion 2 is formed by forming a circuit pattern 3 on the upper surface of the substrate 1 by a copper etching means or the like, and laminating a solder portion 4 on the circuit pattern 3 by a solder leveler means or the like.

【０００４】１１はボンディングヘッドであって、ＴＡ
ＢチップＰを吸着するノズル１２と、ＴＡＢチップＰの
リードＬを電極部２に押し付けて熱圧着する熱圧着子１
３を備えている。上述のように、このリードＬはフィル
ムキャリヤを打抜いて形成されたものである。A bonding head 11 is a TA
A thermocompression bonding element 1 that presses the nozzle 12 for adsorbing the B chip P and the lead L of the TAB chip P against the electrode portion 2 and thermocompression bonding
Equipped with 3. As described above, the lead L is formed by punching the film carrier.

【０００５】ボンディングを行うにあたっては、リード
Ｌと電極部２をマッチングさせて、リードＬを電極部２
上に着地させ、次いで熱圧着子１３を下降させて、リー
ドＬを電極部２に押し付け、熱溶着する。In performing the bonding, the lead L and the electrode portion 2 are matched with each other, and the lead L is connected to the electrode portion 2.
It is landed on the top, and then the thermocompressor 13 is lowered to press the lead L against the electrode portion 2 and heat-welding.

【０００６】この場合、熱圧着子１３の押し付け力が過
小であると、リードＬは電極部２に溶着されず、ボンデ
ィング不良となる。また押し付け力が過大であると、図
４鎖線に示すように、この過大な押し付け力のために、
リードＬは電極部２に溶着される前にこれから滑り落
ち、ボンディング不良となる。殊に半田部４の形状は、
図示するように一般にかまぼこ状であるので、リードＬ
は滑り落ちやすいものである。更にこの場合、半田部４
に熱圧着子１３が過度に押し付けられる結果、溶融した
半田が側方へはみ出し、このはみ出し半田４ａにより電
極部２と電極部２が短絡してしまう問題点があった。In this case, if the pressing force of the thermocompression-bonding element 13 is too small, the lead L will not be welded to the electrode portion 2, resulting in defective bonding. When the pressing force is excessive, as shown by the chain line in FIG. 4, due to the excessive pressing force,
The lead L slips off from the electrode portion 2 before being welded to the electrode portion 2, resulting in defective bonding. Especially, the shape of the solder part 4 is
As shown in the figure, the lead L
Is slippery. Further, in this case, the solder portion 4
As a result of the thermocompression bonding element 13 being excessively pressed against the surface, the melted solder sticks out laterally, and this sticking-out solder 4a causes a short circuit between the electrode portions 2 and 2.

【０００７】したがって本発明は、上記従来の問題点を
解消できる手段を提供することを目的とする。Therefore, an object of the present invention is to provide means for solving the above conventional problems.

【０００８】[0008]

【課題を解決するための手段】このために本発明は、基
板の電極部の近傍に、熱圧着子の下降限度を規制するス
ペーサを突設したものである。To this end, the present invention is provided with a spacer projecting in the vicinity of the electrode portion of the substrate for restricting the lowering limit of the thermocompressor.

【０００９】[0009]

【作用】上記構成によれば、熱圧着子の下降限度はスペ
ーサにより規制されることから、適度の押し付け力でリ
ードを電極部に押し付けて良好にボンディングできる。According to the above construction, since the lower limit of the thermocompression-bonding member is regulated by the spacer, the lead can be pressed against the electrode portion with an appropriate pressing force to perform good bonding.

【００１０】[0010]

【実施例】次に、図面を参照しながら本発明の実施例を
説明する。Embodiments of the present invention will now be described with reference to the drawings.

【００１１】図１は基板の斜視図である。この基板１
は、上記従来の基板１と同構造であるが、電極部２の近
傍のコーナー部にスペーサ５を突設している点が相違し
ている。このスペーサ５の形成方法は任意であって、例
えば回路パターン３と一緒にエッチング手段により形成
してもよく、あるいは回路パターン３とは別途に形成し
てもよい。FIG. 1 is a perspective view of the substrate. This board 1
Has the same structure as the conventional substrate 1 described above, but is different in that a spacer 5 is projectingly provided at a corner portion near the electrode portion 2. The spacer 5 may be formed by any method, for example, it may be formed together with the circuit pattern 3 by an etching means, or may be formed separately from the circuit pattern 3.

【００１２】図２に示すように、このスペーサ５の高さ
は、電極部２の高さよりもわずかに高く、この電極部２
上にボンディングされるリードＬの高さと同高若しくは
略同高になっている。As shown in FIG. 2, the height of the spacer 5 is slightly higher than the height of the electrode portion 2.
The height is the same as or substantially the same as the height of the lead L to be bonded thereon.

【００１３】リードＬのボンディングは、図３に示す従
来手段と同様に行われる。すなわち、リードＬと電極部
２をマッチングさせて、リードＬを電極部２上に着地さ
せ、次いで熱圧着子１３を下降させて、リードＬを電極
部２に押し付け、熱溶着する。Bonding of the lead L is performed in the same manner as the conventional means shown in FIG. That is, the lead L and the electrode portion 2 are matched with each other, the lead L is landed on the electrode portion 2, and then the thermocompression bonding element 13 is lowered to press the lead L onto the electrode portion 2 for heat welding.

【００１４】この場合、熱圧着子１３の下降限度はスペ
ーサ５により規制され、リードＬは半田部４から滑り落
ちることなく適度の力で電極部２に押し付けられてボン
ディングされ、また上述したような過大な押し付け力に
よる半田のはみ出しも解消できる。また半田部４は厚さ
のばらつきがあるが、本手段によれば、すべての半田部
４の高さが同一になるようにレベリングでき、しかもボ
ンディング後の半田部４の厚さが所定厚さになるよう
に、スペーサ５の高さを設定することも可能である。In this case, the lower limit of the thermocompression-bonding element 13 is regulated by the spacer 5, and the lead L is pressed against the electrode portion 2 with a proper force without being slipped off from the solder portion 4 to be bonded, or is excessive as described above. It is also possible to eliminate solder squeeze out due to the pressing force. Further, although the solder portions 4 have variations in thickness, according to this means, it is possible to perform leveling so that all the solder portions 4 have the same height, and the solder portions 4 after bonding have a predetermined thickness. It is also possible to set the height of the spacer 5 so that

【００１５】[0015]

【発明の効果】以上説明したように本発明は、基板の電
極部の近傍に、熱圧着子の下降限度を規制するスペーサ
を突設しているので、ボンディング中にリードが半田部
から滑り落ちることはなく、適度の押し付け力で良好に
ボンディングすることができ、また半田部の厚さのばら
つきを吸収して、すべての半田部の高さが同一になるよ
うにレベリングでき、しかもボンディング後の半田部の
厚さが所定厚さになるように設定することも可能とな
る。As described above, according to the present invention, since the spacer for restricting the lowering limit of the thermocompressor is provided in the vicinity of the electrode portion of the substrate, the lead does not slip off from the solder portion during bonding. Instead, good bonding can be performed with an appropriate pressing force, leveling can be performed so that all solder parts have the same height by absorbing the variation in the thickness of the solder part. It is also possible to set the thickness of the portion to be a predetermined thickness.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明に係る基板の斜視図FIG. 1 is a perspective view of a substrate according to the present invention.

【図２】本発明に係るボンディング中の正面図FIG. 2 is a front view during bonding according to the present invention.

【図３】従来手段のボンディング中の斜視図FIG. 3 is a perspective view of the conventional means during bonding.

【図４】従来手段のボンディング中の正面図FIG. 4 is a front view of the conventional means during bonding.

【符号の説明】[Explanation of symbols]

１ 基板 ２ 電極部 ３ 回路パターン ４ 半田部 ５ スペーサ １３ 熱圧着子 1 substrate 2 electrode part 3 circuit pattern 4 solder part 5 spacer 13 thermocompressor

Claims (1)

【特許請求の範囲】[Claims] 【請求項１】回路パターン上に半田部を積層して形成さ
れた電極部の近傍に、熱圧着子の下降限度を規制するス
ペーサを突設したことを特徴とするＴＡＢチップの搭載
用基板。1. A substrate for mounting a TAB chip, characterized in that a spacer for restricting a lowering limit of a thermocompression-bonding member is provided in the vicinity of an electrode portion formed by laminating a solder portion on a circuit pattern.
JP20167491A 1991-08-12 1991-08-12 Substrate for mounting tab chip Pending JPH0547833A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20167491A JPH0547833A (en) 1991-08-12 1991-08-12 Substrate for mounting tab chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20167491A JPH0547833A (en) 1991-08-12 1991-08-12 Substrate for mounting tab chip

Publications (1)

Publication Number Publication Date
JPH0547833A true JPH0547833A (en) 1993-02-26

Family

ID=16445022

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20167491A Pending JPH0547833A (en) 1991-08-12 1991-08-12 Substrate for mounting tab chip

Country Status (1)

Country Link
JP (1) JPH0547833A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07235566A (en) * 1994-02-22 1995-09-05 Nec Corp Mounting structure of optical element
US5666332A (en) * 1995-06-09 1997-09-09 Sharp Kabushiki Kaisha Magneto-optical recording medium permitting an initializing magnetic field smaller than a recording magnetic field, and method of recording there on
US5724630A (en) * 1995-03-06 1998-03-03 Sharp Kabushiki Kaisha Image forming apparatus with standby temperature control of thermal fixing
JP2010146411A (en) * 2008-12-19 2010-07-01 Toshiba Corp Method for manufacturing inlet and inlet manufactured by the method
JP2011240007A (en) * 2010-05-20 2011-12-01 Hitachi Aloka Medical Ltd Ultrasonic probe and method for manufacturing the ultrasonic probe

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07235566A (en) * 1994-02-22 1995-09-05 Nec Corp Mounting structure of optical element
US5724630A (en) * 1995-03-06 1998-03-03 Sharp Kabushiki Kaisha Image forming apparatus with standby temperature control of thermal fixing
US5666332A (en) * 1995-06-09 1997-09-09 Sharp Kabushiki Kaisha Magneto-optical recording medium permitting an initializing magnetic field smaller than a recording magnetic field, and method of recording there on
JP2010146411A (en) * 2008-12-19 2010-07-01 Toshiba Corp Method for manufacturing inlet and inlet manufactured by the method
JP2011240007A (en) * 2010-05-20 2011-12-01 Hitachi Aloka Medical Ltd Ultrasonic probe and method for manufacturing the ultrasonic probe

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