JP3055285B2 - Intermediate substrate bonding method - Google Patents

Intermediate substrate bonding method

Info

Publication number
JP3055285B2
JP3055285B2 JP4013801A JP1380192A JP3055285B2 JP 3055285 B2 JP3055285 B2 JP 3055285B2 JP 4013801 A JP4013801 A JP 4013801A JP 1380192 A JP1380192 A JP 1380192A JP 3055285 B2 JP3055285 B2 JP 3055285B2
Authority
JP
Japan
Prior art keywords
electrode
spacer
substrate
intermediate substrate
wire
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP4013801A
Other languages
Japanese (ja)
Other versions
JPH05206357A (en
Inventor
賢秀 小山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Panasonic Holdings Corp
Original Assignee
Panasonic Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Corp, Matsushita Electric Industrial Co Ltd filed Critical Panasonic Corp
Priority to JP4013801A priority Critical patent/JP3055285B2/en
Publication of JPH05206357A publication Critical patent/JPH05206357A/en
Application granted granted Critical
Publication of JP3055285B2 publication Critical patent/JP3055285B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01004Beryllium [Be]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3431Leadless components

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は中間基材のボンディング
方法に係り、詳しくは、中間基材の電極にワイヤボンデ
ィング手段により半田部の高さを規定するスペーサを形
成し、このスペーサを基板の電極に着地させてボンディ
ングするようにしたものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of bonding an intermediate substrate, and more particularly, to a method of forming a spacer for defining the height of a solder portion on an electrode of an intermediate substrate by means of wire bonding means. The electrode is landed and bonded.

【0002】[0002]

【従来の技術】ICやLSIなどの電子部品に使用され
る半導体チップ(以下、単にチップという)の電極は、
高集積化の要請から、近年、益々多数化且つ狭ピッチ化
しており、チップによっては、電極の数は数100以上
にも達することから、チップの電極を基板の電極に合致
させてボンディングすることは、次第に困難になってき
ている。このような問題点を解決するために、チップを
プレート状の中間基材を介して、基板にボンディングす
ることが知られている。
2. Description of the Related Art Electrodes of a semiconductor chip (hereinafter, simply referred to as a chip) used for electronic components such as ICs and LSIs are:
In recent years, due to the demand for high integration, the number of electrodes has been increasing and the pitch has become narrower. Depending on the chip, the number of electrodes can reach several hundred or more. Is becoming increasingly difficult. In order to solve such a problem, it has been known to bond a chip to a substrate via a plate-like intermediate substrate.

【0003】図12はその従来手段を示すものであっ
て、1はチップであり、このチップ1の下面の電極4
は、中間基材2の上面の第1の電極5に、ワイヤボンデ
ィング手段により形成されたバンプ8aおよびクリーム
半田8bを介してボンディングされている。また、この
中間基材2の下面にマトリクス状に形成された第2の電
極6は、基板3の上面にマトリクス状に形成された電極
7に、バンプ9aおよびクリーム半田9bを介してボン
ディングされている。また中間基材2の上面の電極5と
下面の電極6は、導電材19により接続されている。
FIG. 12 shows the conventional means, in which 1 is a chip, and an electrode 4 on the lower surface of the chip 1 is shown.
Are bonded to the first electrode 5 on the upper surface of the intermediate substrate 2 via bumps 8a and cream solder 8b formed by wire bonding means. The second electrodes 6 formed in a matrix on the lower surface of the intermediate substrate 2 are bonded to the electrodes 7 formed in a matrix on the upper surface of the substrate 3 via bumps 9a and cream solder 9b. I have. The electrode 5 on the upper surface and the electrode 6 on the lower surface of the intermediate substrate 2 are connected by a conductive material 19.

【0004】この中間基材2の基板3へのボンディング
は、バンプ9aをクリーム半田9bが塗布された電極7
に着地させ、次いでバンプ9aおよびクリーム半田9b
をリフローにより加熱溶融することにより行われる。
[0004] The bonding of the intermediate substrate 2 to the substrate 3 is performed by forming bumps 9a on electrodes 7 coated with cream solder 9b.
And then bump 9a and cream solder 9b
Is heated and melted by reflow.

【0005】ところでバンプ9aおよびクリーム半田9
bは、電極6,7間の接合が良好なように比較的多量に
使用されている。このため、バンプ9aとクリーム半田
9bは、加熱溶融されて一体化し、図13の実線に示す
ように外凸状に膨出する略球形の半田部9になりやす
い。しかしながらこのような外凸状では、半田部9の基
端部fの接着力が弱く、半田部9が電極6,7から剥が
れやすいという問題点があった。
[0005] By the way, the bump 9a and the cream solder 9
b is used in a relatively large amount so that the bonding between the electrodes 6 and 7 is good. Therefore, the bump 9a and the cream solder 9b are heated and melted to be integrated, and easily become the substantially spherical solder portion 9 which bulges outwardly as shown by the solid line in FIG. However, such an outer convex shape has a problem that the adhesive force of the base end portion f of the solder portion 9 is weak and the solder portion 9 is easily peeled off from the electrodes 6 and 7.

【0006】そこで、これを解消する従来手段として、
略球形の半田部9を図13鎖線に示すような内凹状のつ
づみ形に整形して、基端部fを上方の電極6と下方の電
極7にしっかり固着させることが知られている。この整
形は以下のようにして行われる。すなわちリフロー中に
おいて、中間基材2を矢印のように若干上方へ引き上げ
て、加熱溶融状態の半田部9をつづみ形に引き伸し整形
し、この状態のままリフローを進行させて、半田部9を
完全に溶融させた後、冷却して固化させる。
Therefore, as a conventional means for solving this,
It is known that a substantially spherical solder portion 9 is shaped into an indented conical shape as shown by a chain line in FIG. 13 so that a base end portion f is firmly fixed to an upper electrode 6 and a lower electrode 7. This shaping is performed as follows. That is, during the reflow, the intermediate substrate 2 is slightly lifted up as shown by the arrow, and the soldered portion 9 in the heated and melted state is stretched into a continuous shape, and the reflow is progressed in this state. After 9 is completely melted, it is cooled and solidified.

【0007】[0007]

【発明が解決しようとする課題】ところで、従来手段に
おける半田部9の高さは、中間基材2の引き上げ幅hに
よって決定されるが、この中間基材2を一定の幅だけ引
き上げて加熱処理が終了するまでその高さを維持するの
は難しく、形成された半田部9の高さにばらつきが生じ
やすいという問題点があった。
By the way, the height of the solder portion 9 in the conventional means is determined by the lifting width h of the intermediate substrate 2, and the intermediate substrate 2 is pulled up by a certain width and subjected to heat treatment. It is difficult to maintain the height until the process is completed, and the height of the formed solder portion 9 tends to vary.

【0008】そこで本発明は、中間基材の電極を基板の
電極に一定の高さで、しかもしっかりとボンディングで
きる方法を提供することを目的とする。
Accordingly, an object of the present invention is to provide a method capable of firmly bonding an electrode of an intermediate substrate to an electrode of a substrate at a constant height.

【0009】[0009]

【課題を解決するための手段】このために本発明は、中
間基材の第2の電極に、ワイヤボンディング装置のキャ
ピラリツールから導出されたワイヤの下端部のボールを
ボンディングした後、このボールから上方にワイヤを延
出させて切断することにより所定高さのスペーサを形成
し、次いでこのスペーサを基板の電極上の半田に着地さ
せて、この半田を加熱処理するようにした。
To this end, the present invention provides a method for bonding a ball at the lower end of a wire derived from a capillary tool of a wire bonding apparatus to a second electrode of an intermediate base material, forming a spacer of predetermined height by cutting by extending a wire upwardly and then by land the spacer to the solder on the electrode of the board, and to heat treatment to Handa this.

【0010】[0010]

【作用】上記構成によれば、ワイヤボンディングの手法
により、一定高さのスペーサを簡単に形成できる。しか
もリフローにより電極上の半田を溶融させると、溶融し
た半田はスペーサに沿って吸い上げられ、中間基材の電
極と基板の電極をしっかりボンディングできる。
According to the above arrangement, a spacer having a fixed height can be easily formed by a wire bonding technique. In addition , when the solder on the electrodes is melted by reflow, the melted solder is sucked up along the spacer, and the electrodes of the intermediate base material and the electrodes of the substrate can be firmly bonded.

【0011】[0011]

【実施例】(実施例1)次に、図面を参照しながら、本
発明の実施例を説明する。図1は基板と、この基板にボ
ンディングされる中間基材およびチップの全体斜視図で
ある。1はチップ、2は中間基材、3は基板である。チ
ップ1の下面には、電極4がその側縁部に沿って千鳥状
に形成されている。また中間基材2の上面には、チップ
1の電極4に対応するように、第1の電極5が千鳥状に
形成されている。また中間基材2の下面には、第2の電
極6がマトリクス状に形成されている。また基板3の上
面には、この電極6に対応する電極7が同一ピッチでマ
トリクス状に形成されている。
(Embodiment 1) Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is an overall perspective view of a substrate, an intermediate substrate and a chip bonded to the substrate. 1 is a chip, 2 is an intermediate substrate, and 3 is a substrate. On the lower surface of the chip 1, the electrodes 4 are formed in a zigzag along the side edges. On the upper surface of the intermediate substrate 2, first electrodes 5 are formed in a staggered manner so as to correspond to the electrodes 4 of the chip 1. On the lower surface of the intermediate substrate 2, the second electrodes 6 are formed in a matrix. On the upper surface of the substrate 3, electrodes 7 corresponding to the electrodes 6 are formed in a matrix at the same pitch.

【0012】図2において、8aはチップ1の電極4に
形成されたバンプであり、中間基材2の電極5にボンデ
ィングされる。8bは電極5の表面に塗布されたクリー
ム半田である。本実施例では、チップ1の電極4に、ワ
イヤボンディングによりバンプ8aを形成し、このバン
プ8aを中間基材2の電極5に着地させる。次いで加熱
手段により、バンプ8aやクリーム半田8bを加熱して
溶融させ、電極4と電極5をボンディングする。
In FIG. 2, reference numeral 8a denotes a bump formed on the electrode 4 of the chip 1, which is bonded to the electrode 5 of the intermediate substrate 2. 8b is cream solder applied to the surface of the electrode 5. In this embodiment, bumps 8 a are formed on the electrodes 4 of the chip 1 by wire bonding, and the bumps 8 a are landed on the electrodes 5 of the intermediate base material 2. Next, the bumps 8a and the cream solder 8b are heated and melted by heating means, and the electrodes 4 and 5 are bonded.

【0013】次に、図3に示すように中間基材2を表裏
反転させたうえで、図4に示すように中間基材2の第2
の電極6に、ワイヤボンディング装置10のキャピラリ
ツール13から導出されたワイヤ14により、アーチ形
のスペーサ14’を形成する。なお図3において、8は
加熱溶融されて一体化したバンプ8aとクリーム半田8
bである。11はワイヤボンディング装置10の駆動
部、12は先端部にキャピラリツール13が保持された
ホーンであり、駆動部11の駆動により上下方向に揺動
する。
Next, after turning the intermediate substrate 2 upside down as shown in FIG. 3, the second substrate 2 is turned over as shown in FIG.
An arc-shaped spacer 14 ′ is formed on the electrode 6 by the wire 14 led out from the capillary tool 13 of the wire bonding apparatus 10. In FIG. 3, reference numeral 8 denotes a bump 8a which is integrated by heating and melting and a cream solder 8;
b. Reference numeral 11 denotes a driving unit of the wire bonding apparatus 10, and reference numeral 12 denotes a horn having a capillary tool 13 held at a distal end thereof.

【0014】図5はスペーサ14’の形成方法を示して
いる。このスペーサ14’は、QFPやSOPなどの電
子部品の製造工程において行われているワイヤボンディ
ングと同様の手法により、以下のようにして形成され
る。a位置にあるキャピラリツール13の下方にトーチ
15を接近させ、電気的スパークを発生させて、ワイヤ
14の下端部にボール14aを形成する。次にトーチ1
5を側方へ退去させて、キャピラリツール13をb位置
まで下降させ、ボール14aを電極6の一側部にボンデ
ィングする。次いで、キャピラリツール13を斜め上方
のc位置まで若干上昇させて、ワイヤ14を上方へ延出
させた後、d位置まで下降させて、アーチ形に湾曲され
たワイヤ14の基端部14bを電極6の他側部にボンデ
ィングする。
FIG. 5 shows a method of forming the spacer 14 '. The spacer 14 'is formed as follows by a method similar to wire bonding performed in a manufacturing process of electronic components such as QFP and SOP. The torch 15 is made to approach below the capillary tool 13 at the position a to generate an electric spark to form a ball 14 a at the lower end of the wire 14. Next, torch 1
5 is retracted to the side, the capillary tool 13 is lowered to the position b, and the ball 14a is bonded to one side of the electrode 6. Next, the capillary tool 13 is slightly raised to a position c, which is diagonally above, to extend the wire 14 upward, and then lowered to a position d, so that the base end 14b of the arched wire 14 is connected to an electrode. 6 is bonded to the other side.

【0015】次にキャピラリツール13をe位置まで引
き上げ、且つワイヤ14をクランパ(図外)によりクラ
ンプして上方へ引き上げれば、ワイヤ14は基端部14
bから切断され、上記スペーサ14’が形成される。こ
のように、ワイヤボンディングを応用した本手段によれ
ば、ワイヤ14により所定高さHのスペーサ14’を簡
単に形成することができる。なお本実施例は電極6を大
形とし、ワイヤ14のボール14aと基端部14bを電
極6にボンディングしているが、電極6を小形とし、ボ
ール14aのみをこの電極6にボンディングし、基端部
14bは中間基材2の上面にボンディングしてもよい。
Next, when the capillary tool 13 is pulled up to the position e and the wire 14 is clamped by a clamper (not shown) and pulled up, the wire 14 is pulled up to the base end 14.
b to form the spacers 14 '. As described above, according to the present means to which the wire bonding is applied, the spacer 14 ′ having the predetermined height H can be easily formed by the wire 14. In this embodiment, the electrode 6 is made large, and the ball 14a and the base end 14b of the wire 14 are bonded to the electrode 6. However, the electrode 6 is made small, and only the ball 14a is bonded to this electrode 6. The end 14b may be bonded to the upper surface of the intermediate substrate 2.

【0016】以上のようにして、中間基材2のすべての
第2の電極6にスペーサ14’を形成したならば、次に
図6に示すように中間基材2の表裏を反転させ、移載ヘ
ッド16のノズル17に吸着して、スペーサ14’をク
リーム半田18が塗布された基板3の電極7に着地させ
る。図7はスペーサ14’の着地状態を示している。図
示するように、スペーサ14’のアーチ形の下端部が電
極7に着地し、基板3と中間基材2の間隔Dは一定に保
たれる。半田としては、半田レベラ手段や半田メッキ手
段などで形成されたものでもよく、要は、スペーサ1
4’のアーチ形の下端部を電極7上の半田に着地させれ
ばよい。図6において、19は中間基材2の表面の電極
5と裏面の電極6を接続する導電材である。
After the spacers 14 'have been formed on all the second electrodes 6 of the intermediate substrate 2 as described above, the intermediate substrate 2 is turned upside down as shown in FIG. The spacer 14 ′ is attracted to the nozzle 17 of the mounting head 16 and lands on the electrode 7 of the substrate 3 on which the cream solder 18 is applied. FIG. 7 shows a landing state of the spacer 14 '. As shown, the arched lower end of the spacer 14 'lands on the electrode 7, and the distance D between the substrate 3 and the intermediate substrate 2 is kept constant. For solder, use solder leveler or solder plating
It may be formed by steps or the like.
Land the 4 'arched lower end on the solder on electrode 7
I just need. In FIG. 6, reference numeral 19 denotes a conductive material that connects the electrode 5 on the front surface of the intermediate substrate 2 and the electrode 6 on the rear surface.

【0017】このようにして中間基材2を基板3に搭載
したならば、次にリフロー装置により加熱処理する。図
8はリフロー後の側面図である。リフロー装置により加
熱溶融されたクリーム半田18は、ワイヤ14から成る
スペーサ14’に沿って吸い上げられ、同図部分拡大図
に示すように、電極6と電極7の間に、略つづみ形をし
た内凹状の半田部20が形成され、中間基材2は基板3
にしっかり固着される。ここで、半田部20の高さはス
ペーサ14’の高さHによって規定されるため、従来手
段のような、加熱処理時に中間基材2を若干引き上げた
まま維持する方法に比べて、高さ精度の向上が図れる。
After the intermediate substrate 2 is mounted on the substrate 3 as described above, the substrate is heated by a reflow apparatus. FIG. 8 is a side view after reflow. The cream solder 18 heated and melted by the reflow device is sucked up along the spacer 14 ′ composed of the wire 14, and has a substantially continuous shape between the electrode 6 and the electrode 7 as shown in a partially enlarged view of FIG. An inwardly concave solder portion 20 is formed, and the intermediate substrate 2 is
Firmly adhered to. Here, since the height of the solder portion 20 is determined by the height H of the spacer 14 ', the height is higher than that of the conventional method in which the intermediate substrate 2 is slightly lifted and maintained during the heat treatment. The accuracy can be improved.

【0018】さらに本手段では、半田部20の中にスペ
ーサ14’が埋設されているため、このスペーサ14’
の体積分だけクリーム半田18の使用量が削減でき、し
たがってリフロー時に電極7に多量に塗布されたクリー
ム半田18が横方向に流れ出して半田ブリッジや半田ボ
ールが発生するのを抑制できる。なお図8において、リ
フロー後にはクリーム半田18とスペーサ14’は完全
に溶融して一体化し、半田部20となるが、説明の都合
上、両者18,14’が一体化していない状態で示して
いる。
Further, according to the present means, since the spacer 14 'is embedded in the solder portion 20, the spacer 14'
Therefore, the amount of the cream solder 18 used can be reduced by the above volume, so that it is possible to prevent the cream solder 18 applied to the electrode 7 in a large amount from flowing out in the horizontal direction at the time of reflow and to generate a solder bridge or a solder ball. In FIG. 8, after the reflow, the cream solder 18 and the spacer 14 ′ are completely melted and integrated to form the solder portion 20, but for the sake of explanation, the two are not integrated. I have.

【0019】(実施例2)図9は他の実施例に係るボン
ディング中の側面図であり、中間基材2の電極6には、
スペーサ14’が形成されている。このスペーサ14’
も、ワイヤボンディングと同様の手法により、次のよう
にして形成される。すなわち、a位置にあるキャピラリ
ツール13をb位置まで下降させて、ボール14aを電
極6にボンディングし、次いでキャピラリツール13を
c位置まで上昇させてワイヤ14を上方にまっすぐ延出
させ、ここでワイヤ14をクランパによりクランプして
d位置まで引き上げることにより、ワイヤ14を切断し
てスペーサ14’を形成する。
(Embodiment 2) FIG. 9 is a side view during bonding according to another embodiment.
A spacer 14 'is formed. This spacer 14 '
Is formed in the same manner as wire bonding as follows. That is, the capillary tool 13 at the position a is lowered to the position b, the ball 14a is bonded to the electrode 6, and then the capillary tool 13 is raised to the position c to extend the wire 14 straight upward. The wire 14 is cut by forming the spacer 14 ′ by clamping the wire 14 to a position d by clamping it with a clamper.

【0020】以上のようにして、中間基材2のすべての
電極6にスペーサ14’を形成したなら、図10に示す
ようにこのスペーサ14’の高さを調整する高さ調整装
置のシリンダ20のロッド21を突出させて、スペーサ
14’の上端部を押圧子22によって押圧し、すべての
スペーサ14’の高さを所定の高さHに揃える。
When the spacers 14 'are formed on all the electrodes 6 of the intermediate substrate 2 as described above, as shown in FIG. 10, the cylinder 20 of the height adjusting device for adjusting the height of the spacers 14' is used. Of the spacer 14 ′ is pressed by the pressing element 22, and the height of all the spacers 14 ′ is adjusted to a predetermined height H.

【0021】次いで中間基材2を表裏反転させて、図1
1に示すように、クリーム半田18が塗布された基板3
の電極7にスペーサ14’の下端部を着地させる。次に
リフロー装置により加熱処理すると、溶融したクリーム
半田18はスペーサ14’に沿って吸い上げられ、両者
14’,18は一体化して、略つづみ形の半田部20が
形成される。
Next, the intermediate substrate 2 is turned upside down, and FIG.
As shown in FIG. 1, the substrate 3 coated with the cream solder 18
The lower end of the spacer 14 ′ is landed on the electrode 7. Next, when a heat treatment is performed by a reflow device, the melted cream solder 18 is sucked up along the spacer 14 ', and the both 14' and 18 are integrated to form a substantially continuous solder portion 20.

【0022】[0022]

【発明の効果】以上説明したように本発明によれば、中
間基材の電極を、基板の電極に一定の高さで、しかもし
っかりとボンディングできる。
As described above, according to the present invention, the electrode of the intermediate substrate can be firmly bonded to the electrode of the substrate at a constant height.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施例1に係る基板およびこの基板に
搭載される中間基材およびチップの全体斜視図
FIG. 1 is an overall perspective view of a substrate according to a first embodiment of the present invention, an intermediate base material and a chip mounted on the substrate.

【図2】同チップのボンディング中の側面図FIG. 2 is a side view of the chip during bonding.

【図3】同ボンディング中の側面図FIG. 3 is a side view during the bonding.

【図4】同スペーサの形成中のワイヤボンディング装置
の斜視図
FIG. 4 is a perspective view of the wire bonding apparatus during formation of the spacer.

【図5】同スペーサの形成中の側面図FIG. 5 is a side view during formation of the spacer.

【図6】同中間基材のボンディング中の側面図FIG. 6 is a side view of the intermediate substrate during bonding.

【図7】同スペーサの側面図FIG. 7 is a side view of the spacer.

【図8】同中間基材のボンディング後の側面図FIG. 8 is a side view of the intermediate substrate after bonding.

【図9】本発明の実施例2に係るスペーサ形成中の側面
FIG. 9 is a side view during spacer formation according to the second embodiment of the present invention.

【図10】同スペーサの高さ調整中の側面図FIG. 10 is a side view of the spacer during height adjustment.

【図11】同スペーサの側面図FIG. 11 is a side view of the spacer.

【図12】従来手段に係る中間基材のボンディング中の
側面図
FIG. 12 is a side view during bonding of an intermediate substrate according to a conventional means.

【図13】同中間基材のボンディング中の要部側面図FIG. 13 is a side view of a main part of the intermediate substrate during bonding.

【符号の説明】[Explanation of symbols]

1 チップ 2 中間基材 3 基板 5 第1の電極 6 第2の電極 10 ワイヤボンディング装置 13 キャピラリツール 14 ワイヤ 14a ボール 14’ スペーサ 18 クリーム半田 DESCRIPTION OF SYMBOLS 1 Chip 2 Intermediate base material 3 Substrate 5 1st electrode 6 2nd electrode 10 Wire bonding apparatus 13 Capillary tool 14 Wire 14a Ball 14 'Spacer 18 Cream solder

───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7,DB名) H01L 23/12 H01L 21/60 ──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 7 , DB name) H01L 23/12 H01L 21/60

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】上面にチップがボンディングされる第1の
電極を有し、下面にマトリクス状の第2の電極を有する
中間基材のこの第2の電極を、基板にマトリクス状に形
成された電極にボンディングするにあたり、 上記第2の電極に、ワイヤボンディング装置のキャピラ
リツールから導出されたワイヤの下端部のボールをボン
ディングした後、このボールから上方にワイヤを延出さ
せて切断することにより所定高さのスペーサを形成し、
次いでこのスペーサを上記基板の電極上の半田に着地さ
せて、この半田を加熱処理することを特徴とする中間基
材のボンディング方法。
An intermediate substrate having a first electrode to which a chip is bonded on an upper surface and a matrix-like second electrode on a lower surface is formed in a matrix on a substrate. In bonding to the electrode, after bonding the ball at the lower end of the wire led out from the capillary tool of the wire bonding apparatus to the second electrode, the wire is extended upward from the ball and cut to a predetermined value. Form a spacer of height,
Then by landing the spacer in the solder on the upper Symbol substrate electrode, a bonding method of the intermediate base, which comprises heating a semi-field of this.
JP4013801A 1992-01-29 1992-01-29 Intermediate substrate bonding method Expired - Fee Related JP3055285B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4013801A JP3055285B2 (en) 1992-01-29 1992-01-29 Intermediate substrate bonding method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4013801A JP3055285B2 (en) 1992-01-29 1992-01-29 Intermediate substrate bonding method

Publications (2)

Publication Number Publication Date
JPH05206357A JPH05206357A (en) 1993-08-13
JP3055285B2 true JP3055285B2 (en) 2000-06-26

Family

ID=11843364

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4013801A Expired - Fee Related JP3055285B2 (en) 1992-01-29 1992-01-29 Intermediate substrate bonding method

Country Status (1)

Country Link
JP (1) JP3055285B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5796169A (en) * 1996-11-19 1998-08-18 International Business Machines Corporation Structurally reinforced ball grid array semiconductor package and systems
JP3727615B2 (en) * 2002-06-26 2005-12-14 株式会社新川 Wire bonding wire initial ball forming method and wire bonding apparatus

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59208756A (en) * 1983-05-12 1984-11-27 Sony Corp Manufacture of semiconductor device package
JPH02102738U (en) * 1989-01-31 1990-08-15

Also Published As

Publication number Publication date
JPH05206357A (en) 1993-08-13

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