JP2000049192A - Flip-chip element mounting method - Google Patents

Flip-chip element mounting method

Info

Publication number
JP2000049192A
JP2000049192A JP10216236A JP21623698A JP2000049192A JP 2000049192 A JP2000049192 A JP 2000049192A JP 10216236 A JP10216236 A JP 10216236A JP 21623698 A JP21623698 A JP 21623698A JP 2000049192 A JP2000049192 A JP 2000049192A
Authority
JP
Japan
Prior art keywords
bump
substrate
electrode pads
insulating sheet
mounting method
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10216236A
Other languages
Japanese (ja)
Inventor
Masao Asai
正男 浅井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP10216236A priority Critical patent/JP2000049192A/en
Publication of JP2000049192A publication Critical patent/JP2000049192A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/811Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector the bump connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/81101Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector the bump connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a bump connector, e.g. provided in an insulating plate member

Abstract

PROBLEM TO BE SOLVED: To provide a mounting method in which even electrode pads arranged at fine pitch can be connected surely each other. SOLUTION: A large number of contact holes 11 are made through an insulating sheet 10 by punching and filled with solder paste 12 by screen printing. An insulating sheet 10 is then mounted on a substrate 30 while matching the contact holes 11 with electrode pads 31 and a semiconductor element 20 is mounted thereon while matching the contact holes 11 with electrodes 22. The solder paste 12 is spread into vertical gaps by applying a pressure from above and below. Finally, it is heated entirely at 200-220 deg.C to melt the solder paste 12 by reflow thus connecting both electrode pads 22, 31 electrically through a bump.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】この発明は、素子の能動素子
面に形成された電極パッドと基板の電極パッドとをバン
プを介して接続するフリップチップ方式の素子実装方法
に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flip chip type element mounting method for connecting an electrode pad formed on an active element surface of an element to an electrode pad of a substrate via a bump.

【0002】[0002]

【従来の技術】従来のフリップチップ方式の素子実装方
法を図2の工程図に従って説明する。半導体素子1の能
動素子面1aには、図2(a)に示すように内部回路と接
続された電極パッド2が複数形成されており、その周囲
はパッシベーション膜3により保護されている。電極パ
ッド2には、スクリーン印刷や電解メッキ等の手段によ
りハンダバンプ4が形成される。
2. Description of the Related Art A conventional flip chip type element mounting method will be described with reference to the process chart of FIG. As shown in FIG. 2A, a plurality of electrode pads 2 connected to an internal circuit are formed on the active element surface 1a of the semiconductor element 1, and the periphery thereof is protected by a passivation film 3. The solder bumps 4 are formed on the electrode pads 2 by means such as screen printing or electrolytic plating.

【0003】続いて、ハンダバンプ4が形成された半導
体素子1を基板5に対して位置合わせして搭載する。図
2(b)に示すように、基板5にも電極パッド6が形成さ
れており、その周囲はパッシベーション膜7により保護
されている。半導体素子1は、ハンダバンプ4が基板5
の電極パッド6に対応するように位置合わせされる。
Subsequently, the semiconductor element 1 on which the solder bumps 4 are formed is mounted on the substrate 5 while being positioned. As shown in FIG. 2B, an electrode pad 6 is also formed on the substrate 5, and its periphery is protected by a passivation film 7. The semiconductor element 1 includes a solder bump 4 and a substrate 5.
Is aligned so as to correspond to the electrode pad 6 of the first embodiment.

【0004】半導体素子1を基板5上に搭載した後、リ
フローによりハンダバンプ4を溶融させる。ハンダバン
プ4は、溶融して図2(c)に示すように球体状となり、
両電極パッド2,6間を電気的に接続する。最後に、ハ
ンダバンプ4を保護するため、図2(d)に示すように半
導体素子1と基板5との間の隙間に絶縁性樹脂8を充填
し、熱硬化させる。
After mounting the semiconductor element 1 on the substrate 5, the solder bumps 4 are melted by reflow. The solder bumps 4 are melted into a spherical shape as shown in FIG.
The two electrode pads 2 and 6 are electrically connected. Finally, in order to protect the solder bumps 4, the gap between the semiconductor element 1 and the substrate 5 is filled with an insulating resin 8 as shown in FIG.

【0005】[0005]

【発明が解決しようとする課題】しかしながら、上述し
た従来の素子実装方法では、ハンダバンプの接続強度を
高めるためにバンプの高さを増加させようとしてハンダ
量を増やすと、リフロー後の形状が球形であることか
ら、ハンダバンプの高さのみでなく幅も広がり、バンプ
ピッチが拡大して電極パッドの高密度化に対応できない
という問題がある。また、従来の方法では、リフロー時
にハンダバンプの流動範囲を規制する手段がないため、
リフロー後のハンダバンプの幅と高さとの比率がバンプ
毎にばらつき、高さが不足するバンプにおいて電極パッ
ド間の接続不良が発生するという問題もある。
However, in the conventional device mounting method described above, if the solder amount is increased in order to increase the bump height in order to increase the connection strength of the solder bump, the shape after reflow becomes spherical. For this reason, not only the height but also the width of the solder bumps are widened, and the bump pitch is widened, so that there is a problem that it is impossible to cope with the high density of the electrode pads. Also, in the conventional method, there is no means for regulating the flow range of the solder bump during reflow,
There is also a problem that the ratio between the width and the height of the solder bump after the reflow varies from bump to bump, and a connection failure between the electrode pads occurs in the bump having an insufficient height.

【0006】この発明は、上述した従来技術の問題点に
鑑みてなされたものであり、バンプの高さを増加させた
場合にも幅を増加させることなく、電極パッドのピッチ
の高密度化にも対応でき、しかも、電極パッド間を確実
に接続することができるフリップチップ方式の素子実装
方法の提供を課題(目的)とする。
SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems of the prior art, and is intended to increase the pitch of electrode pads without increasing the width even when the height of the bump is increased. It is another object of the present invention to provide a flip-chip type element mounting method that can cope with the above problem and that can reliably connect between electrode pads.

【0007】[0007]

【課題を解決するための手段】この発明にかかるフリッ
プチップ方式の素子実装方法は、上記の目的を達成させ
るため、素子の能動素子面に形成された電極パッドと基
板の電極パッドとの間にバンプを介在させ、リフローに
よりバンプを溶融させて両電極パッド間を電気的に接続
する実装方法において、絶縁性シートに電極パッドの位
置に応じてシートを貫通する接続孔を形成し、接続孔内
にバンプ材料を充填し、絶縁性シートを、電極パッドと
接続孔とが対応するようにして基板と素子との間に配置
し、リフローによりバンプ材料を溶融させることにより
両電極パッドを接続することを特徴とする。
SUMMARY OF THE INVENTION In order to achieve the above object, a flip-chip type device mounting method according to the present invention is provided between an electrode pad formed on an active element surface of a device and an electrode pad of a substrate. In a mounting method in which a bump is interposed and the bump is melted by reflow to electrically connect the two electrode pads, a connection hole is formed in the insulating sheet through the sheet according to the position of the electrode pad, and the inside of the connection hole is formed. Filling the bump material, placing the insulating sheet between the substrate and the element so that the electrode pads correspond to the connection holes, and connecting the two electrode pads by melting the bump material by reflow It is characterized by.

【0008】上記の方法によれば、リフローによるバン
プ材料の広がりは絶縁性シートの接続孔内に限定される
ため、幅方向の広がりを抑えつつ、高さを任意に設定す
ることができる。また、バンプ材料の幅方向の広がりが
規制される結果、バンプの高さを一定に保つことができ
る。
According to the above method, since the spread of the bump material due to the reflow is limited to the inside of the connection hole of the insulating sheet, the height can be arbitrarily set while suppressing the spread in the width direction. In addition, the width of the bump material is regulated in the width direction, so that the height of the bump can be kept constant.

【0009】[0009]

【発明の実施の形態】以下、この発明にかかるフリップ
チップ方式の素子実装方法の実施形態を説明する。図1
は、実施形態にかかる実装方法を示す工程図である。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a flip-chip type device mounting method according to the present invention will be described below. FIG.
FIG. 2 is a process diagram showing a mounting method according to the embodiment.

【0010】図1(a)に示すように、厚さ100μm程
度の絶縁性シート10に、パンチングによりシートを貫
通する同径の接続孔11を多数形成する。絶縁性シート
10は、熱処理により半導体素子と基板とを接着する作
用を持つエポキシ樹脂、シリコン系樹脂からなる。接続
孔11は、断面円形のストレートな孔であり、その形成
位置は、実装される半導体素子、基板の電極パッドの位
置に応じて決定される。
As shown in FIG. 1A, a large number of connection holes 11 having the same diameter penetrating the sheet are formed in an insulating sheet 10 having a thickness of about 100 μm by punching. The insulating sheet 10 is made of an epoxy resin or a silicon-based resin having a function of bonding the semiconductor element and the substrate by heat treatment. The connection hole 11 is a straight hole having a circular cross section, and the formation position is determined according to the position of the semiconductor element to be mounted and the position of the electrode pad on the substrate.

【0011】パンチングは、パンチングマシンを用い、
以下の手順で実行される。まず、絶縁性シート10をパ
ンチングマシンでの加工用の金属枠に糊で貼付ける。金
属枠の角をパンチングマシンのステージ上に設けられた
位置決め用突当て部に2方向から当てて位置決めし、固
定する。次に、パンチングマシンに基板に形成された電
極パッドの座標データを入力し、このデータに基づいて
パンチングマシンを作動させることにより、シートの電
極パッドに対応する部分を打ち抜く。パンチングマシン
には、打ち抜き用の昇降自在のパンチが備えられてお
り、絶縁性シート10が載置されたステージを座標デー
タに基づいて移動させ、所定の位置毎にパンチを昇降さ
せて接続孔11を形成してゆく。なお、パンチは、その
外径が接続孔11の径と等しいものを用いる。接続孔1
1が全て形成された後、絶縁性シート10を金属枠から
剥離することにより、所定の位置に接続孔11が形成さ
れた絶縁性シート10を得ることができる。
Punching is performed using a punching machine.
It is performed in the following procedure. First, the insulating sheet 10 is pasted on a metal frame for processing by a punching machine with glue. The metal frame is positioned and fixed by applying the corners of the metal frame to the positioning abutting portions provided on the stage of the punching machine from two directions. Next, coordinate data of the electrode pads formed on the substrate is input to the punching machine, and the punching machine is operated based on the data, thereby punching out a portion of the sheet corresponding to the electrode pads. The punching machine includes a vertically movable punch for punching. The stage on which the insulating sheet 10 is mounted is moved based on the coordinate data, and the punch is moved up and down at predetermined positions to connect holes 11. To form. In addition, the punch whose outer diameter is equal to the diameter of the connection hole 11 is used. Connection hole 1
After all the layers 1 are formed, the insulating sheet 10 is peeled from the metal frame to obtain the insulating sheet 10 in which the connection holes 11 are formed at predetermined positions.

【0012】続いて、図1(b)に示すように、スクリー
ン印刷により絶縁性シート10の接続孔11内にバンプ
材料としてハンダペースト12を充填する。ハンダペー
ストの量は、絶縁性シート10のシート厚と同じ高さに
なるよう設定される。
Subsequently, as shown in FIG. 1B, a solder paste 12 is filled as a bump material in the connection holes 11 of the insulating sheet 10 by screen printing. The amount of the solder paste is set to be the same height as the sheet thickness of the insulating sheet 10.

【0013】次に、図1(c)に示すように、ハンダペー
スト12を充填した絶縁性シート10を半導体素子20
と基板30との間に配置する。半導体素子20の能動素
子面21には、内部回路と接続された電極パッド22が
複数形成されており、その周囲はパッシベーション膜2
3により保護されている。他方、基板30にも電極パッ
ド31が多数形成されており、その周囲はパッシベーシ
ョン膜32により保護されている。
Next, as shown in FIG. 1C, the insulating sheet 10 filled with the solder paste 12 is
And the substrate 30. On the active element surface 21 of the semiconductor element 20, a plurality of electrode pads 22 connected to an internal circuit are formed.
3 protected. On the other hand, a large number of electrode pads 31 are also formed on the substrate 30, and the periphery thereof is protected by a passivation film 32.

【0014】絶縁性シート10の配置に際しては、まず
基板30の上に、接続孔11と電極パッド31とが対応
するように位置合わせして絶縁性シート10を載置し、
その後、絶縁性シート10の上に、接続孔11と電極2
2とが対応するように位置合わせわせして半導体素子2
0を搭載する。
When arranging the insulating sheet 10, the insulating sheet 10 is first placed on the substrate 30 so that the connection holes 11 and the electrode pads 31 correspond to each other.
Then, the connection hole 11 and the electrode 2 are placed on the insulating sheet 10.
2 and the semiconductor element 2
0 is mounted.

【0015】基板30、絶縁性シート10、半導体素子
20には、予め外形合わせ用のマーカーを形成してお
き、これらの位置合わせの際には、それらのマーカーを
用いて外形を合わせる。
Markers for adjusting the outer shape are formed on the substrate 30, the insulating sheet 10, and the semiconductor element 20 in advance, and the outer shape is adjusted by using the markers at the time of alignment.

【0016】絶縁性シート10を半導体素子20と基板
30との間に配置した状態では、電極パッド22,31
とパッシベーション膜23,32の高さの違いにより、
ハンダペースト12と各電極パッド22,31との間に
隙間が生じる。ここで、半導体素子20と基板30とを
挟み込むようにして上下から圧力をかけると、絶縁性シ
ート10の樹脂層には幅方向に広がる力が作用し、接続
孔11内のハンダペースト12を左右両側から圧迫す
る。この圧迫によりハンダペースト12は、図1(d)に
示すように上下の隙間に入り込み、半導体素子20の電
極パッド22と基板30の電極パッド31とに接触す
る。
When the insulating sheet 10 is disposed between the semiconductor element 20 and the substrate 30, the electrode pads 22, 31
And the height of the passivation films 23 and 32
A gap is generated between the solder paste 12 and each of the electrode pads 22 and 31. Here, when pressure is applied from above and below so as to sandwich the semiconductor element 20 and the substrate 30, a force spreading in the width direction acts on the resin layer of the insulating sheet 10, and the solder paste 12 in the connection hole 11 is moved right and left. Compression from both sides. Due to this compression, the solder paste 12 enters the upper and lower gaps as shown in FIG. 1D and comes into contact with the electrode pads 22 of the semiconductor element 20 and the electrode pads 31 of the substrate 30.

【0017】ここで全体を150℃〜170℃に加熱
し、絶縁性シート10の樹脂を硬化させて半導体素子2
0と基板30とを接着、固定する。最後に、全体を20
0℃〜220℃程度に加熱し、リフローによりハンダペ
ースト12を溶融させることにより、これがバンプとな
って両電極パッド22,31間を電気的に接続する。溶
融したハンダペーストの流動範囲は、接続孔11により
限定されるため、幅方向に広がることはなく、したがっ
て、高さ方向の広がりも従来技術のようにバンプ毎にば
らつくことなく一定となる。
Here, the whole is heated to 150 ° C. to 170 ° C. to cure the resin of the insulating sheet 10 and
0 and the substrate 30 are bonded and fixed. Finally, the whole 20
By heating the solder paste 12 to about 0 ° C. to 220 ° C. and melting the solder paste 12 by reflow, the solder paste 12 becomes a bump to electrically connect the two electrode pads 22 and 31. Since the flow range of the molten solder paste is limited by the connection holes 11, it does not spread in the width direction, so that the spread in the height direction is constant without dispersion from bump to bump as in the prior art.

【0018】上記の実施形態の方法によれば、リフロー
により形成されるバンプ形状が従来のような球形ではな
く、よりストレートな形状に近づく。また、絶縁性シー
ト10の厚さを適宜選択することにより、バンプ幅を広
げることなく任意の高さのバンプを形成することができ
る。このため、バンプの高さを高くした場合にも、バン
プのピッチを小さく保つことにより高密度化に対応する
ことができる。しかも、バンプの高さを一定に保つこと
ができるため、全てのバンプが同一の状態で半導体素子
20と基板30との電極パッド22,31に接続され、
接続不良が発生し難く、電極パッド22,31間を確実
に接続することができる。
According to the method of the above-described embodiment, the shape of the bump formed by the reflow is not a spherical shape as in the related art, but closer to a straight shape. Further, by appropriately selecting the thickness of the insulating sheet 10, a bump having an arbitrary height can be formed without increasing the width of the bump. For this reason, even when the height of the bump is increased, it is possible to cope with high density by keeping the pitch of the bump small. Moreover, since the height of the bumps can be kept constant, all the bumps are connected to the electrode pads 22 and 31 of the semiconductor element 20 and the substrate 30 in the same state,
Connection failure is unlikely to occur, and the electrode pads 22 and 31 can be reliably connected.

【0019】[0019]

【発明の効果】以上説明したように、この発明の方法に
よれば、絶縁性シートに形成された接続孔にバンプ材料
を充填した状態でリフローをかけることにより、形成さ
れるバンプの幅を制限することができ、バンプのピッチ
を小さく保つことにより高密度化に対応することができ
る。また、形成されるバンプの高さが一定に保たれるた
め、全てのバンプが同一の状態で素子と基板との電極パ
ッドに接続され、電極パッド間の接続不良の発生を防ぐ
ことができる。
As described above, according to the method of the present invention, the width of the bump to be formed is limited by reflowing the connection hole formed in the insulating sheet with the bump material being filled. By keeping the pitch of the bumps small, it is possible to cope with high density. In addition, since the height of the formed bumps is kept constant, all the bumps are connected to the electrode pads of the element and the substrate in the same state, and it is possible to prevent the occurrence of connection failure between the electrode pads.

【0020】請求項2のように、絶縁性シートにより素
子と基板とを接着するようにした場合には、素子と基板
とをバンプ部分のみでなく、シート前面で固定すること
ができるため、バンプにかかる負担を軽減すると共に、
より強固な固定が可能となる。
In the case where the element and the substrate are bonded by an insulating sheet, the element and the substrate can be fixed not only at the bump portion but also at the front surface of the sheet. To reduce the burden on
Stronger fixation becomes possible.

【図面の簡単な説明】[Brief description of the drawings]

【図1】 この発明の実施形態にかかるフリップチップ
方式の素子実装方法を段階的に示す工程図である。
FIG. 1 is a process diagram showing step by step a method of mounting a flip-chip device according to an embodiment of the present invention.

【図2】 従来のフリップチップ方式の素子実装方法を
段階的に示す工程図である。
FIG. 2 is a process diagram showing step by step a conventional flip-chip element mounting method.

【符号の説明】[Explanation of symbols]

10 絶縁性シート 11 接続孔 12 ハンダペースト 20 半導体素子 21 能動素子面 22 電極パッド 23 パッシベーション膜 30 基板 31 電極パッド 32 パッシベーション膜 DESCRIPTION OF SYMBOLS 10 Insulating sheet 11 Connection hole 12 Solder paste 20 Semiconductor element 21 Active element surface 22 Electrode pad 23 Passivation film 30 Substrate 31 Electrode pad 32 Passivation film

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 素子の能動素子面に形成された電極パッ
ドと基板の電極パッドとの間にバンプを介在させ、リフ
ローにより前記バンプを溶融させて前記両電極パッド間
を電気的に接続するフリップチップ方式の素子実装方法
において、 絶縁性シートに前記電極パッドの位置に応じてシートを
貫通する接続孔を形成し、該接続孔内にバンプ材料を充
填し、前記絶縁性シートを、前記電極パッドと前記接続
孔とが対応するようにして前記基板と前記素子との間に
配置し、リフローにより前記バンプ材料を溶融させるこ
とにより前記両電極パッドを接続することを特徴とする
フリップチップ方式の素子実装方法。
1. A flip for interposing a bump between an electrode pad formed on an active element surface of an element and an electrode pad of a substrate, melting the bump by reflow, and electrically connecting the two electrode pads. In a chip-type element mounting method, a connection hole penetrating a sheet according to a position of the electrode pad is formed in an insulating sheet, a bump material is filled in the connection hole, and the insulating sheet is connected to the electrode pad. And the connection holes are arranged between the substrate and the element so as to correspond to each other, and the two electrode pads are connected by melting the bump material by reflow. Implementation method.
【請求項2】 前記絶縁性シートは、熱処理により前記
素子と前記基板とを接着する樹脂製のシートであること
を特徴とする請求項1に記載のフリップチップ方式の素
子実装方法。
2. The method according to claim 1, wherein the insulating sheet is a resin sheet for bonding the element and the substrate by heat treatment.
JP10216236A 1998-07-30 1998-07-30 Flip-chip element mounting method Pending JP2000049192A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10216236A JP2000049192A (en) 1998-07-30 1998-07-30 Flip-chip element mounting method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10216236A JP2000049192A (en) 1998-07-30 1998-07-30 Flip-chip element mounting method

Publications (1)

Publication Number Publication Date
JP2000049192A true JP2000049192A (en) 2000-02-18

Family

ID=16685417

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10216236A Pending JP2000049192A (en) 1998-07-30 1998-07-30 Flip-chip element mounting method

Country Status (1)

Country Link
JP (1) JP2000049192A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100484888B1 (en) * 2002-11-07 2005-04-28 재단법인서울대학교산학협력재단 Flip chip mounting method using a solderfill
KR100484891B1 (en) * 2002-09-18 2005-04-28 재단법인서울대학교산학협력재단 One step flip chip mounting method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100484891B1 (en) * 2002-09-18 2005-04-28 재단법인서울대학교산학협력재단 One step flip chip mounting method
KR100484888B1 (en) * 2002-11-07 2005-04-28 재단법인서울대학교산학협력재단 Flip chip mounting method using a solderfill

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