JPH054648U - Communication I / F circuit - Google Patents

Abstract

(57) [Summary] [Objective] To obtain a communication I / F circuit that performs data transmission / reception between devices controlled by the processing of a microprocessor and interrupt control between a plurality of arbitrary devices quickly. To aim. [Composition] The communication I / F circuit is independently provided with a two-port RAM, and all signals such as a data BUS signal and an address / control BUS signal are bidirectional.
Interrupt control is also possible by accessing a specific address on the 2-port RAM. [Effect] Data transmission / reception between arbitrary devices and interrupt processing can be performed at high speed without passing through a microprocessor of a specific channel (device), and processing related to communication of each channel (device) is simple. Is effective.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to a communication I / F circuit for transmitting and receiving data between devices, which is controlled by the processing of a microprocessor.

[0002]

[Prior Art]

 FIG. 4 is a system block diagram in a conventional communication I / F circuit. In the figure, 1 is the No. 1 channel (device) communication I / F circuit, 2 is the No. 2 channel (device) communication I / F circuit, 3 and 4 are No. 3 and No. n channel (device) ) It is a communication I / F circuit and has the same configuration as the circuit of 2. 5 is a data BUS driver / receiver that performs I / F with 6 data BUS, 7 is an address / control BUS driver that performs I / F with 9 address / control BUS, 8 is the same receiver, 10 is An interrupt signal receiver that performs I / F with 12 interrupt signal lines, 11 is the same driver, and 13 is an interrupt signal control circuit, which controls an interrupt signal 19. 14 is a 2-PORT RAM for transmitting / receiving data, 15 is a 2-PORT control circuit for controlling the access of 14, 16 is a channel control circuit, 17 is a channel selection circuit, and 18 is an interrupt signal generation circuit. ..

Next, the operation will be described. First, when data is sent and received between the No. 1 channel (device) and No. 2 channel (device), the No. 1 channel (device) microprocessor is the 1 No. 1 channel (device) communication. I / F circuit data BUS driver / receiver 5, address / control BUS driver 7, 2 No. 2 channel (device) communication I / F circuit data BUS driver / receiver 5, address / control BUS receiver 8 To access 14 2-PORT RAMs. At this time, the coincidence between the channel selection signal 20 selected in advance by the channel selection circuit 17 and the sent address signal 21 is discriminated by the 16 channel control circuits, and if they coincide, the channel is validated. The signal 22 becomes valid and is sent to the 2-PORT control circuit 15 and, after the priority of the access right of the 2-PORT RAM of 14 with the microprocessor of the No. 2 channel (device) is determined here. , 23 to enable access and data transmission / reception. Data transmission / reception between the No. 1 channel (device) and the No. 3 channel (device) or the No. n channel (device) is performed by the same procedure.

Next, the interrupt operation will be described. When an emergency interrupt factor is generated from No.2 channel (device), the microprocessor of No.2 channel (device) controls 18 interrupt signal generation circuits to generate 24 interrupt signals. The signal is sent to the No. 1 channel (device) communication I / F circuit of No. 1 through 11 interrupt signal drivers and 12 interrupt signal lines. The sent signal is sent to the interrupt signal control circuit 13 through the interrupt signal receiver 10 and is sent to the microprocessor of No. 1 channel (device) as an interrupt signal 19 for processing. .. Interrupt signals from No. 3 channel (device) or No. n channel (device) are also processed by the same procedure.

[0005]

[Problems to be solved by the device]

 Since the conventional communication I / F circuit is configured as described above, when transmitting and receiving data between arbitrary devices, the microprocessor of the No. 1 device must be used, and the No. 1 device must be used. The first device had to constantly monitor data exchange requests between arbitrary devices. In addition, even when an emergency interrupt process occurs between arbitrary devices, it is necessary to always go through the No. 1 device, and there is a problem that interrupt processing takes time.

The present invention has been made to solve the above-described problems, and can transmit and receive data and perform an emergency interrupt between arbitrary devices without going through the microprocessor of the device of No. 1. The purpose is to obtain a communication I / F circuit that can perform processing quickly.

[0007]

[Means for Solving the Problems]

 A communication I / F circuit according to the present invention, when transmitting / receiving data between devices controlled by the processing of a microprocessor, has a 2-port RAM independently in the communication I / F circuit and a data BUS signal. By making all address / control BUS signals bidirectional, a control circuit that enables data transmission / reception between multiple devices and generation of an interrupt signal for any device And an interrupt control circuit for facilitating the operation.

[0008]

[Action]

 According to the present invention, in data transmission / reception between devices controlled by a microprocessor, a 2-port RAM required for data transmission / reception, a bidirectional data BUS signal, an address / control are provided in the communication I / F circuit. Since the BUS signal is provided, it is possible to perform data transmission / reception between a plurality of devices independently between any devices without the intervention of other devices, and between any devices. In addition to functioning to enable quick data exchange, even if an interrupt occurs between arbitrary devices, the provision of a control circuit for interrupt generation / reception enables interrupt processing between arbitrary devices. , So that rapid processing can be realized without using other devices.

[0009]

【Example】

 Example 1. An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a system block diagram of a communication I / F circuit according to this embodiment. In the figure, the same reference numerals as those in FIG. 4 indicate the same or corresponding parts, and detailed description thereof will be omitted. In the figure, 1a is a No. 1 channel (device) communication I / F circuit, 2a is a No. 2 channel (device) communication I / F circuit, 3a, 4a is No. 3, No. n channel (device) communication I / F circuit The F circuit has the same configuration as the circuit 2a. The circuits 1a and 2a have the same configuration, and the same reference numerals in the drawings denote the same or corresponding portions. Reference numeral 15a is a 2-PORT control circuit for controlling access 14 and 16a is a channel selection signal 20 from the channel selection circuit 17 and coincides with the sent address signal 21 to generate a channel valid signal 22. At the same time, a channel / interrupt control circuit for controlling the generation of the interrupt signal 19 to the microprocessor by the interrupt enable signal 24 from the 2-PORT control circuit of 15a, and 25 the microprocessor and other channels (devices). The data BUS driver for sending the data to the data BUS6 in order to access the 2-PORT RAM of the microprocessor, 26 is the data of the microprocessor for the microprocessor to access the 2-PORT RAM of the other channel (device). Signal, address signal, and control signal each containing 6 data BUS , 9 for the external BUS access valid signal for the address / control BUS, and is output from the 2-PORT control circuit 15a.

FIG. 2 is a diagram showing a specific example of a memory map of the 2-PORT RAM of each channel (device) and a channel allocation method in the present embodiment. 27 is a memory map and 28 is a specific allocation method. Here is an example. FIG. 3 shows the state of the addresses accessed by the 2-PORT RAM in the communication I / F circuit of each channel (device) in each microprocessor and each channel (device) in this embodiment. It is a figure. In the figure, the same reference numerals as those in FIG. 1 indicate the same or corresponding parts.

Next, the operation will be described. First, when transmitting and receiving data between No. 1 channel (device) and No. 2 channel (device), the microprocessor of No. 1 channel (device) is the No. 1 channel (device) of 1a. Communication I / F circuit data BUS driver / receiver 25, address / control bus driver 7, 2a No. 2 channel (device) Communication I / F circuit data BUS driver / receiver 5, address / control BUS receiver Attempt to access 14 2-PORT RAMs through 8. At this time, if the channel selection signal 20 selected in advance by the channel selection circuit 17 and the sent address signal 21 match, the channel / interruption control circuit 16a discriminates, and if they match. The channel valid signal 22 becomes valid and is sent to the 2-PORT control circuit of 15a, where the priority of the access right of 14-PORT RAM with the microprocessor of No. 2 channel (device) is determined. After that, access is enabled by the access signal 23 and data is transmitted and received.

The above procedure is a procedure for sending data from the No. 1 channel (device) to the No. 2 channel (device). The procedure for sending data to the No. 1 channel (device) will be described. No. 2 channel (device) microprocessor is No. 2 channel (device) communication 2a data I / F circuit data BUS driver / receiver 25, address / control bus driver 7, 1a No. 1 channel (device) ) Attempts to access 14 2-PORT RAM via the data BUS driver / receiver 5 and the address / control BUS receiver 8 of the communication I / F circuit. At this time, in the same way as when data is sent from the No. 1 channel (device) to the No. 2 channel (device), 14a of the 1a No. 1 channel (device) communication I / F circuit is used. Control is performed to access the 2-PORT RAM, and data is sent from No. 2 channel (device) to No. 1 channel (device). The same procedure is used to send and receive data between No. 1 channel (device) and No. 3 channel (device), or No. n channel (device). Various data can be transmitted and received. The data transmitted and received between a plurality of channels (devices) can be discriminated by the microprocessor of each channel (device) by referring to the contents of a predetermined area of the 2-PORT RAM. Run.

Next, the interrupt operation will be described. When an emergency interrupt factor occurs from the No. 2 channel (device) to the No. 1 channel (device), the micro processor of the No. 2 channel (device) uses 1a as in the case of data transmission / reception. An attempt is made to access a specific address in the 2-PORT RAM 14 of the No. 1 channel (device) communication I / F circuit.

At this time, the coincidence between the channel selection signal 20 previously selected by the channel selection circuit 17 and the sent address signal 21 is discriminated by the channel / interrupt control circuit 16a and coincides. If the channel valid signal 22 becomes valid, it is sent to the 2-PORT control circuit of 15a, where the priority of the access right of the 2-PORT RAM of 14 with the No. 1 channel (device) microprocessor is set. After the determination is made, the 2-PORT RAM of 14 is accessed by the access signal of 23, the specific address is determined by the 2-PORT RAM control circuit of 15a, and the interrupt enable signal of 24 is 16a. It is sent to the channel / interrupt control circuit and is used as an interrupt signal of 19 for the micro processor of No. 1 channel (device). When the microprocessor receives the interrupt signal, it accesses the specific address of the 2-PORT RAM of 14 of the No. 1 channel (device) communication I / F circuit, and the interrupt processing corresponding to the content of the data is sent. To execute. Interrupt operations between any devices such as No. 1 channel (device) and No. 3 channel (device), or No. n channel (device) are also performed by the same procedure. Interruption processing between arbitrary devices can be performed quickly.

Example 2. Although the case of n channels (devices) from No. 1 to No. n has been described, the number of channels (devices) may be two, and each channel (device) has a different microprocessor. Also in this case, the same effect can be obtained by making a slight change according to each control method.

[0016]

[Effect of the device]

 As described above, according to the present invention, in transmitting / receiving data between devices controlled by the microprocessor processing, the communication I / F circuit is independently provided with the 2-port RAM, and the data BUS signal, Since all signals such as address / control BUS signals are bidirectional and have the same configuration, data transmission / reception between a plurality of devices can be performed at high speed between any devices and also between any devices. Since interrupt processing can be performed quickly, the processing of the entire system can be improved.

[Brief description of drawings]

FIG. 1 is a system block diagram of a communication I / F circuit according to an embodiment of the present invention.

[Fig. 2] 2-P of each channel (device) in the present invention
It is the figure which showed the memory map of ORT RAM and the specific example of the allocation method of a channel.

FIG. 3 shows a 2-PORT RAM in a communication I / F circuit of each channel (device) in one embodiment of the present invention.
FIG. 3 is a diagram showing a state of addresses accessed from each microprocessor and each channel (device).

FIG. 4 is a system block diagram in a conventional communication I / F circuit.

[Explanation of symbols]

 1 No. 1 channel (device) communication I / F circuit 2 No. 2 channel (device) communication I / F circuit 3 No. 3 channel (device) communication I / F circuit 4 No. n channel (device) communication I / F circuit F circuit 5 data BUS driver / receiver 6 data BUS 7 address / control BUS driver 8 address / control BUS receiver 9 address / control BUS 10 interrupt signal receiver 11 interrupt signal driver 12 interrupt signal line 13 interrupt signal control circuit 14 2-PORT RAM 15 2-PORT control circuit 16 channel control circuit 17 channel selection circuit 18 interrupt signal generation circuit 19 interrupt signal 20 channel selection signal 21 address signal 22 channel valid signal 23 access signal 24 interrupt valid signal 1a No. 1 channel (device) communication I / F times 2a No. 2 channel (device) communication I / F circuit 3a No. 3 channel (device) communication I / F circuit 4a No. 32 channel (device) communication I / F circuit 15a 2-PORT control circuit 16a Channel control circuit 25 Data BUS driver 26 External BUS access valid signal 27 Memory map 28 Specific example of interrupt method

Claims (1)

Claims for utility model registration 1. When transmitting and receiving data between devices controlled by the processing of a microprocessor, the communication I / F circuit is independently provided with a 2-port RAM, and the data BUS is provided. Signals and address / control BUS signals are bidirectional so that data transmission / reception between multiple devices can be performed by a control circuit and generation of interrupt signals for any device. To facilitate. A communication I / F circuit comprising an interrupt control circuit.