JPH0540541A - Clock distribution circuit - Google Patents

Abstract

PURPOSE:To drive the load of large capacity at high speed, and in addition, to attain low power consumption by constituting a clock generation circuit which detects very small voltage difference and operates at high speed. CONSTITUTION:The amplitude of the output signals S1, S2 of the clock generation circuit 1 can be made a desired small amplitude by selecting properly the values of resistors R1, R2. Besides, a level conversion circuit 2 consists of two groups of BiCMOS NAND circuits, and the output of the NAND circuit of one side is connected to the input of the NAND circuit of the other side, and they are constituted so as to feed back the output to each other. As the result, the level conversion circuit 2 becomes of the same configuration as a circuit to latch data. Since the output signals S1, S2 are of small amplitude, the data of the level conversion circuit 2 is not fixed by only the output signals S1, S2, but because of latch configuration to feed back the output to each other, the data is fixed by the fed back signals.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock distribution circuit for distributing an LSI clock signal to each constituent circuit in a chip.

[0002]

2. Description of the Related Art In order to distribute an LSI clock signal to each constituent circuit in a chip, a method of arranging and supplying inverters on a tree is used. FIG. 3 shows a conventional example.
The clock generation circuit 4 is composed of a CMOS inverter circuit. Its logical amplitude is 5V. The output of the clock generation circuit 4 is connected to the input terminal of the inverting circuit 5. In this conventional example, an inverting circuit 5 is provided in order to supply two types of clocks whose phases are inverted. When a periodic pulse signal is supplied to the input terminal of the clock generation circuit 4, the clock signal whose phase is inverted by the inverting circuit and the signal that has not passed through the inverting circuit are supplied to each circuit.

[0003]

In the above-mentioned conventional example, the amplitude is as large as 5 V, so that high speed operation cannot be performed. Since the current drive capability of the MOS transistor is smaller than that of the bipolar transistor, the delay time is greatly affected by the load capacitance. Even if careful design is performed, it is not possible to make the loads of the clock signal lines of the respective constituent circuits equal to each other due to variations in processes and differences in wiring length. Therefore, it is difficult to reduce the clock skew between the constituent circuits. In addition, the current flowing during operation may cause noise in the power supply line, causing a malfunction. Further, interference with adjacent wirings and adjacent devices, that is, crosstalk, is likely to occur because the amplitude voltage is large.

An object of the present invention is to provide a clock distribution circuit which can be driven at high speed, has low power consumption, and has little clock skew and noise by reducing the voltage amplitude.

[0005]

In the clock distribution circuit of the first invention of the present application, the collector of the first bipolar transistor is connected to a high potential power supply through the first resistor, and the collector of the second bipolar transistor is connected. A second resistor connected to the high-potential power supply, and an emitter of the first bipolar transistor and an emitter of the second bipolar transistor connected to a low-potential power supply via a third resistor; 1 bipolar transistor base first
Input signal terminal, the base of the second bipolar transistor serves as a second input signal terminal, the first bipolar transistor serves as a first output signal terminal, and the collector of the second bipolar transistor serves as a second input signal terminal. A clock generation circuit serving as an output signal terminal, sources of the first MOS transistor and the second MOS transistor are connected to the high-potential power supply, and drains of the first MOS transistor and the second MOS transistor and a third The drain of the MOS transistor is connected to the base of the third bipolar transistor, the source of the third MOS transistor is connected to the drain of the fourth MOS transistor,
The source of the fourth MOS transistor is connected to a low potential power supply, the collector of the third bipolar transistor is connected to the high potential power supply, and the emitter of the third bipolar transistor is connected to the drain of the fifth MOS transistor. Connection, the source of the fifth MOS transistor and the drain of the sixth MOS transistor are connected, the source of the sixth MOS transistor is connected to a low potential power supply, the gate of the second MOS transistor and the Four
The MOS transistor gate and the sixth MOS transistor gate as the third input signal terminal, the third bipolar transistor emitter as the third output terminal, and the seventh MOS transistor and the eighth MOS transistor. The source of the transistor is connected to the high potential power source,
The MOS transistor, the drain of the eighth MOS transistor, the drain of the ninth MOS transistor, and the base of the fourth bipolar transistor are connected, and the source of the ninth MOS transistor and the drain of the MOS transistor are connected. The source of the tenth MOS transistor is connected to the low potential power source, the collector of the fourth bipolar transistor is connected to the high potential power source, and the emitter of the fourth bipolar transistor is connected to the eleventh MOS transistor. A drain and a source of the eleventh MOS transistor and a twelfth MOS
The drain of the transistor is connected to the 12th MOS.
The source of the transistor is connected to a low potential power source,
The gate of the MOS transistor, the gate of the tenth MOS transistor, and the gate of the twelfth MOS transistor as a fourth input signal terminal, and the emitter of the fourth bipolar transistor as a fourth output terminal,
The third output terminal, the gate of the seventh MOS transistor, the gate of the ninth MOS transistor, and the gate of the eleventh MOS transistor are connected to each other, and the fourth output terminal and the gate of the MOS transistor are connected to each other. The gate of the third MOS transistor and the fifth MOS
It is composed of a level conversion circuit that connects the gates of the transistors.

In the clock distribution circuit of the second invention of the present application, the collector of the first bipolar transistor is connected to the high-potential power supply via the first resistance, and the collector of the second bipolar transistor is connected via the second resistance. Is connected to the high potential power source, the emitter of the first bipolar transistor and the emitter of the second bipolar transistor are connected to the low potential power source through a third resistor, and the base of the first bipolar transistor is connected. As a first input signal terminal, and the base of the second bipolar transistor as a second input signal terminal.
, An input signal terminal, a collector of the first bipolar transistor serves as a first output signal terminal, and a collector of the second bipolar transistor serves as a second output signal terminal, and a thirteenth MOS transistor. The source of is connected to a high potential power source,
The drain of the transistor and the source of the fourteenth MOS transistor are connected to each other, and the drain of the fourteenth MOS transistor, the drain of the fifteenth MOS transistor and the first drain
The drain of the sixth MOS transistor is connected to the base of the fifth bipolar transistor, the collector of the fifth bipolar transistor is connected to a high potential power source, and the emitter of the fifth bipolar transistor is connected to the seventeenth MO transistor.
The drain of the S transistor is connected to the drain of the 18th MOS transistor, the source of the 15th MOS transistor, the source of the 16th MOS transistor, the source of the 17th MOS transistor, and the 1st
The source of the eighth MOS transistor is connected to a low potential power source, and the gate of the fourteenth MOS transistor, the gate of the sixteenth MOS transistor and the eighteenth MO transistor are connected.
The gate of the S transistor is used as a fifth input signal terminal, the emitter of the fifth bipolar transistor is used as a fifth output signal terminal, and the source of the 19th MOS transistor is connected to a high potential power source. The drain of the transistor and the source of the twentieth MOS transistor are connected, and the drain of the twentieth MOS transistor, the twenty-first MOS transistor drain, and the twenty-second MOS
The drain of the transistor is connected to the base of the sixth bipolar transistor, the collector of the sixth bipolar transistor is connected to a high potential power source, and the emitter of the sixth bipolar transistor is connected to the drain of the 23rd MOS transistor and the 24th Connected to the drain of the second MOS transistor, the source of the twenty-first MOS transistor, the source of the twenty-second MOS transistor, and the second transistor.
The source of the MOS transistor 3 and the 24th MOS
The source of the transistor is connected to a low potential power source, the twentieth transistor is connected to the gate of the MOS transistor and the twenty-second transistor.
The gate of the S transistor and the gate of the 24th MOS transistor serve as a sixth input signal terminal, the emitter of the sixth bipolar transistor serves as a sixth output signal terminal, and the fifth output terminal serves as the 19th A gate of a MOS transistor, a gate of the 21st MOS transistor, and a gate of the 23rd MOS transistor are connected to each other, and the sixth output terminal is connected to a gate of the 13th MOS transistor and a gate of the 15th MOS transistor. And a level conversion circuit connecting the gate of the seventeenth MOS transistor.

[0007]

In the present invention, the differential amplifier in which the emitters of the bipolar transistors are connected to each other constitutes a clock generation circuit which detects a minute voltage difference and operates at high speed, thereby driving a large capacity load at high speed. By reducing the voltage amplitude, not only high-speed driving but also the problem of crosstalk due to capacitive coupling and fluctuation of power supply voltage due to switching current can be solved. Further, before the clock is supplied to each of the constituent circuits synchronized by the clock, by providing the level conversion circuit constituted by using the bipolar transistor and the resistor, the voltage amplitude is increased to perform the logical operation with a large noise margin. be able to.

Further, the level conversion circuit is of the latch type so that the common current is cut and the electrode of low power consumption is achieved.

[0009]

Embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram showing an embodiment of the present invention. The first bipolar transistor Q1 which first inputs the clock signal CKI to the base, and the second clock signal CK2 which is complementary to the first clock signal are input to the base, and the emitter is the first bipolar transistor Q1. A second bipolar transistor Q2 connected to the first and second
Collectors of bipolar transistors Q1 and Q2 of
Between the first and second resistors R1 and R2, which are respectively connected to the respective power supply terminals, and between the emitters of the first and second bipolar transistors Q1 and Q2 and the second power supply terminal. And a resistor R3 of a third resistor R3 connected to the first resistor R3, and differentially amplifying the first and second clock signals CKI and CK2 to obtain the first and second bipolar transistors Q.
The first and second signals S from the collectors of Q1 and Q2, respectively.
A clock generation circuit 1 for outputting 1 and S2, and a first MO
The source of the S transistor T1, the source of the second MOS transistor T2, the drain of the third MOS transistor T3, and the base of the third bipolar transistor Q3 are connected to each other, and the drain of the first MOS transistor T1 and the second
The drain of the MOS transistor T2 and the collector of the third bipolar transistor Q3 are connected to the first power supply terminal, and the source of the third MOS transistor T3 and the fourth
The drain of the MOS transistor T4 of
Connecting the drain of the MOS transistor T5 and the emitter of the third bipolar transistor Q3,
The source of the transistor T5 and the drain of the sixth MOS transistor T6 are connected to each other, and the fourth MOS transistor T6 is connected.
4 and the source of the sixth MOS transistor T6 are connected to the second power supply terminal, the emitter of the third bipolar transistor Q3 serves as the first output terminal, the gate of the second MOS transistor T2, The gate of the fourth MOS transistor T4 and the sixth MOS transistor T6
Is used as the first input terminal, the source of the seventh MOS transistor T7, the source of the eighth MOS transistor T8, the drain of the ninth MOS transistor T9, and the fourth
Connect the base of the bipolar transistor Q4 of
The drain of the MOS transistor T7, the drain of the eighth MOS transistor T8, and the collector of the fourth bipolar transistor Q4 are connected to the first power supply terminal, and the source of the ninth MOS transistor T9 and the tenth MOS transistor are connected.
The drain of the transistor T10 is connected to the eleventh M
The drain of the OS transistor T11 and the emitter of the fourth bipolar transistor Q4 are connected to each other, and
The source of the transistor T11 and the drain of the twelfth MOS transistor T12 are connected, the source of the tenth MOS transistor T10 and the source of the twelfth MOS transistor T12 are connected to the second power supply terminal, and the fourth bipolar transistor is connected. The emitter of the transistor Q4 is used as the second output terminal, and the gate of the eighth MOS transistor T8, the gate of the tenth MOS transistor T10, and the twelfth M transistor are used.
The gate of the OS transistor T12 is used as the second input terminal, the first output terminal is connected to the gate of the seventh MOS transistor T7, the gate of the ninth MOS transistor T9 and the gate of the eleventh MOS transistor T11, The second output terminal is connected to the gate of the first MOS transistor T1, the gate of the third MOS transistor T3, and the fifth MO.
The first signal S1 is connected to the gate of the S-transistor T5.
Is input to the first input terminal and the second signal S2 is input to the second input terminal.

Output signals S1 and S2 of the clock generation circuit 1
The amplitude of can be determined by properly selecting the values of resistors R1 and R2.
It can have a desired small amplitude. The level conversion circuit 2 is composed of two sets of BiCMOS NAND circuits, and the output of one NAND circuit is connected to one input of the other NAND circuit so that the outputs are fed back to each other. As a result, the level conversion circuit 2 has the same structure as the circuit for latching data. Since S1 and S2 have low amplitudes, the level conversion circuit 2 cannot determine the data only by S1 and S2, but the latch configuration in which the outputs are fed back mutually determines the data by the signal fed back. By the same direction, the level conversion circuit can be realized without a through current.

FIG. 2 is a circuit diagram showing another embodiment of the present invention. A first bipolar transistor Q1 that first inputs the clock signal CKI to the base, and a second clock signal CK that is complementary to the first clock signal CK to the base.
2 and a second bipolar transistor Q2 whose emitter is connected to the first bipolar transistor;
And first and second resistors R1 and R2 respectively connected between the collectors of the second bipolar transistors Q1 and Q2 and the first power supply terminal, and the first and second resistors R1 and R2, respectively.
Of the bipolar transistors Q1 and Q2 and the second
And a third resistor R3 connected between the first and second clock signals CKI and CK2 by differentially amplifying the first and second clock signals CKI and CK2.
The first and second signals S from the collectors of Q1 and Q2, respectively.
A clock generation circuit 1 for outputting 1 and S2, and a fifteenth M
The drain of the OS transistor T15, the drain of the sixteenth MOS transistor T16, the source of the fourteenth MOS transistor T14, and the fifth bipolar transistor Q.
The base of 5 is connected, and the thirteenth MOS transistor T1
The source of the third MOS transistor T14 is connected to the drain of the fourteenth MOS transistor T14, the drain of the seventeenth MOS transistor T17 is connected to the drain of the eighteenth MOS transistor T18, and the emitter of the fifth bipolar transistor Q5 is connected. The drain of the MOS transistor T13 and the collector of the fifth bipolar transistor Q5 are connected to the first power supply terminal, the source of the fifteenth MOS transistor T15, the source of the sixteenth MOS transistor T16 and the seventeenth MOS transistor T17. The source and the source of the eighteenth MOS transistor T18 are connected to the second power supply terminal, and the fifth bipolar transistor Q
And the gate of the fourteenth MOS transistor T14, the gate of the sixteenth MOS transistor T16, and the eighteenth MOS transistor T18.
Is used as the third input terminal, and the drain of the 21st MOS transistor T21, the drain of the 22nd MOS transistor T22, and the 20th MOS transistor T20 are used.
Is connected to the base of the sixth bipolar transistor Q6, the source of the 19th MOS transistor T19 is connected to the drain of the 20th MOS transistor T20, and the drain of the 23rd MOS transistor T23 is connected to the 24th MOS. The drain of the transistor T24 and the emitter of the sixth bipolar transistor Q6 are connected to each other, and
The drain of the ninth MOS transistor T19 and the collector of the sixth bipolar transistor Q6 are connected to the first power supply terminal, and the source of the 21st MOS transistor T21, the source of the 22nd MOS transistor T22, and the 23rd MOS are connected. The source of the transistor T23 and the 24th M
The source of the OS transistor T24 is connected to the second power supply terminal, the emitter of the sixth bipolar transistor Q6 is used as the fourth output terminal, and the gate of the twentieth MOS transistor T20 and the gate of the twenty-second MOS transistor T22 are connected. The gate of the 24th MOS transistor T24 is used as the fourth input terminal, and the third output terminal is used as the 19th MOS.
The gate of the transistor T19, the gate of the 21st MOS transistor T21, and the gate of the 23rd MOS transistor T23 are connected to each other, and the fourth output terminal is connected to the gate of the 13th MOS transistor T13 and the 15th MOS.
The gate of the transistor T15 and the gate of the seventeenth MOS transistor T17 are connected to each other, and the first input signal S1
To the third input terminal and the second signal S2 to the fourth input terminal.

Output signals S1 and S2 of the clock generation circuit 1
The amplitude of can be determined by properly selecting the values of resistors R1 and R2.
It can have a desired small amplitude. The level conversion circuit 3 is composed of two sets of BiCMOS NOR circuits. The output of one NOR circuit is connected to the input of the other NOR circuit, and the outputs are fielded back to each other. As a result, the level conversion circuit 3 has the same configuration as the circuit for latching data. Since S1 and S2 have low amplitudes, the level conversion circuit 3 cannot determine the data only by S1 and S2, but the latch configuration in which the outputs are fed back mutually determines the data by the signal fed back. By the same method, the level conversion circuit can be realized without through current.

[0013]

As described above, according to the present invention, a clock generating circuit which detects a minute voltage difference and operates at high speed is constructed, a large capacity load is driven at high speed, and a voltage amplitude is reduced. By doing so, not only high-speed driving but also the problem of crosstalk due to capacitive coupling and fluctuation of power supply voltage due to switching current can be solved. Also, by making the level conversion circuit a latch type, the through current is reduced,
Low power consumption can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram of a clock distribution circuit showing a first embodiment of the present invention.

FIG. 2 is a clock generation circuit diagram showing a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a conventional example.

[Explanation of symbols]

1,4 Clock generation circuit 2,3 Level conversion circuit 5 Inversion circuit R1, R2, R3 First, second and third resistors Q1, Q2, Q3, Q4, Q5, Q6 Bipolar transistor T1, T28 MOS transistor

Claims (2)

[Claims] 1. A collector of a first bipolar transistor is connected to a high potential power source via a first resistor, and a collector of a second bipolar transistor is connected to the high potential power source via a second resistor, The emitter of the first bipolar transistor and the emitter of the second bipolar transistor are connected to a low potential power source through a third resistor, and the base of the first bipolar transistor serves as a first input signal terminal. A base of the second bipolar transistor serves as a second input signal terminal, a collector of the first bipolar transistor serves as a first output signal terminal, and a collector of the second bipolar transistor serves as a second output signal terminal. And a first M
The sources of the OS transistor and the second MOS transistor are connected to the high potential power source, and the drains of the first MOS transistor, the second MOS transistor and the third MOS transistor are connected.
The drain of the MOS transistor is connected to the base of the third bipolar transistor, the source of the third MOS transistor is connected to the drain of the fourth MOS transistor, and the source of the fourth MOS transistor is connected to the low potential power source. Connection, the collector of the third bipolar transistor is connected to the high-potential power supply, the emitter of the third bipolar transistor is connected to the drain of the fifth MOS transistor, and the source of the fifth MOS transistor is connected to the source of the fifth MOS transistor. The drain of the sixth MOS transistor is connected, the source of the sixth MOS transistor is connected to a low potential power source, the gate of the second MOS transistor, the gate of the fourth MOS transistor, and the sixth MOS transistor.
Of the MOS transistor is used as a third input signal terminal, the emitter of the third bipolar transistor is used as a third output terminal, and the sources of the seventh MOS transistor and the eighth MOS transistor are connected to the high potential power source. The seventh MOS transistor and the eighth MOS
The drain of the transistor, the drain of the ninth MOS transistor and the base of the fourth bipolar transistor are connected, and the source of the ninth MOS transistor and the tenth
Connecting the drain of the MOS transistor of
The source of the MOS transistor of is connected to the low potential power supply,
The collector of the fourth bipolar transistor is connected to the high potential power source, the emitter of the fourth bipolar transistor is connected to the drain of the eleventh MOS transistor, the source of the eleventh MOS transistor and the twelfth MOS transistor. A drain of the transistor is connected, a source of the twelfth MOS transistor is connected to a low potential power source, a gate of the eighth MOS transistor and the first
0 MOS transistor gate and the twelfth MO transistor
The gate of the S transistor serves as a fourth input signal terminal, the emitter of the fourth bipolar transistor serves as a fourth output terminal, the third output terminal, the gate of the seventh MOS transistor, and the ninth MOS. A level connecting the gate of the transistor and the gate of the eleventh MOS transistor, and connecting the fourth output terminal, the gate of the MOS transistor, the gate of the third MOS transistor and the gate of the fifth MOS transistor. A clock distribution circuit comprising a conversion circuit. 2. A collector of the first bipolar transistor is connected to a high potential power source via a first resistor, and a collector of a second bipolar transistor is connected to the high potential power source via a second resistor, The emitter of the first bipolar transistor and the emitter of the second bipolar transistor are connected to a low potential power supply via a third resistor, and the base of the first bipolar transistor is connected to the first potential source.
Input signal terminal, the base of the second bipolar transistor is the second input signal terminal, the collector of the first bipolar transistor is the first output signal terminal, and the collector of the second bipolar transistor is the second A clock generation circuit that serves as an output signal terminal of the second MOS transistor and a source of the thirteenth MOS transistor are connected to a high potential power source, and the drain of the thirteenth MOS transistor and the fourteenth M transistor are connected.
The source of the OS transistor is connected, and the 14th MO is connected.
The drain of the S transistor, the drain of the fifteenth MOS transistor, the drain of the sixteenth MOS transistor, and the base of the fifth bipolar transistor are connected to each other, and the collector of the fifth bipolar transistor is connected to a high potential power source. The emitter of the bipolar transistor is connected to the drains of the seventeenth MOS transistor and the drain of the eighteenth MOS transistor, the source of the fifteenth MOS transistor, the source of the sixteenth MOS transistor and the seventeenth MOS transistor. The source and the source of the eighteenth MOS transistor,
A gate of the fourteenth MOS transistor, a gate of the sixteenth MOS transistor and a gate of the eighteenth MOS transistor as a fifth input signal terminal connected to a low potential power source, and an emitter of the fifth bipolar transistor. As a fifth output signal terminal, the source of the nineteenth MOS transistor is connected to a high potential power source, the drain of the nineteenth MOS transistor is connected to the source of the twentieth MOS transistor, and the twentieth MOS transistor is connected. The drain of the MOS transistor, the drain of the 21st MOS transistor, the drain of the 22nd MOS transistor and the base of the sixth bipolar transistor are connected, and the collector of the sixth bipolar transistor is connected to a high potential power source.
The emitter of the sixth bipolar transistor is connected to the 23rd
Connected to the drain of the MOS transistor and the drain of the 24th MOS transistor, the source of the 21st MOS transistor, the source of the 22nd MOS transistor, the source of the 23rd MOS transistor, and the 24th MOS transistor. Is connected to a low potential power source, and the gate of the 20th MOS transistor, the gate of the 22nd MOS transistor and the 24th MOS transistor are connected.
The gate of the MOS transistor of is used as a sixth input signal,
The emitter of the sixth bipolar transistor is the sixth output signal terminal, and the fifth output terminal is the gate of the nineteenth MOS transistor, the gate of the twenty-first MOS transistor, and the gate of the twenty-third MOS transistor. And the thirteenth M of the sixth output terminal.
A clock distribution circuit comprising a level conversion circuit that connects the gate of an OS transistor, the gate of the fifteenth MOS transistor, and the gate of the seventeenth MOSS transistor.