JPH0535361A - Clock distributing circuit - Google Patents

Abstract

PURPOSE:To provide the clock distributing circuit which enables high-speed driving, reduces clock skew and further resolves the problem of power supply voltage fluctuation caused by cross talk or switching currents due to capacitance coupling. CONSTITUTION:A clock generating circuit 1 is composed of a differential amplifier so as to detect fine voltage difference and to be operated at high speed, high-speed driving is executed by reducing a voltage amplitude, and the problem of power supply voltage fluctuation caused by crosstalk or switching currents due to capacity coupling is resolved. Further, before the clock is supplied to respective constitutive circuits synchronized by the clock, it is passed through a level conversion circuit 2 so as to increase the voltage amplitude and to enable logical operations having large noise tolerance.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock distribution circuit for distributing a clock signal to each constituent circuit, and more particularly to an L distribution circuit.
The present invention relates to a clock distribution circuit provided on an SI chip.

[0002]

2. Description of the Related Art In order to distribute an LSI clock signal to each constituent circuit in a chip, a method of arranging and supplying inverters in a tree shape is often used. FIG. 2 is a circuit diagram showing an example of a conventional clock distribution circuit. Referring to FIG. 2, this clock distribution circuit is composed of three clock generation circuits 3, 4 and 5. Then, the input clock signal CK is distributed to each constituent circuit (not shown) in the LSI chip while being inverted and amplified. The clock generation circuit is composed of a CMOS inverter. These logic amplitudes are as large as 3V to 5V.

[0003]

In the conventional clock distribution circuit described above, the following occurs due to the large amplitude of 3V to 5V. First, it is difficult to operate at high speed. Since the current drive capability of the MOS transistor is smaller than that of the bipolar transistor, the delay time is greatly affected by the load capacitance. Even if careful design is performed, it is not possible to completely equalize the loads of the clock signal lines to the respective constituent circuits due to process variations and wiring length differences. Therefore, it is difficult to reduce the clock skew between the constituent circuits. In addition, noise may be generated in the power supply line due to the current flowing during operation, resulting in malfunction. Further, interference with adjacent wirings and adjacent devices, that is, noise due to crosstalk and inductance is likely to occur because the amplitude voltage is large. Further, when two-phase clocks with inverted phases are generated, a delay occurs between the two clocks. That is, clock skew occurs. An object of the present invention is to provide a clock distribution circuit which can be driven at a high speed and has a small clock skew and noise while ensuring a large noise margin.

[0004]

SUMMARY OF THE INVENTION A clock distribution circuit of the present invention is a clock generation circuit comprising an operational amplifier which receives two clock signals which are in a complementary relationship with each other, and an output signal of at least one of the clock generation circuits. And a level conversion circuit which supplies the voltage amplitude to the circuit synchronized with the input clock signal.

[0005]

According to the present invention, a differential amplifier in which the emitters of bipolar transistors are connected to each other constitutes a clock generation circuit which detects a minute voltage difference and operates at high speed. By reducing the voltage amplitude of the output signal of the output circuit of the clock generation circuit, not only high-speed driving but also the problem of crosstalk due to capacitive coupling and fluctuation of power supply voltage due to switching current are solved. Furthermore,
Before the clock signal is supplied to each of the constituent circuits synchronized by the clock, the level conversion circuit is used to increase the voltage amplitude and perform a logical operation with a large noise margin.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an optimum embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram of an embodiment of the present invention. Referring to FIG. 1, the present embodiment includes a first base
The first clock signal CK1 and the second clock signal CK2 having a complementary relationship with the first clock signal CK1 are input to the base.
A second bipolar transistor Q whose emitter is commonly connected to the emitter of the first bipolar transistor Q1.
2 and the first and second bipolar transistors Q1 and Q
A first and a second resistor R connected between the collector of 2 and the high-potential power supply terminal (power supply voltage Vcc) 6 respectively.
1, R2 and a third resistor R3 connected between the emitters of the first and second bipolar transistors Q1 and Q2 and the localization power supply terminal 7, and the first and second bipolar transistors Q1 and Q2. Of the third bipolar transistor Q3 are connected to the bases of the third and fourth bipolar transistors Q3 and Q4, respectively.
The collectors of Q3 and Q4 are connected to the high-potential power supply terminal 6, and the first and second clock signals CK1 and CK2 are differentially amplified to
From the collectors of the first and second bipolar transistors Q1 and Q2, via the third and fourth bipolar transistors Q3 and Q4, respectively, and first and second signals S1 and S2.
Of the signals S1 and S2 of the clock generator circuit, and the first and second signals S from the clock generator circuit 1 to the base.
The fifth and sixth bipolar transistors Q5 and Q6, to which the first and the second transistors S1 and S2 are respectively input, and whose emitters are both connected to the low power supply terminal 7, and the fifth and sixth bipolar transistors Q5 and Q6, respectively.
Collectors of transistors Q5 and Q6 and high-level power supply terminal 6
And a fourth and a fifth resistor R4, R5, which are connected to the low potential power supply terminal 7 and the emitters of the fifth and sixth transistors Q5, Q6, respectively. Sixth and seventh resistors R connected correspondingly
6 and R7, and a level conversion circuit 2 for expanding the amplitude of the first signal S1 or the second signal S2 and supplying it to a constituent circuit (not shown) synchronized by the clock signal CK1 or the clock signal CK2. It is a structure having.

In this embodiment, the clock generation circuit 1 is arranged in each part on the LSI chip and used as a clock generation circuit according to the load state due to wiring and fan-out. Clock signal S generated by the clock generation circuit
1 and S2 are low voltage swings. This enables high speed operation and reduces clock skew. Also,
Crosstalk due to capacitive coupling and power supply noise due to switching current can be reduced. Further, a level conversion circuit 2 is provided in front of each constituent circuit, and the low voltage amplitude clock is converted into a large voltage amplitude clock here. As a result, the signal S whose level has been converted in each constituent circuit and whose amplitude has increased becomes
1 or the signal S2 can be used as a clock input to operate at a large voltage, so a large noise margin can be secured.
Moreover, it is possible to reduce the power consumption by making the circuit configuration a CMOS configuration.

In the above embodiment, the transistors Q3 and Q4 of the clock generation circuit 1 are
This is an emitter follower that acts as a buffer for lowering the output impedance of the clock generation circuit 1 and increasing adaptation to load fluctuations.
It does not depend on the presence or absence of these transistors.

Further, in the present embodiment, as the level conversion circuit, the one in which the resistor, the bipolar transistor and the resistor are connected in series between the high potential power supply terminal 6 and the low potential power supply terminal 7 is used. Is not limited to this. Other type level conversion circuits, for example, edited by Seiji Kubo, B
Even a level conversion circuit for converting a low voltage amplitude signal into a large voltage amplitude signal using a current mirror circuit, as described in iCMOS technology, p. 48, Corona (1990), etc. Of course good things.

[0010]

As described above, according to the present invention, a clock generation circuit which detects a minute voltage difference and operates at high speed is constructed, a large capacity load is driven at high speed, and a voltage amplitude is reduced. By doing so, not only high-speed driving but also the problem of crosstalk due to capacitive coupling and fluctuation of power supply voltage due to switching current can be solved.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a clock distribution circuit according to an embodiment of the present invention.

FIG. 2 is a circuit diagram of an example of a conventional clock distribution circuit.

[Explanation of symbols]

1, 3, 4, 5, Clock generation circuit 2 Level conversion circuit 6 High power supply terminal 7 Low power supply terminal Q1, Q2, Q3, Q4, Q5, Q6 Bipolar transistor R1, R2, R3, R4, R5, R6, R7 Resistance

Claims (2)

[Claims] 1. A clock generation circuit comprising a differential amplifier which inputs two clock signals which are complementary to each other, and a voltage amplitude of at least one output signal of the clock generation circuit is expanded to obtain a clock of the input clock. A level conversion circuit for supplying a circuit synchronized with a signal, the clock distribution circuit. 2. A first power supply having a collector connected to a high power supply terminal via a first resistor, a base connected to a first signal input terminal, and an emitter connected to a low power supply terminal via a second resistor. A bipolar transistor, and a second bipolar transistor having a collector connected to a high-potential power supply terminal through a third resistor, a base connected to a second signal input terminal, and an emitter connected to the emitter of the first bipolar transistor. A third bipolar transistor having a collector connected to the high-potential power supply terminal and a base connected to the collector of the first bipolar transistor; and a collector connected to the high-potential power supply terminal and a base connected to the collector of the second bipolar transistor. Clock generator circuit consisting of a fourth bipolar transistor and a collector Connected to the high-potential power supply terminal, the emitter is connected to the low-potential power supply terminal through the fifth resistor, and the base is connected to one of the emitter of the third bipolar transistor and the emitter of the fourth bipolar transistor. A level conversion circuit formed of a fifth bipolar transistor, the first clock signal is input to the first signal input terminal, and the first clock signal is input to the second signal input terminal. Is connected so that a second clock signal having a complementary relationship with is input.