JPH0536977A - Switching element - Google Patents

Abstract

PURPOSE:To reduce the P gate junction capacitance of a switching element and to increase the dV/dt strength of the element. CONSTITUTION:P gate diffused regions P3 and P4, in which an impurity is diffused shallow, are respectively provided on the insides of P gate diffused regions P1-1 and P2-1, which are formed in the surface of an N-type substrate 1 and wherein an impurity is diffused deep, and regions, wherein an impurity is not diffused, are provided at parts, where oblique lines are drawn, of the regions P3 and P4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a photo thyristor,
The present invention relates to a structure of a switching element such as a photo triac, a thyristor, and a triac, which has high sensitivity and high dV / dt resistance.

[0002]

2. Description of the Related Art A lateral photo triac will be described below as an example of a switching element. FIG. 3 is a schematic plan view of an example of a conventional structure.
Is a schematic sectional view thereof. On the surface of the N-type substrate 1, the P-type P-gate diffusion regions P1 and P including the N-type cathode diffusion regions K1 and K2 are symmetrically provided inside.
2 are formed in pairs, and P-type anode diffusion regions A1 and A2 respectively corresponding to the outside and P-type gate resistance R
_GK1 and R _GK2 are formed. Further, on the back surface of the N-type substrate 1, at the same time as the cathode diffusion, the cathode diffusion region K1 is formed.
And the N-type diffusion region 2 having the same concentration as K2 is formed over the entire surface.

The concentration of the N-type substrate 1 is generally 10 ¹³
It is -10 ¹⁵ cm ^-3 . The terminals T1 and T2 are connection terminals to an external circuit, and the terminal T1 is connected to the anode diffusion region A1 and the cathode diffusion region K2. Further, the terminal T2 is connected to the anode diffusion region A2 and the cathode diffusion region K1.

The anode diffusion region A1 and the P gate diffusion region P2 are connected by a gate resistance R _GK2 , and the anode diffusion region A2 and the P gate diffusion region P1 are connected by a gate resistance R _GK1 .

Each of the diffusion layers of the anode diffusion regions A1 and A2 and the P gate diffusion regions P1 and P2 has a depth of about 10 mm.
50 microns, a surface concentration of about 10 ¹⁶ ~10 ¹⁸ cm ^-3. Each of the diffusion layers in the cathode diffusion regions K1 and K2 has a depth of 3 to 15 μm and a surface concentration of about 10 ²⁰ to 10 ^21.
cm ^-3 .

As described above, a triac is composed of two sets of thyristors having a PNPN structure.

[0007]

However, the conventional structure has the following problems.

The P-gate diffusion regions P1 and P2 have a large light-receiving area for the purpose of increasing the sensitivity. However, if this is done, the junction capacitance C _{jPG of the} P-gate becomes large and dV / dt.
The withstand capacity becomes low. That is, when a steep rising voltage is applied between the anode and the cathode, the P gate junction becomes reverse biased, and the displacement current C _passes through this junction capacitance C _{jPG.
Since jPG} · dV / dt flows and malfunctions, the larger the P gate junction capacitance C _jPG , the lower the dV / dt withstand capability.

[0009]

In the present invention, a region in which impurities are not diffused is provided in a part of the P gate diffusion region.

[0010]

By providing a region where impurities are not partially diffused in a part of the P gate diffusion region, the P gate junction capacitance is reduced and the dV / dt withstand capability is improved.

Regarding the photosensitivity, there is a region where impurities are not partially diffused, but since light is picked up from the P gate diffusion region around the region, the photosensitivity equivalent to the conventional one can be maintained.

[0012]

FIG. 1 is a plan view of an embodiment of the present invention,
FIG. 2 is a sectional view thereof.

The N-type substrate 1 is, for example, an N-type silicon single crystal having an impurity concentration of 10 ¹³ to 10 ¹⁵ cm ^-3 . On the surface of the N-type substrate 1, the anode diffusion regions A1 and A2 and the deep P diffusion region P are diffused symmetrically.
1-1 and P2-1 are simultaneously formed using boron as an impurity. These shapes are, for example, frame-shaped and do not diffuse inside. The diffusion layer has a depth of about 20 to 50.
Micron, surface concentration is about 10 ¹⁶ to 10 ¹⁸ cm ⁻³ .

Next, gate resistances R _GK1 and R _GK2 are provided on the outside thereof, and shallow diffusion P gate diffusion regions P3 and P4 (shown by broken lines) are provided inside the P gate diffusion regions P1-1 and P2-1. Are simultaneously formed as impurities.
Part of the outside of the P gate diffusion regions P3 and P4 partially overlaps with the P gate diffusion regions P1-1 and P2-1. At this time, the P gate diffusion regions P3 and P4 are surrounded by the frame-shaped P gate diffusion regions P1-1 and P2-1 between the solid line portion and the broken line portion and surrounded by the broken line. , The part that is not diffused (shown with diagonal lines)
There is.

The diffusion layer has a depth of about 3 to 15 microns and a surface concentration of about 10 ¹⁶ to 10 ¹⁸ cm ^-3 .

These shallow diffusion P gate diffusion regions P3
And P4 inside the cathode diffusion regions K1 and K2.
And the N-type diffusion region 2 is simultaneously formed on the back surface of the N-type substrate 1. The diffusion layer has a predetermined sensitivity and dV /
To obtain dt, set the depth and surface concentration to the desired values.

The anode diffusion region A1 and the P gate diffusion regions P2-1 and P4 are connected by a gate resistance R _{GK 2} , and the anode diffusion region A2 and the P gate diffusion region P1-.
1, P3 are connected by a gate resistor R _GK1 .

For forming these diffusion regions, a thermal diffusion method, an ion implantation method, a doped C / V / D method or the like is used.

Although not shown, the electrode wiring is formed by selectively etching an Al film deposited on the surface of the N-type substrate 1. The terminal T1 is connected to the anode diffusion region A1 and the cathode diffusion region K2, and the terminal T2 is connected to the anode diffusion region A2.
And the cathode diffusion region K1.

[0020]

According to the present invention, it is possible to obtain a switching element which maintains the same photosensitivity as the conventional one and has a high dV / dt resistance.

[Brief description of drawings]

FIG. 1 is a plan view of an embodiment of the present invention.

FIG. 2 is a cross-sectional view of FIG.

FIG. 3 is a plan view of a conventional example.

FIG. 4 is a cross-sectional view of FIG.

[Explanation of symbols]

1 N-type substrate 2 N-type diffusion region A1, A2 Anode diffusion region P1-1, P2-1, P3, P4 P Gate diffusion region K1, K2 Cathode diffusion region R _GK1 , R _GK2 Gate resistance T1, T2 terminal

Claims (1)

Claim: What is claimed is: 1. A switching element comprising: a P-gate diffusion region formed on a surface of an N-type semiconductor substrate; and a region in which impurities are not diffused.