JPH0536746A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0536746A JPH0536746A JP3209859A JP20985991A JPH0536746A JP H0536746 A JPH0536746 A JP H0536746A JP 3209859 A JP3209859 A JP 3209859A JP 20985991 A JP20985991 A JP 20985991A JP H0536746 A JPH0536746 A JP H0536746A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- resin
- film
- insulating film
- island
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体ウエハにトランジ
スタなどの素子を形成し、半導体集積回路装置チップご
とにウエハを切断した半導体装置に関するものである。
本発明はまた、チップに切断された半導体集積回路装置
を樹脂封止法により封止した半導体装置実装体に関する
ものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which elements such as transistors are formed on a semiconductor wafer and the wafer is cut into individual semiconductor integrated circuit device chips.
The present invention also relates to a semiconductor device package in which a semiconductor integrated circuit device cut into chips is sealed by a resin sealing method.
【０００２】[0002]
【従来の技術】半導体集積回路装置（以下ＩＣという）
はシリコンウエハにウエハプロセスによってトランジス
タなどの素子が形成され、チップごとに切断されたもの
である。切断されて得られたＩＣチップは樹脂封止その
他の封止法により封止される。その際、図１に示される
ように、ＩＣチップ２は例えばリードフレームのアイラ
ンド部４にダイボンディングされ、リードフレームのイ
ンナーリード６との間にワイヤ８によりボンディングが
なされる。ＩＣチップ２の表面には素子が形成されてい
るが、その周辺部はウエハを各チップに切断する際のダ
イシングラインであったため、基板が露出した状態にな
っている。そのため、ワイヤ８が垂れ下がってＩＣチッ
プ２の基板エッジと接触して電気的な短絡を起こす不良
が発生することがある。その対策として、ワイヤ８に絶
縁被覆を設けた金ワイヤを使用したり、ワイヤ８の長さ
を短かくするようにＩＣチップ２のボンディングパッド
のレイアウトを設計したり、リードフレーム６を設計す
ることにより対応している。2. Description of the Related Art Semiconductor integrated circuit devices (hereinafter referred to as ICs)
Is a device in which elements such as transistors are formed on a silicon wafer by a wafer process and cut into chips. The IC chip obtained by cutting is sealed by resin sealing or another sealing method. At that time, as shown in FIG. 1, the IC chip 2 is die-bonded to the island portion 4 of the lead frame, for example, and is bonded to the inner lead 6 of the lead frame by the wire 8. Elements are formed on the surface of the IC chip 2, but the peripheral portion of the IC chip 2 is a dicing line for cutting the wafer into chips, so that the substrate is exposed. Therefore, the wire 8 may hang down and come into contact with the substrate edge of the IC chip 2 to cause an electrical short circuit. As a countermeasure, use of a gold wire provided with an insulation coating on the wire 8, design the layout of the bonding pad of the IC chip 2 so as to shorten the length of the wire 8, or design the lead frame 6. Is supported by.
【０００３】ＩＣチップ２を樹脂封止する方法として、
図２に示されるようなトランスファモールド法が主流を
なしている。トランスファモールド法では、リードフレ
ーム１０にＩＣチップ２をボンディングし、ＩＣチップ
２を含む領域を上型１２と下型１４で囲い、型１２，１
４の樹脂封入口１８から樹脂を注入する。型１２，１６
とリードフレーム１０の間には、樹脂注入口と反対側に
エアーベントと称される空気抜き用の溝１８が設けられ
ている。As a method of resin sealing the IC chip 2,
The transfer mold method as shown in FIG. 2 is predominant. In the transfer molding method, the IC chip 2 is bonded to the lead frame 10, and the region including the IC chip 2 is surrounded by the upper die 12 and the lower die 14 to form the die 12, 1.
Resin is injected from the resin sealing port 18 of 4. Mold 12, 16
Between the lead frame 10 and the lead frame 10, an air vent groove 18 called an air vent is provided on the side opposite to the resin injection port.
【０００４】上型１２と下型１４は同一形状をしてお
り、モールド成型時に注入される樹脂は下型１４のフレ
ーム面に接しながら注入され、内部では上型１２と下型
１４に沿って同時に流れ、エアーベンド１８から空気を
押し出しながら型１２と１４の内部を密封する。このと
き、型内部での樹脂の流れ速度はチップ２の側面の大き
さ（チップサイズやアイランドサイズ）により左右され
る。つまり、実装するＩＣチップ２のサイズにより型内
で上型１２側と下型１４側とで樹脂の流れ速度のバラン
スが崩れ、アイランド４が上下に浮き沈みして不良が発
生することがある。その傾向としては、ＩＣチップ２の
サイズがアイランド４のサイズより小さいときには上型
側の樹脂速度の方が下型側の樹脂速度より大きくなって
アイランド４が引き上がる傾向があり、逆にＩＣチップ
２のサイズがアイランド４のサイズより大きいときには
下型側の樹脂速度の方が上型側の樹脂速度より大きくな
ってアイランド４が沈む傾向があり、ＩＣチップ２のサ
イズとアイランド４のサイズが等しいときに樹脂速度は
上型側と下型側で等しくなってアイランド４の上下方向
の浮き沈みがなくなる。そのため、注入する樹脂の温
度、圧力又は注入時間などの注入条件や、注入する樹脂
の特性を変更してアイランドの浮き沈みを少なくした
り、リードフレーム４のサイズに合わせてＩＣチップ２
のサイズを設計するなどの方法をとっている。The upper mold 12 and the lower mold 14 have the same shape, and the resin injected during molding is injected while being in contact with the frame surface of the lower mold 14, and inside the upper mold 12 and the lower mold 14. At the same time, air is forced out of the air bend 18 to seal the inside of the molds 12 and 14. At this time, the flow velocity of the resin inside the mold depends on the size of the side surface of the chip 2 (chip size or island size). That is, depending on the size of the IC chip 2 to be mounted, the balance of the resin flow speed between the upper mold 12 side and the lower mold 14 side may be lost in the mold, and the island 4 may rise and fall up and down to cause a defect. The tendency is that when the size of the IC chip 2 is smaller than the size of the island 4, the resin speed on the upper die side becomes higher than the resin speed on the lower die side, and the island 4 tends to be pulled up. When the size of 2 is larger than the size of the island 4, the resin speed on the lower mold side is higher than the resin speed on the upper mold side, and the island 4 tends to sink, and the size of the IC chip 2 is equal to the size of the island 4. At this time, the resin speed becomes equal on the upper mold side and the lower mold side, and ups and downs of the island 4 disappear. Therefore, the injection conditions such as the temperature, pressure, and injection time of the resin to be injected and the characteristics of the resin to be injected are changed to reduce the ups and downs of the island, and the IC chip 2 is adjusted according to the size of the lead frame 4.
The size of the design is taken.
【０００５】[0005]
【発明が解決しようとする課題】本発明の第１の目的
は、ワイヤボンディングされるＩＣチップにあって、そ
のＩＣチップのエッジとワイヤとの短絡による不良をな
くすことである。本発明の第２の目的は、トランスファ
モールド法による樹脂封止実装体にあって、樹脂を型内
に注入する際のアイランドの上下方向の浮き沈みを少な
くした実装体を提供することである。SUMMARY OF THE INVENTION A first object of the present invention is to eliminate defects in an IC chip to be wire-bonded due to a short circuit between the edge of the IC chip and the wire. A second object of the present invention is to provide a resin-sealed mounting body by the transfer molding method, in which the ups and downs of islands when the resin is injected into the mold are reduced.
【０００６】[0006]
【課題を解決するための手段】本発明のＩＣチップで
は、素子が形成されている表面の周辺部に絶縁膜が形成
されている。好ましい態様では、ＩＣチップ周辺部の絶
縁膜の少なくとも最上層が透明樹脂層である。本発明の
実装体では、ＩＣチップがダイボンディングされている
アイランド部の周辺部にチップ側に突出した凸部が設け
られている。In the IC chip of the present invention, an insulating film is formed on the peripheral portion of the surface on which the element is formed. In a preferred aspect, at least the uppermost layer of the insulating film around the IC chip is a transparent resin layer. In the mounted body of the present invention, the convex portion protruding toward the chip is provided in the peripheral portion of the island portion to which the IC chip is die-bonded.
【０００７】[0007]
【作用】ＩＣチップの周辺部に絶縁膜が形成されている
ので、ボンディング用のワイヤが垂れ下がってＩＣチッ
プのエッジと接触しても、その絶縁膜によってワイヤと
ＩＣチップ基板との短絡は起こらない。絶縁膜が酸化膜
や窒化膜の場合にはウエハをチップにダイシングすると
き、その絶縁膜に欠けやクラックが発生する恐れがある
が、絶縁膜の最上層が樹脂であればそのような恐れはな
くなる。ＩＣチップがダイボンディングされているアイ
ランド部の周辺部に凸部を設けると、トランスファモー
ルド法による樹脂封止の際、仮にチップサイズが小さい
ものであっても上型側と下型側とでの樹脂の流れ速度に
は影響が現われなくなり、アイランド部の浮き沈みが抑
えられる。Since the insulating film is formed on the periphery of the IC chip, even if the bonding wire hangs down and comes into contact with the edge of the IC chip, the insulating film does not cause a short circuit between the wire and the IC chip substrate. . When the insulating film is an oxide film or a nitride film, when the wafer is diced into chips, cracks or cracks may occur in the insulating film. Disappear. If a convex portion is provided in the peripheral portion of the island portion to which the IC chip is die-bonded, even if the chip size is small, the upper mold side and the lower mold side are provided at the time of resin sealing by the transfer molding method. The flow rate of the resin is not affected and the ups and downs of the island are suppressed.
【０００８】[0008]
【実施例】図３は一実施例のＩＣチップを表わす。
（Ａ）は概略平面図、（Ｂ）はリードフレームにそのＩ
Ｃチップをワイヤボンディング法により一部接続したと
きの概略側面図である。ＩＣチップ２０の内側の表面に
はトランジスタその他の素子が形成されており、周辺部
２２には絶縁膜が形成されている。絶縁膜はシリコン酸
化膜又はシリコン窒化膜である。このＩＣチップを
（Ｂ）のように、リードフレームのアイランド部４にダ
イボンディングし、インナーリード６との間にワイヤ８
でボンディングを施す。仮に、ワイヤ８が垂れ下がって
ＩＣチップ２０のエッジと接触しても、エッジには絶縁
膜２２が形成されているので、電気的短絡は起こらな
い。周辺部の絶縁膜２２は酸化膜又は窒化膜の上にさら
に樹脂膜をコーティングしてあることが好ましい。その
ような樹脂膜としてはエポキシ樹脂やポリイミド樹脂な
どの透明樹脂が好ましい。FIG. 3 shows an IC chip according to one embodiment.
(A) is a schematic plan view, (B) is the lead frame
It is a schematic side view when a C chip is partially connected by a wire bonding method. Transistors and other elements are formed on the inner surface of the IC chip 20, and an insulating film is formed on the peripheral portion 22. The insulating film is a silicon oxide film or a silicon nitride film. This IC chip is die-bonded to the island portion 4 of the lead frame as shown in FIG.
Bond with. Even if the wire 8 hangs down and comes into contact with the edge of the IC chip 20, since the insulating film 22 is formed at the edge, no electrical short circuit occurs. The peripheral insulating film 22 is preferably formed by further coating a resin film on the oxide film or the nitride film. As such a resin film, a transparent resin such as an epoxy resin or a polyimide resin is preferable.
【０００９】図４によりこのＩＣチップを製造する方法
を説明する。（Ａ）に示されるように、シリコンウエハ
２４にウエハプロセスによりトランジスタなどの素子を
形成した後、各ＩＣチップ２２の間に存在するダイシン
グラインに酸化膜や絶縁膜などの絶縁膜２２を形成す
る。絶縁膜２２はＩＣチップ内の素子形成時の酸化膜や
窒化膜の形成と同時に形成することができる。さらに、
好ましくは、絶縁膜２２として酸化膜や窒化膜上にエポ
キシ樹脂やポリイミド樹脂膜を形成する。樹脂膜の形成
は、樹脂形成領域に開口をもつようなマスクをおき、そ
のマスクを介して樹脂コーティングしたり、ダイシング
ラインを覆う形状に切り抜かれたシート状の樹脂フィル
ムを例えばエポキシ系接着剤で貼り付ける。ダイシング
ラインの幅は１００μｍ程度である。次に、（Ｂ）のよ
うにダイシングラインに沿ってダイシングを行ない、チ
ップごとに切り離す。カッティングラインの幅Ｃは例え
ば４０〜６０μｍである。A method of manufacturing this IC chip will be described with reference to FIG. As shown in (A), after forming elements such as transistors on the silicon wafer 24 by a wafer process, the insulating film 22 such as an oxide film or an insulating film is formed on the dicing lines existing between the IC chips 22. . The insulating film 22 can be formed at the same time when the oxide film or the nitride film is formed at the time of forming the element in the IC chip. further,
Preferably, an epoxy resin or polyimide resin film is formed on the oxide film or the nitride film as the insulating film 22. The resin film is formed by placing a mask having an opening in the resin forming area, resin coating through the mask, or a sheet-shaped resin film cut out to cover the dicing line with, for example, an epoxy adhesive. paste. The width of the dicing line is about 100 μm. Next, as shown in (B), dicing is performed along the dicing line to separate the chips. The width C of the cutting line is, for example, 40 to 60 μm.
【００１０】図５はリードフレームのアイランド部を改
良した実施例を表わす。この実施例の実装体用のリード
フレームでは、ＩＣチップ２をダイボンディングするア
イランド部３０の周辺部がＩＣチップ２側に突出した凸
部３２を備えている。凸部３２はリードフレームを作成
する際の金型成形で折り曲げることにより製作すること
ができる。また凸部３２はアイランド部３０とは別の材
質とすることができ、例えばエポキシ樹脂の枠を接着剤
によりアイランド部３０の周辺部に接着したり、又は樹
脂成型によりアイランド部３０上に直接形成することも
できる。凸部３２の高さはダイボンディングされるＩＣ
チップ２の高さとほぼ等しい高さに設定しておく。FIG. 5 shows an embodiment in which the island portion of the lead frame is improved. In the lead frame for mounting body of this embodiment, the peripheral portion of the island portion 30 for die-bonding the IC chip 2 is provided with the convex portion 32 protruding toward the IC chip 2 side. The convex portion 32 can be manufactured by bending with a metal mold when the lead frame is formed. The convex portion 32 can be made of a material different from that of the island portion 30. For example, a frame of epoxy resin is adhered to the peripheral portion of the island portion 30 with an adhesive, or is formed directly on the island portion 30 by resin molding. You can also do it. The height of the convex portion 32 is an IC to be die-bonded.
The height is set to be almost equal to the height of the tip 2.
【００１１】図５のように凸部３２をもつアイランド部
３０にＩＣチップ２を実装し、型１２，１４内に収容し
て樹脂を封入する際、ＩＣチップ２のサイズが変わって
も凸部３２が存在することにより上型側と下型側での樹
脂の流れ速度がＩＣチップ２のサイズの影響を受けにく
くなる。そのため、樹脂封入の最初に設定した条件のま
まで安定した品質の樹脂封止を行なうことができる。特
に、アイランド部３０のサイズとそれに実装するＩＣチ
ップ２のサイズとの大きさの差が大きいときほど有効に
働く。When the IC chip 2 is mounted on the island portion 30 having the convex portion 32 as shown in FIG. 5 and is housed in the molds 12 and 14 and the resin is encapsulated, the convex portion is changed even if the size of the IC chip 2 is changed. Due to the presence of 32, the resin flow speeds on the upper mold side and the lower mold side are less likely to be affected by the size of the IC chip 2. Therefore, stable quality resin sealing can be performed under the conditions set at the beginning of resin sealing. In particular, it works more effectively when the size difference between the size of the island portion 30 and the size of the IC chip 2 mounted thereon is large.
【００１２】[0012]
【発明の効果】本発明によりＩＣチップの周辺部に絶縁
膜を形成すると、ＩＣチップとリードフレームを接続す
るワイヤボンディングのワイヤとＩＣチップとが接触し
ても、短絡による不良が発生するのを防止することがで
きる。ＩＣチップ周辺部の絶縁膜の最上層が透明樹脂膜
であれば、ダイシングの際に絶縁膜が欠けたり、クラッ
クが入ったりするのを防ぐことができるとともに、透明
樹脂膜であればダイシング時などの際の画像処理を従来
通り行なうことができる。チップ周辺部に絶縁膜が形成
された状態で最終製品まで製造ラインを流されることに
なり、ウエハやチップをつかんで移動させたりするハン
ドリング時に素子形成面に傷がついたりするのを防ぐこ
ともできる。ＩＣチップをダイボンディングするアイラ
ンド部の周辺部にチップ側に突出した凸部が設けられて
いるときは、トランスファモールド法により樹脂封止す
る際、実装されるＩＣチップのサイズが変わっても型内
での樹脂の流れ抵抗が大きな影響を受けることがなくな
り、安定した品質の樹脂封止実装体を得ることができ
る。When the insulating film is formed on the peripheral portion of the IC chip according to the present invention, even if the wire for wire bonding connecting the IC chip and the lead frame and the IC chip come into contact with each other, a defect due to a short circuit may occur. Can be prevented. If the uppermost layer of the insulating film around the IC chip is a transparent resin film, it is possible to prevent the insulating film from being chipped or cracked during dicing, and if it is a transparent resin film, such as during dicing. The image processing at the time of can be performed as usual. With the insulating film formed on the periphery of the chip, the manufacturing line will be flown to the final product, and it is possible to prevent scratches on the element formation surface during handling such as grasping and moving the wafer or chip. it can. When a convex portion protruding toward the chip is provided in the peripheral portion of the island portion for die-bonding the IC chip, the resin is sealed by the transfer molding method, and the size of the mounted IC chip is changed even if the size of the IC chip is changed. The flow resistance of the resin is not significantly affected, and a resin-sealed package having stable quality can be obtained.
【図１】従来のワイヤボンディングを示す部分正面図で
ある。FIG. 1 is a partial front view showing conventional wire bonding.
【図２】従来のトランスファモールド法を示す端面図で
ある。FIG. 2 is an end view showing a conventional transfer molding method.
【図３】一実施例のＩＣチップを示す図であり、（Ａ）
は概略平面図、（Ｂ）はそのＩＣチップの一部がワイヤ
ボンディングされた状態を示す概略正面断面図である。FIG. 3 is a diagram showing an IC chip of an embodiment, (A)
Is a schematic plan view, and (B) is a schematic front sectional view showing a state in which a part of the IC chip is wire-bonded.
【図４】図３の実施例の製造方法を示す図であり、
（Ａ）はウエハ状態の部分概略平面図、（Ｂ）はダイシ
ングした状態を示す概略拡大断面図である。FIG. 4 is a diagram showing a manufacturing method of the embodiment of FIG.
(A) is a partial schematic plan view of a wafer state, and (B) is a schematic enlarged sectional view showing a dicing state.
【図５】実装体の実施例を示す図であり、（Ａ）は樹脂
封止状態を示す端面図、（Ｂ）は主としてアイランド部
を示す拡大端面図である。5A and 5B are views showing an example of a mounting body, FIG. 5A is an end view showing a resin-sealed state, and FIG. 5B is an enlarged end view mainly showing an island portion.
２，２０ ＩＣチップ ４，３０ アイランド部 ８ ワイヤ ２２ 周辺部 2,20 IC chip 4,30 Island section 8 wires 22 Peripheral area
Claims (3)
されている表面の周辺部に絶縁膜が形成されている半導
体装置。1. A semiconductor device in which an insulating film is formed on a peripheral portion of a surface on which an element is formed in a semiconductor integrated circuit device chip.
脂層である請求項１に記載の半導体装置。2. The semiconductor device according to claim 1, wherein at least the uppermost layer of the insulating film is a transparent resin layer.
集積回路装置チップがダイボンディングされ、インナー
リードと前記チップがボンディングされ、前記チップ部
分が樹脂封止されている実装体において、前記アイラン
ド部の周辺部にはチップ側に突出した凸部が設けられて
いることを特徴とする半導体装置実装体。3. A semiconductor integrated circuit device chip is die-bonded to an island portion of a lead frame, an inner lead is bonded to the chip, and the chip portion is resin-sealed. The semiconductor device mounting body, wherein the semiconductor device mounting body is provided with a convex portion protruding toward the chip side.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3209859A JPH0536746A (en) | 1991-07-26 | 1991-07-26 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3209859A JPH0536746A (en) | 1991-07-26 | 1991-07-26 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0536746A true JPH0536746A (en) | 1993-02-12 |
Family
ID=16579812
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3209859A Pending JPH0536746A (en) | 1991-07-26 | 1991-07-26 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0536746A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0622845A2 (en) * | 1993-04-30 | 1994-11-02 | Hewlett-Packard Company | Apparatus and method for tape automated bonding beam lead insulation |
-
1991
- 1991-07-26 JP JP3209859A patent/JPH0536746A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0622845A2 (en) * | 1993-04-30 | 1994-11-02 | Hewlett-Packard Company | Apparatus and method for tape automated bonding beam lead insulation |
| EP0622845A3 (en) * | 1993-04-30 | 1995-03-29 | Hewlett Packard Co | Apparatus and method for tape automated bonding beam lead insulation. |
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