JPH0535592B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention provides a unit consisting of a plurality of semiconductor memory boards in an electronic computer system. This invention relates to a memory board device that can be expanded.

<Conventional technology> In general computer systems, since the processing content differs depending on each user,
It is necessary to have a configuration that allows internal memory to be expanded according to each user's request, and the conventional method for expanding internal memory is to attach a memory board with semiconductor memory mounted separately from the memory board of the standard device. It's summery.

<Problems to be Solved by the Invention> As mentioned above, when expanding the internal memory, the memory board is attached and expanded as a unit, so there is a problem that the mounting structure is complicated, and the memory board As the number of drivers increases, the maintenance process becomes complicated, and furthermore, there are various problems such as the need to provide the driver circuit on multiple boards when mounting the driver circuit.

<Object of the Invention> The present invention has been made in view of the above problems, and it is possible to increase memory by connecting an auxiliary board on which a group of semiconductor memories is mounted to a memory board without increasing the number of memory boards. The object of the present invention is to provide a memory substrate device that can perform the following steps.

<Means for Solving the Problems> In order to achieve the above object, the semiconductor memory board device of the present invention is a memory board device in which a plurality of semiconductor memory boards in an electronic computer system are unitized. On the board,
A semiconductor memory group equipped as a standard device, a plurality of expansion areas in which an auxiliary board having an expansion semiconductor memory group is connected and attached via a connector, and a memory control circuit, and the elements constituting the memory control circuit. The main feature is that the standard memory groups and the expansion areas are arranged in a matrix on the periphery of the memory board.

<Function> The memory board device of the present invention configured as described above connects the auxiliary board provided with the semiconductor memory group to the expansion area of the memory board via the connector when, for example, it is desired to add memory to an electronic computer system. By doing so, the memory capacity can be increased without increasing the number of memory boards. In such a case, the semiconductor memory group added to the memory board via the auxiliary board will be arranged in a matrix together with the memory group that is standard equipment on the memory board, resulting in extremely easy maintenance. .

<Example> Hereinafter, one embodiment of the present invention will be explained in detail.

First, the technical background of the present invention will be explained with reference to FIG. 4. For example, in an electronic computer system,
Various circuit boards A, such as a CPU board, various control boards, and memory boards, are housed in parallel in chassis unit B, and each circuit board A is connected to guide rails (not shown) formed in pairs in chassis unit B. It is inserted removably while being held in the
A connector plug (not shown) provided at the lower end of each is connected to a connector jack (not shown) on the motherboard in chassis unit B for electrical connection. Further, during maintenance, each circuit board A is provided with a bypass board so that it can be led out from the unit B. Conventionally, when adding memory, an additional circuit board is attached as described above, so it is necessary to use space and connection structure for installing a considerable number of additional boards in unit B.

The memory board 1 of the present invention, which is housed and attached to such a unit B, has a structure as shown in FIG. That is, a connector 3 that is electrically connected to the aforementioned connector jack on the motherboard is protruded from the lower end, and a memory board with semiconductor memories 4a consisting of RAM chips arranged in a matrix is provided at the lower left. A semiconductor memory group 4 having a capacity of, for example, 1 Mbyte is provided as standard by directly soldering to the semiconductor memory group 4. Three areas around the memory group 4 are provided with expansion areas 5a, 5b, and 5c for adding more memory, and each expansion area 5
Data bus connectors 6a, 6b, 6c and address/control bus connectors 7a, 7b, 7c are attached to data bus connectors 6a, 5b, and 5c by soldering, respectively.
are inclined at a predetermined angle with respect to the horizontally positioned address bus/control bus connectors 7a to 7c, and are disposed non-parallel to each other. Moreover, each pair of connectors 6a, 7a, 6b, 7b, 6c, and 7c in each of the expansion areas 5a to 5c are arranged in the same shape.

In addition, memory control IC elements 8 are arranged so as to surround the semiconductor memory group 4 and each of the expansion areas 5a to 5c.
A memory control circuit 8 is constituted by a group of IC elements arranged and attached in an L-shape, and this memory control circuit 8 controls the semiconductor memory group 4 and the memories individually added by each user. .

The semiconductor memory group 4 is mounted on the auxiliary board 9 for memory expansion installed in the expansion areas 5a to 5c.
A semiconductor memory 10 consisting of the same RAM chip as
A semiconductor memory group 10 for expansion is provided, which is formed by arranging and soldering the semiconductor memories 6a in the same shape, and a pair of connectors 6 for each of the expansion areas 5a to 5c.
a, 7a, 6b, 7b, 6c, and 7c, a pair of connectors 11 and 12 are arranged in the same shape and provided on the component mounting surface, and one connector 11
A data bus of the semiconductor memory group 10 is connected to the connector 12, and an address bus and a control bus are connected to the other connector 12, respectively.

If you want to add more memory to the memory board 1, turn over the auxiliary board 9 from the state shown in FIG.
For example, they are inserted into the corresponding connectors 6b, 7b, 6c, and 7c of the expansion areas 5b and 5c, and are electrically connected. The second image shows this installation condition.
As is clear from the figure, each semiconductor memory 10a is housed in the gap formed between the two boards 1 and 9 due to the lengths of the connectors 6b, 7b, 6c, and 7c, which facilitates thinning when adding memory. I can figure it out.
In other words, as shown in Figure 4, unit B
By effectively utilizing the gaps between the circuit boards A arranged in tandem, the entire device including the unit B can be downsized.

Furthermore, since the data bus connectors 6a to 6c are arranged at an angle with respect to the address bus/control bus connectors 7a to 7c and are not parallel to each other, the data bus, address bus, and Misconnection with the control bus can be reliably prevented. Furthermore, each expansion area 5a~
Each pair of connectors 6a, 7a, 6 in 5c
b, 7b, 6c, and 7c are formed in the same pin arrangement, and each pin signal is also assigned the same, so the auxiliary board 9 can be attached to any mounting area 5a.
~5c can also be connected, providing compatibility with the auxiliary board 9. Furthermore, the semiconductor memory group 4 of the memory board 1 and the semiconductor memory group 10 of the auxiliary board 9 to be added to each of the expansion areas 5a to 5c are such that the semiconductor memories 4a and 10a are arranged in the same shape, that is, in a matrix. It has an easy-to-maintain structure, so it is easy to maintain.

Next, in FIG. 3 showing the electrical configuration, the same or equivalent parts as in FIGS. 1 and 2 are given the same reference numerals, and will be described in detail below. The CPU circuit 13 of the electronic computer system outputs various signals in accordance with the given commands and processes the commands. Connecting portions 14a, 14b, 14c of the auxiliary board 9 to the data bus connector 11, each address bus/control bus connector 7a to 7c of the memory board 1, and the address bus/control bus connector 1 of each auxiliary board 9.
2 to each semiconductor memory group 10 of the auxiliary board 9 connected to the semiconductor memory group 4 of the memory board 1 and each of the expansion areas 5a to 5c surrounded by broken lines. has been done. Each semiconductor memory group 4, 10 is connected to a bidirectional data bus D ₀ to
31, lower address data A _L0 to o and a read/write control signal R/W indicating whether to read the contents of the memory or write data to the memory are supplied, and each semiconductor memory group 4, 10
Address comparators 16a to 16d for selecting
A selection signal Sa~ is sent to each semiconductor memory group 4, 10 from
Supply Sd. In addition, a preset signal indicating the difference between the output of the start address setting circuit of each semiconductor memory group 4, 10 allocated by a switch or the like, and the start address of each expanded semiconductor memory group 10 and the start address of the memory board 1 is set. Constant data K1, K2, and K3 are added in adders 18a, 18b, and 18c, respectively, and upper data Aa to Ad of the addresses of the semiconductor memories 4 and 10 outputted from the adders 18a to 18c are added to the address comparators. 16b-16d
supplied to Therefore, each address comparator 16a
~16d selects the semiconductor memory group 10 corresponding to the upper address data A _H0~ 3 from the CPU circuit 13. Note that address comparators 16a to 16d, adders 18a to 18c, and start address setting circuit 18
is constituted by the memory control circuit 8 shown in FIG.

Now, hypothetically, if the electronic computer is 3 shown in Figure 3.
When the highest semiconductor memory group 10 in the group is accessed, the CPU circuit 13 outputs a read/write control signal R/W indicating whether data is to be read or written and address data A _L , A _H .
Here, the address comparators 16a to 16d use the output upper address data A _H and the upper address data Aa to Ad of the addresses of the semiconductor memory groups 4 and 10 determined by the address setting circuit 17 and the adders 18a to 18c. Compare with. At this time, since the upper address data A _H is equal to the upper address data Ab of the semiconductor memory group 10 shown at the top, the selection signal Sb is output only from the second address comparator 16b, and the selection signal Sb is output from the second address comparator 16b. The semiconductor memory group 10 becomes active and can be accessed.
In this way, by allowing memory to be added to the single memory board 1, the memory can be added without increasing the number of memory boards, and the memory control circuit and the like can also be configured simply. Further, by separately arranging the semiconductor memory group 4 serving as a memory section and the control section, the function of the memory board 1 can be easily determined, and maintainability is improved.

<Effects of the Invention> As detailed above, according to the memory board device of the present invention, the auxiliary board equipped with the semiconductor memory group can be connected to each expansion area of the memory board via the connector, so the number of memory boards can be reduced. It is possible to increase the number of memories without increasing memory capacity, and in addition, the expansion semiconductor memory group 5a is arranged in a matrix together with the semiconductor memory group that is standardly equipped on the memory board, and the memory control circuit is located around the memory board. Since the memory board is provided in a section and is arranged separately from the memory section, the function of the memory board can be determined at a glance, which has the advantage of significantly improving maintainability.

[Brief explanation of the drawing]

Each drawing shows an embodiment of the memory board device according to the present invention, in which Fig. 1 is an exploded front view, Fig. 2 is a cutaway side view, Fig. 3 is a block diagram of the electrical configuration, and Fig. 4 is a perspective view. be. 1...Memory board, 4...Semiconductor memory group, 4
a...Semiconductor memory, 5a-5a...Expansion area, 6a-6c, 7a-7c...Memory board connector, 9...Auxiliary board, 10a...Semiconductor memory, 11, 12...Auxiliary board connector .

Claims (1)

[Claims] 1. In a memory board device in which a plurality of semiconductor memory boards are integrated into a unit in a computer system, an auxiliary board including a standard semiconductor memory group and an expansion semiconductor memory group is connected to the semiconductor memory board by a connector. It has a plurality of expansion areas that can be connected and attached, and a memory control circuit, and a group of elements constituting the memory control circuit is arranged in a peripheral portion of the memory board, and the standard memory group and each of the expansion areas A memory board device characterized in that: and are arranged in a matrix.