JPH05347479A - Multilayer printed wiring board - Google Patents
Multilayer printed wiring boardInfo
- Publication number
- JPH05347479A JPH05347479A JP15488492A JP15488492A JPH05347479A JP H05347479 A JPH05347479 A JP H05347479A JP 15488492 A JP15488492 A JP 15488492A JP 15488492 A JP15488492 A JP 15488492A JP H05347479 A JPH05347479 A JP H05347479A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- gold plating
- terminal
- wiring board
- multilayer printed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/403—Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は多層プリント配線板に関
し、特に金めっき処理が施され金めっき層が形成された
端子を有する多層プリント配線板に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer printed wiring board, and more particularly to a multilayer printed wiring board having a terminal which has been subjected to a gold plating treatment to form a gold plating layer.
【０００２】[0002]
【従来の技術】従来の金めっき処理が施され金めっき層
が形成された端子を有するプリント配線板は、図３に示
すように、外部との接触用の端子は、コネクタとの挿抜
する領域まで金めっき処理が施されて金めっき層２が形
成されており、端子から引き出された配線パターンは、
ソルダレジスト層１の印刷により絶縁されている。2. Description of the Related Art As shown in FIG. 3, a conventional printed wiring board having a terminal on which a gold plating layer has been formed by applying a gold plating treatment has a terminal for contacting with the outside, which is a region to be inserted into and removed from a connector. The gold plating layer 2 is formed by performing the gold plating process up to and the wiring pattern drawn out from the terminal is
It is insulated by printing the solder resist layer 1.
【０００３】この場合、ソルダレジスト層１と金めっき
層２の境界部分に０．１μｍ程度、銅層３が露出する可
能性があり、この銅層３の露出部は、配線パターンに、
高湿度の環境下で、電流が流れると、電食をおこし、銅
層３が銅の電食部７で消失してしまうことがあった。In this case, the copper layer 3 may be exposed to the boundary between the solder resist layer 1 and the gold plating layer 2 by about 0.1 μm, and the exposed portion of the copper layer 3 is a wiring pattern.
When an electric current flows under the environment of high humidity, electrolytic corrosion may occur and the copper layer 3 may disappear at the electrolytic corrosion portion 7 of copper.
【０００４】[0004]
【発明が解決しようとする課題】この従来の金めっき層
が形成された端子を有する多層プリント配線板では、ソ
ルダレジスト層と金めっき層との間に、０．１μｍ程度
銅層が露出する可能性があるため、高湿度の環境下で電
流が流れると境界部に露出した銅層が電食をおこし、銅
層そのものが消失してしまうという問題点があった。In this conventional multilayer printed wiring board having a terminal on which a gold plating layer is formed, a copper layer of about 0.1 μm can be exposed between the solder resist layer and the gold plating layer. Therefore, when a current flows in a high humidity environment, the copper layer exposed at the boundary causes electrolytic corrosion and the copper layer itself disappears.
【０００５】本発明の目的は、電食による銅層の消失の
ない多層プリント配線板を提供することにある。An object of the present invention is to provide a multilayer printed wiring board in which the copper layer does not disappear due to electrolytic corrosion.
【０００６】[0006]
【課題を解決するための手段】本発明は、金めっき処理
が施され金めっき層が形成された端子を有する多層プリ
ント配線板において、前記端子からの引き出し配線パタ
ーンを前記端子の直下に設けた非貫通の表層バイアホー
ルを経由して内層パターンに接続したことを特徴とす
る。According to the present invention, in a multilayer printed wiring board having a terminal which is subjected to a gold plating treatment and a gold plating layer is formed, a lead-out wiring pattern from the terminal is provided immediately below the terminal. It is characterized in that it is connected to the inner layer pattern through a non-penetrating surface layer via hole.
【０００７】[0007]
【実施例】次に、本発明の実施例について図面を参照し
て説明する。Embodiments of the present invention will now be described with reference to the drawings.
【０００８】図１は本発明の第１の実施例の端子部の断
面図である。FIG. 1 is a sectional view of a terminal portion according to the first embodiment of the present invention.
【０００９】第１の実施例は、図１に示すように、金め
っき層２が形成された端子部の銅層３からの配線パター
ンは、端子部直下に設けた非貫通の表層バイアホール
（ＳｕｒｆａｃｅＶｉａＨｏｌｅ）（以下、ＳＶＨと記
す）４を経由して、内層パターン５に接続されている。
この構造では、端子部からの引き出し配線パターンは、
内層パターン５となり表面に露出していないので、図３
に示すように従来の端子のように、ソルダレジスト１と
金めっき層２との境界部に発生しやすい電食を防止でき
るという効果がある。In the first embodiment, as shown in FIG. 1, the wiring pattern from the copper layer 3 of the terminal portion where the gold plating layer 2 is formed is a non-penetrating surface via hole (immediately below the terminal portion). It is connected to the inner layer pattern 5 via a SurfaceViaHole (hereinafter referred to as SVH) 4.
In this structure, the lead wiring pattern from the terminal is
Since it is the inner layer pattern 5 and is not exposed on the surface,
As shown in FIG. 5, there is an effect that it is possible to prevent electrolytic corrosion that is likely to occur at the boundary between the solder resist 1 and the gold plating layer 2 as in the conventional terminal.
【００１０】図２は本発明の第２の実施例のキー接点部
の断面図である。FIG. 2 is a sectional view of a key contact portion according to the second embodiment of the present invention.
【００１１】第２の実施例は、図２に示すように、キー
接点などに、きフラッシュを施した金フラッシュ層８を
形成した場合に適用した例である。金フラッシュが施さ
れ金フラッシュ層８が形成されたキー接点部の銅層３か
らの引き出し配線パターンは、キー接点部直下に設けた
ＳＶＨ４を経由して内層パターン５に接続されている。As shown in FIG. 2, the second embodiment is an example applied to a case where a gold flash layer 8 subjected to a flash is formed on a key contact or the like. The lead wiring pattern from the copper layer 3 of the key contact portion where the gold flash is applied and the gold flash layer 8 is formed is connected to the inner layer pattern 5 via the SVH 4 provided immediately below the key contact portion.
【００１２】[0012]
【発明の効果】以上説明したように本発明は、金めっき
層が形成された端子部やキー接点部より引き出された配
線パターンを基材内部の直下にＳＶＨを設けて、ＳＶＨ
経由で内層パターンに配線することで、ソルダレジスト
との境界部における銅層の露出が無くなり、高湿度の境
界下で電流を流すことにより発生する電食を防止できる
という効果を有する。As described above, according to the present invention, the SVH is provided immediately below the inside of the base material with the wiring pattern drawn out from the terminal portion or the key contact portion on which the gold plating layer is formed.
By wiring via the inner layer pattern via the copper layer, the copper layer is not exposed at the boundary with the solder resist, and electrolytic corrosion caused by passing an electric current under the boundary of high humidity can be prevented.
【図１】本発明の第１の実施例の端子部の断面図であ
る。FIG. 1 is a sectional view of a terminal portion according to a first embodiment of the present invention.
【図２】本発明の第２の実施例のキー接点部の断面図で
ある。FIG. 2 is a sectional view of a key contact portion according to a second embodiment of the present invention.
【図３】従来の多層プリント配線板の端子部の一例の断
面図である。FIG. 3 is a cross-sectional view of an example of a terminal portion of a conventional multilayer printed wiring board.
１ ソルダレジスト層 ２ 金めっき層 ３ 銅層 ４ ＳＶＨ ５ 内層パターン ６ 基材 ７ 銅の電食部 ８ 金フラッシュ層 1 Solder Resist Layer 2 Gold Plating Layer 3 Copper Layer 4 SVH 5 Inner Layer Pattern 6 Base Material 7 Copper Electrolytic Corrosion 8 Gold Flash Layer
Claims (1)
された端子を有する多層プリント配線板において、前記
端子からの引き出し配線パターンを前記端子の直下に設
けた非貫通の表層バイアホールを経由して内層パターン
に接続したことを特徴とする多層プリント配線板。1. In a multilayer printed wiring board having a terminal that has been subjected to a gold plating treatment and a gold plating layer has been formed, a lead-out wiring pattern from the terminal is provided through a non-penetrating surface layer via hole provided directly below the terminal. Then, a multilayer printed wiring board characterized by being connected to an inner layer pattern.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15488492A JPH05347479A (en) | 1992-06-15 | 1992-06-15 | Multilayer printed wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15488492A JPH05347479A (en) | 1992-06-15 | 1992-06-15 | Multilayer printed wiring board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05347479A true JPH05347479A (en) | 1993-12-27 |
Family
ID=15594064
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15488492A Withdrawn JPH05347479A (en) | 1992-06-15 | 1992-06-15 | Multilayer printed wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05347479A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4879281A (en) * | 1986-03-24 | 1989-11-07 | Lion Corporation | Artificial saliva composition |
-
1992
- 1992-06-15 JP JP15488492A patent/JPH05347479A/en not_active Withdrawn
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4879281A (en) * | 1986-03-24 | 1989-11-07 | Lion Corporation | Artificial saliva composition |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19990831 |