JPH05344768A - Motor drive circuit - Google Patents

Abstract

PURPOSE:To start a motor smoothly while increasing the rotational speed gradually from zero by operating the output stage with a chopping output having duty corresponding to the difference between a value obtained by integrating the voltage of driving power supply and a value obtained by integrating specific pulse signals generated from the driving power supply. CONSTITUTION:Upon provision of a driving signal to a power supply circuit 14, a first integrating circuit 15, an oscillation circuit 16, a second integrating circuit 17, and a comparing circuit 18 function and a logic gate 19 or 20 produces a chopping output having such duty as the time interval of high level is initially short and elongates as the integrated voltage from the first integrating circuit 15 increases. This chopping output turns FETQ1, Q2 at first output stage 11 or FETQ3, Q4 at second output stage 12 ON/OFF through transistors Tr3, Tr1, Tr2 or Tr6, Tr4, Tr5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a motor drive circuit used to control the start or stop of a small motor for automobile electrical equipment.

[0002]

2. Description of the Related Art As a motor drive circuit used to control the start or stop of a small motor for automobile electrical equipment, for example, the one described in Japanese Patent Laid-Open No. 63-194092 is known.

In the motor drive circuit described in the above publication, a relay is operated in response to a switching operation of a switch, and the operation of the relay supplies a voltage of a power source to the motor.

[0004]

However, in the above-mentioned motor drive circuit, since the voltage of the power supply is directly supplied to the motor by the operation of the relay, the motor receives a large amount of energy at the time of starting and suddenly starts to rotate. Therefore, there is a drawback that an impact may occur.

[0005]

The problem to be solved by the present invention is that when a large amount of energy is supplied to the motor when the motor is started, a shock may occur.

[0006]

SUMMARY OF THE INVENTION In a motor drive circuit according to the present invention, in order to prevent a shock when starting a motor, a source is an emitter of a first transistor and a gate is the first transistor. First FET with its drain connected to the motor brush terminal
A source connected to the emitter of the second transistor, a gate connected to the collector of the second transistor and a drain connected to the brush terminal of the motor; and a gate of the first FET and a second FET. An output stage comprising a resistor connected in series with the gate of the FET of the first FET and a diode connected between the source and the drain of the first FET and between the source and the drain of the second FET. At the same time, a power supply circuit that operates by a drive signal to generate a drive power supply, a first integration circuit that integrates the voltage of the drive power supply and generates a first integrated voltage, and a predetermined pulse signal by the drive power supply. An oscillator circuit for generating the pulse signal, a second integrator circuit for integrating the pulse signal to generate a second integrated voltage corresponding to the pulse signal, and a first integrator circuit for the first integrator circuit.
Of the output stage of the output stage is provided with a comparison circuit that compares the integrated voltage of the second integrated voltage with the second integrated voltage from the second integration circuit and generates a variable output with a duty corresponding to the level of the comparison difference. The output terminal of the comparison circuit is connected to the input side, and in a more preferable embodiment, the time constant of the first integration circuit is larger than the time constant of the second integration circuit. And realized the purpose of smoothly starting the motor.

[0007]

In the motor drive circuit according to the present invention,
When the drive power supply is generated by the power supply circuit, the voltage of the drive power supply is integrated by the first integration circuit, so that the first integrated voltage is generated. Further, the oscillation circuit generates a predetermined pulse signal based on the driving power source, and the second integration circuit generates the second integrated voltage corresponding to the pulse signal from the oscillation circuit. Then, the comparison circuit compares the first integrated voltage with the second integrated voltage, and a chopping output having a duty corresponding to the level of the difference obtained by the comparison is generated. Since this chopping output is applied to the input side of the output stage, the first transistor Tr1 causes the second FET, and the second transistor Tr2 causes the first FET to gradually decrease the off time interval. Because it operates on,
The motor is started from the stopped state while gradually increasing the rotation.

[0008]

1 to 4 show an embodiment of a motor drive circuit according to the present invention, showing a full-bridge motor drive circuit.

The illustrated motor drive circuit 1 comprises a first output stage 11, a second output stage 12 which is a pair with the first output stage 11, and a power supply unit 13 which is a power supply means.

The first output stage 11 is mainly the first FET.
Q1, the second FET Q2, the first transistor Tr1,
Second transistor Tr2, third transistor Tr
3, a resistor r1, a first diode D1, and a second diode D2.

The second output stage 12 mainly includes a third FET Q3, a fourth FET Q4 and a fourth transistor T.
r4, a fifth transistor Tr5, a sixth transistor Tr6, a resistor r2, a third diode D3, and a fourth diode D4.

The power supply unit 13 mainly includes a power supply circuit 14, a first integration circuit 15, an oscillation circuit 16, a second integration circuit 17, a comparison circuit 18, a first logic gate (AND) 19, and a second logic circuit. The theoretical gate (and) 20 of

The first and third FETs Q1 and Q3 are P-channel type, the second and fourth FETs Q2 and Q4 are N-channel type, and the first and fourth transistors Tr1 and T1.
r4 is a PNP type, and the second, third, fifth and sixth transistors Tr2, Tr3, Tr5, Tr6 are NPN type.

The source of the first FET Q1 of the first output stage 11 is connected to the emitter of the first transistor Tr1 and also to the power supply 50, and the drain of the first FET Q1 is one brush provided in the motor 10. Terminal 10a
It is connected to the.

The gate of the first FET Q1 is connected to the collector of the first transistor Tr1 and also to one end of the resistor r1.

A first diode D1 is connected between the source and the drain of the first FET Q1 in the forward direction from the drain to the source (toward the power supply 50). FET between source and gate
A bidirectional Zener diode ZD1 for protection is connected.

The base of the first transistor Tr1 is connected to the collector of the third transistor Tr3 via the resistor r3, and the resistor r4 is connected between the emitter and the base of the first transistor Tr1. The connection point between the resistor r4 and the emitter of the first transistor Tr1 is grounded via the resistors r5, r6, and r7.

Further, the connection point between the resistor r3 and the collector of the third transistor Tr3 and the resistor r5 and the resistor r6.
A fifth diode D5 is connected in the forward direction from the resistor r5 to the collector of the transistor Tr3 at the connection point of.

The emitter of the third transistor Tr3 is grounded, the base of the third transistor Tr3 is grounded via the resistor r8, and the first logic of the power supply unit 13 is connected via the resistor r9. It is connected to the output side of the gate 19.

The source of the second FET Q2 of the first output stage 11 is grounded, and the drain of the second FET Q2 is connected to the one brush terminal 10a of the motor 10.

The gate of the second FET Q2 is connected to the other end of the resistor r1 and the collector of the second transistor Tr2.

Then, between the source and drain of the second FET Q2, from the source to the drain (power source 50
The second diode D2 is connected in the forward direction, and the FE is connected between the source and the gate of the second FET Q2.
A bidirectional Zener diode ZD2 for T protection is connected.

The base of the second transistor Tr2 is connected to the connection point of the resistors r6 and r7.

The second output stage 12 is constructed symmetrically with the first output stage 11, and the source of the third FET Q3 of the second output stage 12 is connected to the emitter of the fourth transistor Tr4 and the power supply 50. Connected to the third FET Q
The drain of 3 is the other brush terminal 1 provided in the motor 10.
It is connected to 0b.

The gate of the third FET Q3 is connected to the collector of the fourth transistor Tr4 and to one end of the resistor r2.

A third diode D3 is connected between the source and the drain of the third FET Q3 in the forward direction from the drain to the source (toward the power supply 50), and the third diode D3 of the third FET Q3 is connected. FET between source and gate
A bidirectional Zener diode ZD3 for protection is connected.

The base of the fourth transistor Tr4 is connected to the collector of the sixth transistor Tr6 via the resistor r10, and the resistor r11 is connected between the emitter and the base of the fourth transistor Tr4. The connection point between the resistor r11 and the emitter of the fourth transistor Tr4 is grounded via the resistors r12, r13, r14.

In addition, at the connection point between the resistor r10 and the collector of the sixth transistor Tr6 and the connection point between the resistor r12 and the resistor r13, a forward direction from the resistor r12 to the collector of the sixth transistor Tr6 is provided. 6 diode D
6 is connected.

The emitter of the sixth transistor Tr6 is grounded, the base of the sixth transistor Tr6 is grounded via the resistor r15, and the resistor r1.
It is connected to the output side of the second logic gate 20 of the power supply unit 13 via 6.

The source of the fourth FET Q4 of the second output stage 12 is grounded, and the drain of the fourth FET Q4 is connected to the other brush terminal 10b of the motor 10.

The gate of the fourth FET Q4 is connected to the other end of the resistor r2 and to the collector of the fifth transistor Tr5.

Then, between the source and drain of the fourth FET Q4, from the source to the drain (power source 50
The fourth diode D4 is connected in the forward direction, and the FE is connected between the source and the gate of the fourth FET Q4.
A bidirectional Zener diode ZD4 for T protection is connected.

The base of the fifth transistor Tr5 is connected to the connection point of the resistors r13 and r14.

Here, since the gate input of the first FET Q1 gradually reaches the on-operation potential from the off state by the time constant set by the product of the gate parasitic capacitance and the resistor r1, the first FET Q1 is turned on. As shown in FIG. 4, it is turned on after a delay time T1 from off.

The second FET Q2 also has a resistor r1 and
Similarly to the first FET Q1, the third and fourth FETs Q3 and Q4 are connected to the resistor r2, and the delay time T2 from the off time T2 to the delay time T
3, Turns on after T4.

On the other hand, in the power supply circuit 14 of the power supply unit 13, one end of the resistor r17 is connected to the drive signal input terminals 2 and 3 via the diodes D7 and D8, as is apparent from FIG. The other end of the container r17 is connected to the collector of the seventh transistor Tr7. The base of the seventh transistor Tr7 is grounded via the Zener diode ZD5, and the resistor r18 is connected between the collector and the base of the seventh transistor Tr7.

The emitter of the seventh transistor Tr7 is connected to the output terminal 14b and is also connected to the other ends of the capacitors C1 and C2 whose one ends are grounded, and further the resistor r19 of the first integrating circuit 15 is connected. It is connected to one end.

Here, when the drive signal is transferred to the drive signal input terminal 2 or 3, the power supply circuit 14 receives the diode D7.
Or, since the current of the drive signal flows through the resistor r17 → the resistor r18 → the zener diode ZD5 via D8,
The base of the seventh transistor Tr7 operates at a constant voltage. The voltage of the emitter of the seventh transistor Tr7 is
(The voltage between the base and the voltage between the base and the emitter), and a stable power source is supplied to the first integrating circuit 15 by the capacitors C1 and C2.

In the first integrating circuit 15, the other end of the resistor r19 is connected to one end of the capacitor C3, and the other end of the capacitor C3 is grounded. The connection point 15a between the resistor r19 and the capacitor C3 is connected to the plus input side of the comparator 18a included in the comparison circuit 18 via the resistor r20, and one end of the resistor r19 is the resistor of the oscillation circuit 16. It is connected to one end of r21.

When the driving power is input to the resistor r19 from the power supply circuit 14, the first integrator circuit 15 starts charging with the time constant set by [capacitor C3 × resistor r19]. As is clear from FIG. 3, the first integrated voltage that is fully charged in a relatively long time is generated.

The oscillation circuit 16 has the other end of the resistor r21 connected to the output side of the comparator 16a via the resistor r22 and the positive input side of the comparator 16a, and is further grounded via the resistor r23. Has been done.

One end of the resistor r21 is connected to one end of the resistor r24, and the other end of the resistor r24 is connected to the output side of the comparator 16a.

The negative input side of the comparator 16a is grounded via the capacitor C4 and the resistor r
25 and a resistor r26 to be connected to the output side of the comparator 16a, and a diode D9 is connected to one end and the other end of the resistor r26.

One end of the resistor r24 has a second integrating circuit 17
Connected to one end of the resistor r27 of the comparator 16a
The output side of is connected to one end of the resistor r28 of the second integrating circuit 17.

When the driving power is input from the power supply circuit 14, the oscillating circuit 16 receives [capacitor C4 × (resistor r25
+ Resistor r26)] continuously generates a low-level signal with a time constant set by [resistor r25 × capacitor C4]. As described above, the pulse signal having the period TF is generated.

In the second integrating circuit 17, the collector of the eighth transistor Tr8 is connected to the other end of the resistor r27,
The collector of the eighth transistor Tr8 is a resistor r29,
It is grounded via a capacitor C5, and the emitter of the eighth transistor Tr8 is grounded. The base of the eighth transistor Tr8 is connected to the other end of the resistor r28 and is grounded via the resistor r30.

One end of the resistor r27 is connected to one end of the resistor r31 of the comparison circuit 18, and the connection point 17a between the resistor r29 and the capacitor C5 is the resistor r3 of the comparison circuit 18.
2 is connected to the other end.

The second integrator circuit 17, when the output from the comparator 16a of the oscillator circuit 16 is low level,
That is, when the eighth transistor Tr8 is off, the capacitor C5 has a time constant set by [capacitor C5 × (resistor r27 + resistor r29)] through the resistors r27 and r29 (in the case of the first integrating circuit 15, When the output from the comparator 16a of the oscillation circuit 16 is at a high level, that is, when the eighth transistor Tr8 is on, the capacitor C5 is started.
Through resistor r29 [capacitor C5 × resistor r2
9] to start the discharge with the time constant set.

As a result, the second integrating circuit 17 operates as shown in FIG.
As is clear from the above, the second integrated voltage having a sawtooth waveform is generated at a period corresponding to the pulse signal having the period TF from the oscillation circuit 16.

In the comparison circuit 18, the other end of the resistor r32 is connected to the minus input side of the comparator 18a, the other end of the resistor r20 is connected to the plus input side of the comparator 18a, and the other end of the resistor r31 is connected to the comparator. 18a is connected to the output side, and the output side of the comparator 18a is connected to one input side of the first logic gate 19.

In the comparison circuit 18, the first integrated voltage from the first integration circuit 15 is input to the positive input side of the comparator 18a, and the second integrated voltage is input to the negative input side of the comparator 18a.
Since the second integrated voltage from the integrating circuit 17 of is input,
A comparator 18a compares the first and second integrated voltages to generate a chopping output that is high level when (minus input side <plus input side) and low level when (minus input side> plus input side). To do.

The output from the comparison circuit 18 is shown in FIG.
As is clear from the above, in the initial stage, the high level time is short, and the high level time becomes longer as the first integrated voltage from the first integrating circuit 15 becomes higher.

On the other hand, the other input side of the first logic gate 19 is connected to one drive signal input terminal 2 through the resistor r33 and the other end is grounded.
Is connected to one end of.

One input side of the first logic gate 19 is connected to one input side of the second logic gate 20, and the other input side of the second logic gate 20 is a resistor r.
The resistor r36 is connected to the other drive signal input terminal 3 via 35 and is also connected to one end of a resistor r36 whose other end is grounded.

According to the AND logic, the first logic gate 19 has one drive signal input terminal 2 at the high level (1).
At this time, the chopping output is supplied to the third transistor Tr3 corresponding to the output from the comparison circuit 18, the second logic gate 20 follows the AND logic, and the other drive signal input terminal 3 is at the high level (1 ), The comparison circuit 18
The chopping output is supplied to the sixth transistor Tr6 corresponding to the output from the.

The one drive signal input terminal 2 and the other drive signal input terminal 3 are connected to a switch (not shown). When this switch is switched to one side, one drive signal input terminal 2 is at a high level (1 ) And the other drive signal input terminal 3 becomes low level (0) and the switch is switched to the other side, the other drive signal input terminal 3 becomes high level (1) and one drive signal input terminal 2 becomes low level (0). If the switches are not switched, the input terminals 2 and 3 both become low level (0).

As is clear from FIG. 4, the motor drive circuit 1 having such a structure has one drive signal input terminal 2 and the other drive signal input terminal 3 at the low position A where the switches are not switched. Since the output of the first logic gate 19 and the output of the second logic gate 20 are at level (0), the second transistor Tr2 and the fifth transistor Tr5 are on. ..

Since the second transistor Tr2 and the fifth transistor Tr5 are turned on, the first FET Q1 of the first output stage 11 and the third FET Q3 of the second output stage 12 are delayed by the delay times T1 and T3. Turned on and first
The second FET Q2 of the output stage 11 and the fourth FET Q2 of the second output stage 12
FET Q4 is off, and the first FET Q1 and the third FET Q3
Of the brush terminals 10a, 1 of the motor 10 by the FET Q3 of
Since the short circuit is formed with respect to 0b, the motor 10 does not move.

Therefore, when the switch is switched to the one side at the B position, the other drive signal input terminal 3 remains at the low level (0) and one drive signal input terminal 2 becomes the high level (1), so that the diode Power supply circuit 1 via D7
The drive signal is input to 4.

When the drive signal is input to the power supply circuit 14, the first integrator circuit 15, the oscillator circuit 16, the second integrator circuit 17, and the comparator circuit 18 operate as described above. The chopping output from the logic gate 19 is supplied to the third transistor Tr3.

The third transistor Tr3 is turned on when the chopping output is at the high level (1) to turn off the second transistor Tr2 and turn on the first transistor Tr1. Therefore, the first transistor Tr1 of the first output stage 11 is turned on. FETQ1 of the first output stage 11 is cut off, and the second FETQ2 of the first output stage 11 is turned on after a delay time T2 set by the resistor r1.

The third transistor Tr3 is turned off when the chopping output is at the low level (0), and the second transistor Tr3 is turned on.
Turning on the transistor Tr2 of the first transistor T
In order to turn off r1, the second FET Q of the first output stage 11
2 is cut off, and the first FET Q of the first output stage 11
1 turns on after a delay time T1 set by the resistor r1.

While the third transistor Tr3 is on, the second FET Q2 of the first output stage 11 has the delay time T
2 and the third FET Q3 of the second output stage 12 is turned on, the power source 50 → the third FET Q3 of the second output stage 12 → the other brush terminal 10b of the motor 10 → one of the motors 10 Of the brush terminal 10a → the second FET Q2 of the first output stage 11 is formed. Also, while the third transistor Tr3 is off, the first
Since the FET Q1 and the third FET Q3 both turn on to form a short circuit, the motor 10 rotates forward while gradually increasing the rotation speed of the motor shaft 10c to a set value, as is apparent from FIG.

When the switch is returned from the one side at the C position, both drive signal input terminals 2 and 3 become low level (0), so that the power supply circuit 14, the first integration circuit 15, and the oscillation circuit. 16, the second integration circuit 17, the comparison circuit 18 are turned off, the third transistor Tr3 is turned off, the second transistor Tr2 is turned on, and the first output stage 1
The first FET Q1 of 1 is turned on after the delay time T1 set by the resistor r1 and the first transistor Tr1 is turned off, so that the second FET Q2 of the first output stage 11 is cut off.

At this time, in synchronization with the turning off of the second FET Q2, the third FET Q3 (on) of the second output stage 12 → the other brush terminal 10b of the motor 10 → the one brush terminal 10a of the motor 10 → the first When a short circuit is formed from the diode D1 to the power source 50 and the current flowing in the short circuit disappears, the motor 10 is turned off until the third FET Q3 of the second output stage 12 is turned off by the counter electromotive force of the motor 10. The other brush terminal 10b of 10 → third FE
TQ3 and third diode D3 → first FET Q1 of first output stage 11 → one brush terminal 10 of motor 10
Since the short circuit passing through a is formed, the shaft 10c of the motor 10 instantaneously stops at the C position.

When the switch is switched to the other side at the D position, one drive signal input terminal 2 remains low level (0) and the other drive signal input terminal 3 becomes high level (1). The power supply circuit 1 is operated in the same manner as when one of the drive signal input terminals 2 becomes high level (1)
4, the first integrator circuit 15, the comparator circuit 16, the second integrator circuit 17, and the comparator circuit 18 operate, so that the chopping output is supplied from the second logic gate 20 to the sixth transistor Tr6.

The sixth transistor Tr6 is turned on when the chopping output is at high level (1) and turned off when the chopping output is at low level (0).
Of the second output stage 12 is turned on after the delay time T4 while the sixth transistor Tr6 is turned on and the first transistor of the first output stage 11 is turned on. Since the FET Q1 is turned on, the power source 50 → the first FET Q1 of the first output stage 11 → the motor 10
One of the brush terminals 10a → the other brush terminal 10b of the motor 10 → the fourth FET Q4 of the second output stage 12, and the first FET Q1 while the sixth transistor Tr6 is off. , The third FET Q3
Are turned on to form a short circuit, and the motor 10 is reversely rotated while gradually increasing the rotation speed of the motor shaft 10c to a set value.

Further, when the switch is returned from the other side at the E position, both drive signal input terminals 2 and 3 become low level (0), so that the power supply circuit 14,
First integrator circuit 15, oscillator circuit 16, second integrator circuit 1
7, the comparison circuit 18 is turned off, and the fourth F of the second output stage 12 is
ETQ4 is cut off.

At this time, in synchronization with the turning off of the fourth FET Q4, the first FET Q1 (on) of the first output stage 11 → one brush terminal 10a of the motor 10 → the other brush terminal 10b of the motor 10 → the third A short circuit is formed from the diode to the power source 50, and when the current flowing in the short circuit disappears, the counter electromotive force of the motor 10 causes the motor 10 of the first output stage 11 until the first FET Q1 is turned off. One brush terminal 10a → first FET Q
1 and the first diode D1 → the third of the second output stage 12
Since a short circuit passing through the FET Q3 → the other brush terminal 10b of the motor 10 is formed, the motor shaft 10c of the motor 10 stops at the E position in an instant.

In the meantime, the second FETQ of the first output stage 11 corresponds to the high level (1) of the chopping output.
2, the fourth FET Q4 of the second output stage 12 has a delay time T
After 2 and T4, the on operation is performed and the off operation is repeated corresponding to the low level (0) of the chopping output.

[0071]

As described above, since the motor drive circuit according to the present invention has the above-described structure, the output stage operates by the output from the power supply means, so that the motor is gradually stopped. Since the motor can be started up by increasing the rotation, it does not support a large amount of energy to the motor, and as a result, there is an excellent effect that the motor can be started smoothly.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of an embodiment of a motor drive circuit according to the present invention.

FIG. 2 is a specific circuit diagram of power supply means in the motor drive circuit shown in FIG.

FIG. 3 is a waveform diagram of power supply means in the motor drive circuit shown in FIG.

FIG. 4 is a time chart explaining the operation of the motor drive circuit shown in FIG.

[Explanation of symbols]

1 Motor Drive Circuit 10 Motor 10a Brush Terminal 11 (12) Output Stage 13 Power Supply Means 14 Power Supply Circuit 15 First Integrator Circuit 16 Oscillation Circuit 17 Second Integrator Circuit 18 Comparison Circuit D1, D2, D3, D4 Diode Q1 ( Q3) First FET (third FET) Q2 (Q4) Second FET (fourth FET) r1, r2 Resistor Tr1 (Tr4) First transistor (fourth transistor) Tr2 (Tr5) 2nd transistor (5th transistor)

Claims (2)

[Claims] 1. A first FET having a source connected to the emitter of the first transistor, a gate connected to the collector of the first transistor, and a drain connected to the brush terminal of the motor.
A second FET having a source connected to the emitter of the second transistor, a gate connected to the collector of the second transistor, and a drain connected to the brush terminal of the motor; and a gate and a second FET of the first FET. Between the resistor connected in series with the gate of the first FET and the source and drain of the first FET, and the second FET
A power supply circuit which is provided with a diode connected between the source and the drain of the power supply circuit and which is driven by a drive signal to generate a drive power supply; A first integrator circuit for generating a pulse signal, an oscillator circuit for generating a predetermined pulse signal by the driving power source, and a second integration circuit for integrating the pulse signal to generate a second integrated voltage corresponding to the pulse signal. Circuit and a comparator circuit for comparing the first integrated voltage from the first integrator circuit and the second integrated voltage from the second integrator circuit and generating a chopping output at a duty corresponding to the level of the comparison difference. A motor drive circuit comprising: a power supply unit including: and an output end of the comparison circuit connected to an input side of the output stage. 2. The motor drive circuit according to claim 1, wherein the time constant of the first integrating circuit is larger than the time constant of the second integrating circuit.