JPH05300774A - Driving circuit for motor - Google Patents

Abstract

PURPOSE:To improve responding performance by connecting a resistor to gates of first, second FETs and diodes between sources and drains of the first, second FETs. CONSTITUTION:When a forward side signal input terminal 2 is 'H', a transistor(Tr) 3 is turned ON. Simultaneously, when a Tr 2 is turned OFF and a Tr 1 is turned ON, an FET Q1 is turned OFF, and an FET Q2 is turned ON after a delay time set by a resistor r1. A circuit of an FET Q3, a brush terminal (BI) 10b, a BI 10a and the FET Q2 is conducted, and a motor 10 is forwardly rotated. Then, when the motor 10 is deenergized, the FET Q1 is turned ON after the delay time set by the resistor r1. In this case, a short-circuiting circuit of the FET Q3, the BI 10b, the BI 10a and a diode D1 is formed. When a current flowing the short-circuiting circuit is eliminated, a short-circuit of the BI 10a, a diode D3 and the diode D3, the FET Q1 and the BI 10b is formed and the motor 10 is stopped by a counterelecctromotive force of the motor 10.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a motor drive circuit used to control the start or stop of a small motor for automobile electrical equipment.

[0002]

2. Description of the Related Art As a motor drive circuit for controlling the start or stop of a small motor for automobile electrical equipment, for example, one disclosed in Japanese Patent Laid-Open No. 63-194092 is known.

In the motor drive circuit described in the above publication, a relay is operated in response to a switching operation of a switch, and the operation of the relay forms an energization path to the motor.

[0004]

However, in the above-mentioned motor drive circuit, since the energization path to the motor is formed by the relay, it is considered that mechanical noise is not generated when the movable contact provided in the relay performs the switching operation. It is difficult to say, and when mechanical noise is generated, the noise is offensive to the ears, and thus there is a drawback that it gives an occupant an unpleasant feeling.

Further, since the relay switches the movable contact after the energization through the relay coil, the relay contacts from the timing of energizing the relay coil until the movable contact ends the switching operation. There is a possibility that a time lag may occur between them and it is difficult to improve the response performance.

Further, even when the energization path to the motor is cut off, a time lag may occur between the timing of stopping the energization of the relay coil and the end of the switching operation of the movable contact on the return side. Therefore, there is a drawback that the motor may coast without synchronizing with the switching of the switch.

[0007]

SUMMARY OF THE INVENTION The problem to be solved by the present invention is that when a current-carrying path to a motor is formed by a relay, mechanical noise may be generated to give an occupant an uncomfortable feeling. The point is that there is a limit to the improvement of response performance due to a time lag in the switching operation.

[0008]

The motor drive circuit according to the present invention does not give an occupant an uncomfortable feeling.
In order to provide excellent response performance, the source is connected to the emitter of the first transistor, the gate is connected to the collector of the first transistor, and the drain is connected to the brush terminal of the motor. A second FET having a gate connected to the emitter of the second transistor, a gate connected to the collector of the second transistor, and a drain connected to the brush terminal of the motor; and a gate of the first FET and a second F
A resistor connected in series with the gate of ET, and a first F
It is characterized in that an output stage having a diode connected between the source and the drain of the ET and between the source and the drain of the second FET is provided. In a more preferred embodiment, the output stage is provided to the motor. It is characterized in that the diode is connected in a forward direction to the power supply in a more preferable embodiment, and the operation is quiet and the response performance is excellent. Was realized.

[0009]

In the motor drive circuit according to the present invention, the gate inputs of the first FET and the second FET gradually reach the ON-operation potential after the time set by the resistor. Since the first FET and the second FET have a function of turning on separately after a preset delay time, they do not turn on at the same time. In addition, FET
Since the short circuit is formed by the diode and the motor, the motor stops in an instant. In addition, since there is no mechanical switching such as relays,
No noise is generated.

[0010]

1 and 2 show an embodiment of a motor drive circuit according to the present invention, showing a full-bridge motor drive circuit.

The illustrated motor drive circuit 1 mainly includes a first FET Q1, a second FET Q2, a first transistor Tr1, a second transistor Tr2, a third transistor Tr3, a resistor R1 and a first diode D1 ,. Second
From the diode D2 of the first output stage 1 to the motor 10
1 is configured.

Further, the third FET Q3 and the fourth FET Q
4, fourth transistor Tr4, fifth transistor T
A second output stage 12 is formed from the r5, the sixth transistor Tr6, the resistor R2, the third diode D3, and the fourth diode D4 with respect to the first output stage 11 as a pair.

The first and third FETs Q1 and Q3 are P-channel type, the second and fourth FETs Q2 and Q4 are N-channel type, and the first and fourth transistors Tr1 and T1.
r4 is a PNP type, and the second, third, fifth and sixth transistors Tr2, Tr3, Tr5, Tr6 are NPN type.

The source of the first FET Q1 of the first output stage 11 is connected to the emitter of the first transistor Tr1 and also to the power supply 50, and the drain of the first FET Q1 is one brush provided in the motor 10. Terminal 10a
It is connected to the.

The gate of the first FET Q1 is connected to the collector of the first transistor Tr1 and also to one end of the resistor r1.

A first diode D1 is connected between the source and the drain of the first FET Q1 in the forward direction from the drain to the source (toward the power supply 50). FET between source and gate
A bidirectional Zener diode ZD1 for protection is connected.

The base of the first transistor Tr1 is connected to the collector of the third transistor Tr3 via the resistor r3, and the resistor r4 is connected between the emitter and the base of the first transistor Tr1. The connection point between the resistor r4 and the emitter of the first transistor Tr1 is grounded via the resistors r5, r6, and r7.

Further, the connection point between the resistor r3 and the collector of the third transistor Tr3 and the resistor r5 and the resistor r6.
A fifth diode D5 is connected in the forward direction from the resistor r5 to the collector of the transistor Tr3 at the connection point of.

The emitter of the third transistor Tr3 is grounded, the base of the third transistor Tr3 is grounded via the resistor r8, and is also connected to the forward signal input terminal 2 via the resistor r9. Has been done.

The source of the second FET Q2 of the first output stage 11 is grounded, and the drain of the second FET Q2 is connected to the one brush terminal 10a of the motor 10.

The gate of the second FET Q2 is connected to the other end of the resistor r1 and the collector of the second transistor Tr2.

Then, between the source and drain of the second FET Q2, from the source to the drain (power source 50
The second diode D2 is connected in the forward direction, and the FE is connected between the source and the gate of the second FET Q2.
A bidirectional Zener diode ZD2 for T protection is connected.

The base of the second transistor Tr2 is connected to the connection point of the resistors r6 and r7.

The second output stage 12 is constructed symmetrically with the first output stage 11, and the source of the third FET Q3 of the second output stage 12 is connected to the emitter of the fourth transistor Tr4 and the power supply 50. Connected to the third FET Q
The drain of 3 is the other brush terminal 1 provided in the motor 10.
It is connected to 0b.

The gate of the third FET Q3 is connected to the collector of the fourth transistor Tr4 and to one end of the resistor r2.

A third diode D3 is connected between the source and the drain of the third FET Q3 in the forward direction from the drain to the source (toward the power supply 50), and the third diode D3 of the third FET Q3 is connected. FET between source and gate
A bidirectional Zener diode ZD3 for protection is connected.

The base of the fourth transistor Tr4 is connected to the collector of the sixth transistor Tr6 via the resistor r10, and the resistor r11 is connected between the emitter and the base of the fourth transistor Tr4. The connection point between the resistor r11 and the emitter of the fourth transistor Tr4 is grounded via the resistors r12, r13, r14.

In addition, at the connection point between the resistor r10 and the collector of the sixth transistor Tr6 and the connection point between the resistor r12 and the resistor r13, a forward direction from the resistor r12 to the collector of the sixth transistor Tr6 is provided. 6 diode D
6 is connected.

The emitter of the sixth transistor Tr6 is grounded, the base of the sixth transistor Tr6 is grounded via the resistor r15, and the resistor r1.
It is connected to the reverse side signal input terminal 3 via 6.

The source of the fourth FET Q4 of the second output stage 12 is grounded, and the drain of the fourth FET Q4 is connected to the other brush terminal 10b of the motor 10.

The gate of the fourth FET Q4 is connected to the other end of the resistor r2 and to the collector of the fifth transistor Tr5.

Then, between the source and drain of the fourth FET Q4, from the source to the drain (power source 50
The fourth diode D4 is connected in the forward direction, and the FE is connected between the source and the gate of the fourth FET Q4.
A bidirectional Zener diode ZD4 for T protection is connected.

The base of the fifth transistor Tr5 is connected to the connection point of the resistors r13 and r14.

The forward direction signal input terminal 2 and the reverse direction signal input terminal 3 are connected to a switch (not shown),
When this switch is switched to one side, the forward direction signal input terminal 2 becomes high level (1) and the reverse direction signal input terminal 3 becomes low level (0), and when the switch is switched to the other side, reverse The direction side signal input terminal 3 becomes high level (1) and the forward direction side signal input terminal 2 becomes low level (0). If the switches are not switched, the input terminals 2 and 3 both become low level (0).

Here, the gate input of the first FET Q1 gradually reaches the on-operation potential from the off-state by the time constant set by the product of the gate parasitic capacitance and the delay operation resistor r1. The FET Q1 is turned on after a delay time T1 from off as shown in FIG.

The second FET Q2 also has a resistor R1 and
Similarly to the first FET Q1, the third and fourth FETs Q3 and Q4 are connected to the resistor r2, and the delay time T2 from the off time T2 to the delay time T
3, Turns on after T4.

As is apparent from FIG. 2, the motor drive circuit 1 having such a structure has the forward direction signal input terminal 2 and the reverse direction signal input terminal 3 at the point A where the switches are not switched. Both are at a low level, and the power supply 50 → resistor r5 → resistor r6, resistor r7 → ground, power supply 50 → resistor r12 → resistor r13 → resistor r14 →
The second transistor Tr2 and the fifth transistor Tr5 are turned on by the energization of the ground.

Since the second transistor Tr2 and the fifth transistor Tr5 are on, the first FET Q1 of the first output stage 11 and the third FET Q3 of the second output stage 12 are both on and Second FET of 1 output stage 11
Q2, the fourth FET Q4 of the second output stage 12 is off, and the first FET Q1 and FET Q3 form a short circuit with respect to the brush terminals 10a and 10b of the motor 10, so that the motor 10 does not move. There is.

Therefore, when the switch is switched to the one side at the point B, the backward signal input terminal 3 remains at low level (0) and the forward signal input terminal 2 goes to high level (1). Transistor Tr3 turns on.

At the same time that the third transistor Tr3 is turned on, the base potential of the second transistor Tr2 is set to the low level to turn off the second transistor Tr2, and the base potential of the first transistor Tr1 is set to the low level. Then, the transistor Tr1 is turned on.

Since the second transistor Tr2 is turned off and the first transistor Tr1 is turned on,
The first FET Q1 of the first output stage 11 is cut off,
The second FET Q2 of the first output stage 11 turns on at the point C after the delay time T2 set by the resistor r1.

By turning on the second FET Q2 of the first output stage 11, the third FET Q3 of the second output stage 12 →
The other brush terminal 10b of the motor 10 → the one brush terminal 10a of the motor 10 → the second FET of the first output stage 11
Since the energization path is formed toward Q2, the motor shaft 10c included in the motor 10 is normally rotated.

Then, when the switch is returned from the one side at the point D, the forward and backward signal input terminals 2,
Since all 3 become low level (0), the base potential of the third transistor Tr3 becomes low level.
The third transistor Tr3 turns off, the first transistor Tr1 turns off, and the second transistor Tr2 turns on.

The first transistor Tr1 turns off and the second transistor
The second FET Q2 of the first output stage 11 is cut off by turning on the transistor Tr2 of 1., so that the energization path of the motor 10 is cut off.

Since the second transistor Tr2 is turned on, the first FET Q1 of the first output stage 11 has the resistor r
It is turned on at point E after a delay time T1 set from 1 and.

At this time, in synchronization with the turning off of the second FET Q2, the third FET Q3 of the second output stage 12 → the other brush terminal 10b of the motor 10 → the one brush terminal 10a of the motor 10 → the first diode D1. When a short circuit passing through the motor 10 is formed and the current flowing in the short circuit disappears, the counter electromotive force generated from the motor 10 causes the motor 10
One brush terminal 10a → the third diode D3 and the third diode → the first FETQ of the first output stage 11
1 → A short circuit passing through the other brush terminal 10b of the motor 10 is formed, so that the motor 10 stops in an instant.

Since the second transistor Tr2 is turned on, the first FET Q1 of the first output stage 11 has the resistor r
After a delay time T1 set from 1 and 1, the switch is turned on at point E to return to the state where the switch is not switched.

When the switch is switched to the other side at the point F, the forward direction signal input terminal 2 remains at low level (0) and the reverse direction signal input terminal 3 goes to high level (1). The transistor Tr6 of No. 6 is turned on.

At the same time when the sixth transistor Tr6 is turned on, the base potential of the fifth transistor Tr5 is set to low level to turn off the fifth transistor Tr5, and the base potential of the fourth transistor Tr4 is set to low level to fourth level. Then, the transistor Tr4 of is turned on.

By turning off the fifth transistor Tr5 and turning on the fourth transistor Tr4,
The third FET Q3 of the second output stage 12 is cut off,
The fourth FET Q4 of the second output stage 12 turns on at the point G after the delay time T4 set by the resistor r2.

When the fourth FET Q4 of the second output stage 12 is turned on, the first FET Q1 of the first output stage 11 →
One brush terminal 10a of the motor 10 → the other brush terminal 10b of the motor 10 → the fourth FET of the second output stage 12
Since the energization path is formed toward Q4, the motor shaft 10c included in the motor 10 is rotated in the reverse direction.

Further, when the switch is returned from the other side at the H point, both the forward direction side and reverse direction side signal input terminals 2 and 3 become low level (0).
Since the base current of the transistor Tr6 becomes low level, the sixth transistor Tr6 is turned off, the fourth transistor Tr4 is turned off, and the fifth transistor Tr5 is turned on.

The fourth transistor Tr4 turns off, and the fifth transistor Tr4
By turning on the transistor Tr5 of the above, the fourth FET Q4 of the second output stage 12 is cut off, so that the energization path of the motor 10 is cut off.

Since the fifth transistor Tr5 is turned on, the third FET Q3 of the second output stage 12 has a resistor r
After the delay time T3 set by 2 and 2, it turns on at point I.

At this time, in synchronization with the turning off of the fourth FET Q4, the first FET Q1 of the first output stage 11 → one brush terminal 10a of the motor 10 → the other brush terminal 10b of the motor 10 → the third diode D3. When a short circuit passing through the motor 10 is formed and the current flowing in the short circuit disappears, the counter electromotive force generated from the motor 10 causes the motor 10
One brush terminal 10a → first FET Q1 and first diode D1 → third FET Q of second output stage 12
3 → Since a short circuit passing through the other brush terminal 10b of the motor is formed, the motor 10 stops instantly.

Here, the diode D1 and the diode D are provided from the time when the switch is restored to the point B, from the point E to the point F, and when the switch is restored from the point I.
3, the first FET Q1 of the first output stage 11, the second output stage 1
Since the short circuit is formed by the second third FET Q3, the motor 10 is held stationary.

FIG. 3 shows another embodiment of the motor drive circuit according to the present invention, showing a half-bridge motor drive circuit.

The motor drive circuit 1 in this case is composed of only the first output stage 11 shown in FIG.
The other brush terminal 10b is connected to the power supply 50.

In this case, when the signal input terminal 2 on the positive direction side is at the low level (0), the second transistor Tr2 is on, so the first FET Q1 is on and the second FE is on.
TQ2 is off.

When the signal input terminal 2 on the positive direction side is at high level (1), the first FET Q1 is cut off, and the second FET Q1 is cut off.
FET Q2 of the delay time T set by the resistor r1
When turned on after 2, the energization path is formed in the motor 10, and the forward direction side signal input terminal 2 is at low level (0).
And a short circuit passing through one brush terminal 10a of the motor 10 → the other brush terminal 10b of the motor 10 → the first diode D1 is formed in synchronism with the second FET Q2 being turned off.

When the signal input terminal 2 on the positive direction side becomes low level (0), the second transistor 2 is turned on, so that the first FET Q1 has the delay time T1 set by the resistor r1. It turns on later and returns.

[0062]

As described above, since the motor drive circuit according to the present invention has the above-mentioned configuration, the first FET and the second FET are separately turned on after the preset delay time. Since it does not turn on at the same time and does not generate mechanical noise due to relays, etc., it does not cause occupant discomfort, quiet operation can be performed, and the FET and diode allow the motor to operate. On the other hand, since the short circuit is formed, the motor can be controlled surely, and the excellent response performance can be achieved.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of an embodiment of a motor drive circuit according to the present invention.

FIG. 2 is a time chart explaining the operation of the motor drive circuit shown in FIG.

FIG. 3 is a circuit configuration diagram of another embodiment of the motor drive circuit according to the present invention.

[Explanation of symbols]

1 Motor Drive Circuit 10 Motors 10a, 10b Brush Terminals 11, 12 (Output Stage) First Output Stage, Second Output Stage D1, D2, D3, D4, Diode Q1 (Q3) First FET (Third FET) Q2 (Q4) 2nd FET (4th FET) r1 (r2) Resistor Tr1 (Tr4) 1st transistor (4th transistor) Tr2 (Tr5) 2nd transistor (5th transistor)

Claims (3)

[Claims] 1. A first FET having a source connected to the emitter of the first transistor, a gate connected to the collector of the first transistor, and a drain connected to the brush terminal of the motor.
A second FET having a source connected to the emitter of the second transistor, a gate connected to the collector of the second transistor, and a drain connected to the brush terminal of the motor; and a gate and a second FET of the first FET. Between the resistor connected in series with the gate of the first FET and the source and drain of the first FET, and the second FET
A motor drive circuit comprising an output stage having a diode connected between the source and the drain of the motor drive circuit. 2. The motor drive circuit according to claim 1, wherein a pair of output stages is provided for the motor. 3. The motor drive circuit according to claim 1, wherein the diode is connected to the power supply in the forward direction.