JP3225159B2 - DC motor control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DC motor control device for controlling a motor by a phase synchronization system.

[0002]

2. Description of the Related Art Conventionally, in a DC motor control device of this type, as shown in FIG. 4, an encoder (for example, a two-phase type 1a, an output from the encoder 1a is supplied to a frequency dividing circuit 2, an output of the frequency dividing circuit 2 is supplied to a PLL (phase synchronization) control circuit 3, and the output from the PLL control circuit 3 The speed output and the phase output are supplied to an amplifier 4, which supplies a motor drive output amplified based on these outputs to a motor drive circuit 5, and supplies a drive current to the motor from the motor drive circuit 5. Had become.

The PLL control circuit 3 compares a phase signal from an encoder with a predetermined phase signal, and outputs a motor drive signal according to the comparison result to perform voltage phase control of the motor. is there.

The motor driving circuit 5 includes a PNP transistor 6 and an NPN transistor 7 connected in Darlington. And this PNP transistor 6
Has an emitter connected to the power supply voltage VCC via a resistor 10, a collector grounded via a resistor 8, and a base connected to the output terminal of the amplifier 4.

[0005] The NPN transistor 7 is
Its emitter is grounded via a resistor 9 and
A collector is connected to one of a pair of terminals of the DC motor 1, and a base is connected to a collector of the PNP transistor 6. The other terminal of the DC motor 1 is connected to a power terminal V through a fuse 11.
Connected to C.

The amplifier 4 outputs a motor drive signal VS as shown in FIG. 5A in accordance with the output (frequency) of the encoder 1a of the DC motor 1. That is, when the frequency for the target speed (the target current based on the set pulse of the oscillation circuit of the PLL control circuit) is underspeed, the motor drive signal VS at the H level is output as shown in the frequency range A. The base current of the transistor 7 at this time is as shown in a range A of FIG. 5B, and in this case, the transistor 7 is used in a saturation region. When the output relative to the target speed is overspeed, an L level motor drive signal as shown in a frequency range C is output.

In a lock range B in which the frequency with respect to the target speed is between the underspeed and the overspeed (a range that can be controlled by the PLL control circuit), a motor drive signal VS having an intermediate value from L level to H level proportional to the frequency is generated. Is output. The base current of the transistor 7 at this time is as shown in a range B of FIG. 5B, and in this case, the transistor 7 is used in an unsaturated region.

When such a motor drive signal VS is output from the amplifier 4, the base current of the transistor 8 and the supply current supplied to the DC motor are shown in FIGS. 5 (b) and 5 (c), respectively. It becomes as shown in.

In the DC motor control device having such a configuration, when a motor start signal is supplied to the PLL control circuit 3, the motor drive current as shown in FIG.
Supplied to That is, a current corresponding to the output (frequency) of the encoder 1a is supplied to the DC motor 1 via the frequency dividing circuit 2, the PLL control circuit 3, the amplifier 4, and the motor driving circuit 21.

Specifically, for example, when the motor is started, if the target speed (target current value) is underspeed, the amplifier 4 outputs a motor drive signal of H level. Thereafter, until the overspeed occurs, the amplifier 4 outputs a motor drive signal of an intermediate level between the H level and the L level. By supplying the intermediate-level motor drive signal to the DC motor in this manner, a current corresponding to the speed of the DC motor 1 is supplied.

[0011]

Generally, a transistor has a property of generating a large amount of heat when used in an unsaturated region.

However, in the above-described DC motor control device, the motor drive control is performed by a motor drive signal at an intermediate level between the H level and the L level.
As shown in FIG. 5B, the transistor is used in an unsaturated region, and there is a problem that heat generation of the transistor itself increases. For this reason, it has been necessary to attach a heat sink for heat dissipation.

Accordingly, an object of the present invention is to provide a DC motor control device capable of minimizing heat generation of a semiconductor switching element.

[0014]

SUMMARY OF THE INVENTION The present invention relates to a DC motor control device for controlling a motor by a phase synchronization method, comprising: a motor drive circuit for driving the DC motor by turning on and off semiconductor switching elements; A phase signal converting means provided in the DC motor and converting the rotational movement of the DC motor into a phase signal, and comparing the phase signal from the phase signal converting means with a predetermined phase signal, and according to the result of the comparison. A phase synchronization control circuit for outputting a motor drive signal; a motor voltage detection means for detecting a current supplied to the DC motor as a voltage level; and a voltage level from the motor voltage detection means and a motor from the phase synchronization control circuit. The drive signal level is compared with the drive signal level, and the control signal for turning on / off the semiconductor switching element is driven according to the comparison result. A voltage comparator for supplying the road provided,
The DC motor is driven by supplying a chopping current to the DC motor by the on / off operation of the semiconductor switching element.

[0015]

In the present invention having such a configuration, when the DC motor is driven, the drive signal output from the phase synchronization control circuit is supplied to the voltage comparator according to the output of the phase signal conversion means. Then, the voltage comparator compares the motor drive signal level from the phase synchronization control circuit with the voltage level from the motor voltage detection means, and generates a control signal for turning on / off the semiconductor switching element according to the comparison result. The DC motor is driven by supplying the chopping current by supplying the DC motor to the motor drive circuit.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. The same parts as those shown in FIG. 4 are denoted by the same reference numerals, and detailed description will be omitted.

FIG. 1 is a block diagram showing the configuration of this embodiment. The difference from FIG. 4 is that a motor drive circuit 21 has a bridge circuit instead of a pair of transistors 6 and 7.
MOS FETs (field effect transistors) 25, 2
6, 27, 28, instead of supplying the output from the PLL control circuit 3 directly to the motor drive circuit 21 via the amplifier 4, a comparator 22 as a voltage comparator is further provided.
In addition, a motor control signal is supplied to the motor drive circuit 21 indirectly via the control unit 23.

More specifically, the motor drive circuit 21 includes a series circuit including a P-channel type FET 25 and an N-channel type FET 26 between a power supply terminal VC and ground via a resistor 24 as a motor voltage detecting means, and a P-channel type. FET
27 and a series circuit composed of an N-channel FET 28 intervene in parallel.

The connection point between the P-channel FET 27 and the N-channel FET 28 is connected to one terminal of the DC motor 1, and the connection point between the P-channel FET 25 and the N-channel FET 26 is Is connected to the other terminal.

These FETs 25, 26, 27,
The base 28 is connected to four output terminals of the control unit 23 via resistors 31, 32, 33, and 34, respectively.

The control unit 23 controls the forward and reverse rotation of the DC motor 1. That is, for example, FE
When a motor drive control signal is supplied to T25 and T28, the DC motor rotates in the forward direction.
When a motor drive control signal is supplied to the DC motor 7, the DC motor rotates in the reverse direction.

The input terminal of the control unit 23 is the comparator 2
The output terminal of the amplifier 4 is connected to the reference voltage input terminal of the comparator 22. The comparison voltage input terminal of the comparator 22 is connected to a connection point between the FETs 26 and 28 of the motor drive circuit 21 and the resistor 24.

The comparator 22 receives the signal from the amplifier 4 shown in FIG.
The voltage VS of the motor drive signal as shown in FIG. 7A is compared with the divided voltage VR by the resistor 24 based on the current supplied to the motor drive circuit 21, and the control unit 23 is operated in accordance with the comparison result. A control signal for turning on / off the FET (switching operation) is supplied.

That is, when the divided voltage VR is equal to or less than the voltage VS of the motor drive signal,
An on signal for turning on the FETs 25, 28 or 26, 27 is supplied to the control unit 23, and when the divided voltage VR is higher than the motor drive signal voltage VS, the control unit
An off signal for turning off 5, 28 or 26, 27 is supplied.

Thus, the FET 25, 28 or 26,
The base 27 is supplied with a chopped current as shown in FIG. 2 (b), and the output voltage VS of the amplifier 4 is reduced as shown in FIG.
Even in the case of the lock range B shown in FIG.
5, 28 or 26, 27 are used in the saturation region. Therefore, the FETs 25, 28 or 26, 27 are not used in the unsaturated region.

Specifically, when the output voltage VS of the amplifier 4 is within the lock range B shown in FIG.
When the divided voltage VR of the motor drive circuit 21 becomes larger, the FETs 25, 28 or 26, 27 are turned off, and as shown in FIG.
FET2 with the current in the slope portion of FIG.
The current flowing at the base of 5, 28 or 26, 27 is chopped.

At this time, the current supplied to the DC motor 1 is, as shown in FIG.
Since the ON / OFF control of the transistors 6 and 27 is performed, the current repeatedly increases and decreases with a constant width y, but when viewed macroscopically, the waveform is substantially the same as the motor drive signal of the amplifier 4.

The comparator 22 is provided with a timer 22a, which counts a very short predetermined time from the generation of the OFF signal. That is, the off signal is sent to the control unit 2
3, the current does not flow through the resistor 24, the divided voltage VR becomes zero, and the divided voltage VR becomes lower than the voltage VS of the motor drive signal, thereby preventing the ON signal from being supplied immediately after the OFF signal is supplied. Therefore, the ON signal is not generated until a predetermined time has elapsed from the generation of the OFF signal.

In this embodiment having such a configuration, when a motor start signal is supplied to the PLL control circuit 3, a motor drive current as shown in FIG. That is, the DC motor 1 includes the frequency dividing circuit 2 and the PLL
A current corresponding to the output (frequency) of the encoder 1a is supplied via the control circuit 3, the amplifier 4, and the motor drive circuit 21.

More specifically, the current supplied to the DC motor 1 has a large phase difference between the output from the encoder 1a and a preset target speed at the time of starting the motor (under speed). The current value a rises rapidly and becomes the current value a. After that, when the vehicle reaches overspeed, it descends rapidly, but when it descends too much, it rises again. By repeating this, it converges to the target speed.

At this time, the FETs 25, 28 or 26, 2
The base current flowing to 7 is chopped by the comparison result of the comparator. In particular, FETs 25, 28 or 26,
When 27 is used in the lock range B shown in FIG. 2, for example, when the supply current to the DC motor 1 is the current value b or c, it is also turned on / off, so that the FET 25, 28 or 26,
27 is used in the saturation region.

As described above, the voltage VS output from the PLL control circuit 3 via the amplifier 4 and the divided voltage VR from the motor drive circuit 21 are compared, and the control unit 23 transmits the voltage VS according to the comparison result. A motor control signal is supplied to the motor drive circuit 21 to turn on / off the FET 25, 28 or 26, 27 (switching operation) of the motor drive circuit 21, so that the output from the PLL control circuit 3 is H level and L level. F, even in the lock range.
ET can be used in the saturation region.

Therefore, when the motor is driven, the FETs 25, 2
8 or 26, 27 are not used in the unsaturated region. Therefore, heat generation of the FET of the motor drive circuit 21 can be suppressed as much as possible. Thus, there is no need to attach a heat sink or the like.

Further, since a FET is used instead of using a transistor as in the prior art, heat generation of the motor drive circuit 21 can be further suppressed.

Further, the motor drive circuit 21 is provided with four FETs constituting a bridge circuit, and the control circuit 23 selectively supplies a drive current to the FETs. Can be.

In the present embodiment, the description has been given of the case where the FET is used as the semiconductor switching element. However, the present invention is not limited to this, and a transistor may be used.

[0037]

As described above in detail, according to the present invention, it is possible to provide a control device for a DC motor capable of minimizing heat generation of a semiconductor switching element.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention.

FIG. 2 shows an amplifier and an FE for a frequency in the embodiment.
The figure which shows the base current of T, and the supply current to a motor.

FIG. 3 is a diagram showing a time change of a current supplied to a DC motor in the embodiment.

FIG. 4 is a block diagram showing a configuration of a conventional DC motor control device.

FIG. 5 is a diagram showing an amplifier, a base current of an FET, and a current supplied to a motor with respect to a frequency in a conventional DC motor control device.

FIG. 6 is a diagram showing a time change of a supply current to a DC motor in a conventional DC motor control device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... DC motor 1a ... Encoder 3 ... PLL control circuit 6,7 ... Transistor 21 ... Motor drive circuit 23 ... Comparator 25,26,27,27 ... FET

Claims (1)

(57) [Claims] 1. A control device for a DC motor that performs motor control by a phase synchronization method, comprising: a motor drive circuit that drives the DC motor by turning on / off a semiconductor switching element; A phase signal converting means for converting the rotational motion of the DC motor into a phase signal; comparing the phase signal from the phase signal converting means with a predetermined phase signal; and outputting a motor drive signal according to the result of the comparison. A phase synchronization control circuit, a motor voltage detection means for detecting a current supplied to the DC motor as a voltage level, a voltage level from the motor voltage detection means and a motor drive signal level from the phase synchronization control circuit. And the voltage level is
On operating the semiconductor switching element when the No. levels below
If the voltage level is higher than the motor drive signal level,
A voltage comparator for supplying a control signal for turning off the semiconductor switching element to a motor drive circuit, and driving the DC motor by supplying a chopping current by turning on and off the semiconductor switching element to the DC motor. A control device for a DC motor.