JP3065580B2 - DC motor drive circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an induced electromotive force sensing type DC motor drive circuit which detects an induced electromotive force generated according to the rotation speed of an armature and controls the driving of a DC motor. .

[0002]

2. Description of the Related Art The inventor has previously proposed a circuit shown in FIG. 3 as a DC motor drive circuit of an induced electromotive force sensing type capable of controlling a restraining torque.

[0003] In FIG. 3, the DC motor 1 is connected at one end to the DC power supply terminal 6 to which a DC voltage + V _c is supplied,
The other end is the drain D of the field effect transistor (FET) 2
It is connected to the. Terminal of the DC motor 1 of the FET2 side is connected to the inverting input terminal of the voltage comparator 3 via a resistor R _3. The source of the FET 2 is grounded, and the gate G is connected to the output terminal of the AND gate 4.

A resistor R ₁ , a variable resistor VR ₁ and a resistor R
One end of the series circuit consisting of ₂ is connected to the DC power supply terminal 6, the other end of the series circuit (the resistor R ₂ side) is grounded. Variable resistor VR ₁ is connected between the resistors R ₁ and R _2, the sliding contact of the variable resistor VR ₁ is connected to the non-inverting input terminal of the voltage comparator 3. Therefore, this non-inverting input terminal of the voltage comparator 3, a DC voltage + V _c resistors R _1, R ₂ and the variable resistor setting voltage V ₂ divided by the resistance value of VR ₁ is supplied. The set voltage V ₂ is a voltage for setting the restraining torque of the DC motor 1 (the limit torque when the motor 1 is determined to be in the restraining state and the motor 1 is stopped).

The voltage comparator 3 has a setting voltage V ₂ supplied to the non-inverting input terminal and a voltage V ₂ supplied to the inverting input terminal.
Compare with _M. Then, the voltage comparator 3 outputs a voltage V ₀ which high level when the voltage V ₂ greater than the voltage V _M, the output voltage V ₀ which low level when the voltage V ₂ is smaller than the voltage V _M I do. The output terminal of the voltage comparator 3 is connected to one input terminal of the AND gate 4.

[0006] The other input terminal of the AND gate 4 is connected to the output terminal of the oscillator 5 and supplied with the cutoff pulse P ₁ from the oscillator 5. The AND gate 4 calculates the logical product of the output voltage V ₀ of the voltage comparator 3 and the cutoff pulse P ₁ and supplies an output signal to the gate G of the FET 2. When the output signal of the AND gate 4 is at a high level, the FET 2 is turned on, and when the output signal is at a low level, the FET 2 is turned off. Blocking pulses P ₁ described above is an oscillation signal comprising only a low level instantaneously every predetermined period T.

[0007] Next, FIG.
The operation of the DC motor drive circuit shown in FIG.

It is assumed that the output shaft (not shown) of the DC motor 1 is rotated by an external force, and the armature is rotated. Due to the rotation of the armature, both ends of the DC motor 1
As shown in FIG. 7, an induced electromotive force E _M proportional to the rotation speed of the armature is generated. For this reason, a voltage V _M expressed by the following equation is generated at the drain D of the FET 2.

V _M = V _C -E _M

[0010] The voltage V _M is supplied to the inverting input terminal of the voltage comparator 3. The induced electromotive with power E _M increases, when the voltage V _M is smaller than the set voltage V _2, the voltage comparator 3 changes the output voltage V ₀ from the low level to the high level. For this purpose, a cutoff pulse P ₁ is supplied to the gate G of the FET 2 as an output signal of the AND gate 4. Then, FET2 is turned on when blocking pulse P ₁ is at a high level. Therefore, the DC voltage + V _C is applied to the DC motor 1, and the output shaft of the DC motor 1 continues to rotate.

[0011] The output shaft of the DC motor 1 is to be while continuing rotation, blocking pulses P ₁ becomes low level periodically instantaneously. For this reason, the FET 2 is similarly turned off instantaneously periodically. In the period of the off state of the FET2, the voltage V _M is smaller than the set voltage V _2, blocking pulse P ₁ as an output signal of the AND gate 4 is continuously supplied to the gate G of the FET2. Therefore, FET2
Continuously repeats the ON state and the OFF state. Conversely, the voltage V _M at the time of the OFF state of the FET2 is set voltage V
If greater than _2, the output voltage V ₀ which voltage comparator 3 changes to the low level. Therefore, the output signal of the AND gate 4 is continuously at a low level.
Keeps the off state and enters the power supply cutoff state.

The current I _M flowing through the DC motor 1 at the boundary between whether the motor 1 can continue to rotate or whether the FET 2 continues to be in the OFF state and enters the power supply cutoff state depends on the internal resistance of the DC motor 1. _Assuming that r _M , it is expressed by the following equation.

I _M ≒ V ₂ / r _M (= (V _C -E _M ) / r _M )

Therefore, by controlling the voltage V ₂ , it is possible to control the restraining torque of the DC motor 1 and control its driving state. Then, for control of the voltage V _2, the variable resistor VR ₁ is adjusted.

[0015] In the case of a DC motor drive circuit described above shown in FIG. 3, for the period T of the blocking pulses P ₁ is constant, variable width of the restraining torque of the DC motor 1 has a problem that narrow. That is, in order for the FET 2 to be turned on, the induced electromotive force must be equal to or more than a predetermined value. When the cycle T is short, the variable resistor VR _{1 is connected} to the resistor R ₁ in order to maximize the constraint torque. However, there is a problem that it is difficult to obtain the maximum drive current I _M ′ (= V _C / r _M ). Also, conversely, when the long period T, the resistance to the variable resistor VR ₁ in order to reduce the constraint torque R
Be set to ₂ side, it is impossible to sufficiently reduce the driving current I _M during the restrictive torque.

[0016]

Further, in the case of the above-described DC motor driving circuit shown in FIG. 3, the DC motor speed control which can reliably determine the restraint state with a simple configuration is simple. I couldn't do it for sure.

SUMMARY OF THE INVENTION The present invention solves the above-mentioned drawbacks, and enables a DC motor capable of reliably determining the restrained state with a simple configuration to reliably perform a DC motor speed control with a simple configuration. It is an object to provide a drive circuit.

[0018]

A DC motor driving circuit according to the present invention comprises a voltage comparator for comparing an induced electromotive force generated at a terminal of a DC motor with a preset voltage, and an output signal of the voltage comparator. A drive transistor for turning on the DC motor to supply a drive voltage to the DC motor, a pulse generating circuit for periodically generating a cutoff pulse for instantaneously turning off the drive transistor, and changing a duty cycle of the cutoff pulse. Speed setting means.

[0019]

An embodiment of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of a DC motor drive circuit according to the present invention. 1, the same reference numerals as those in FIG. 3 denote the same components. Then, in order to avoid duplication with the description of FIG. 3, only the portions different from the configuration of FIG. 3 will be described below.

In FIG. 1, the input terminal of the sawtooth wave forming circuit 12 is connected to the gate G of the FET (drive transistor) 2. The sawtooth wave forming circuit 12 includes a resistor R ₄ ,
R ₅ , variable resistor (speed setting unit) VR ₂ , diode D
₁ , D ₂ and capacitor C ₁ . That is, between the gate G and the sliding contact of the variable resistor VR ₂ of FET2, the resistance R ₄ is connected. Variable resistor V
One end of R ₂ is connected to one end of resistor R _5, the other end of the resistor R ₅ is connected to the anode of the diode D _1, the cathode of the diode D ₁ is connected to the capacitor C _1. The other end of the variable resistor VR ₂ is connected to the cathode of the diode D _2, the anode of the diode D _2, the capacitor C ₁
It is connected to, and is connected to the cathode of the diode D _1. Thus, one end of the capacitor C ₁ is connected to the diode D ₁ and D _2, and the other end of the capacitor C ₁ is grounded. A connection point between the capacitor C ₁ and the diodes D ₁ and D ₂ is an output terminal of the sawtooth wave forming circuit 12.

The output terminal of the sawtooth wave forming circuit 12 is connected to the inverting input terminal of the voltage comparator 7 and the non-inverting input terminal of the voltage comparator 8. The non-inverting input terminal of the voltage comparator 7 is connected to the sliding contact of the variable resistor VR ₁ for torque control. Therefore, the non-inverting input terminal of the voltage comparator 7, is supplied set voltage V _2. Therefore, the voltage comparator 7 compares the output voltage V _N of the set voltage V ₂ and the sawtooth wave forming circuit 12. When the set voltage V ₂ is larger than the output voltage V _N , the voltage comparator 7
Outputs a voltage V _3, and outputs a voltage V ₃ of the low level L when the voltage V ₂ is smaller than the voltage V _N. The output terminal of the voltage comparator 7 is connected to the set input terminal SET of the pulse forming circuit 11.

The inverting input terminal of the voltage comparator 8 is supplied with a reference voltage V _{1 obtained by} dividing the DC voltage + V _C by the resistance values of the resistors R ₆ and R ₇ . Therefore, this voltage comparator 8
Compares the voltage V _N supplied to the non-inverting input terminal with the reference voltage V ₁ supplied to the inverting input terminal. And
The voltage comparator 8 outputs a voltage V ₄ of the high level H when the voltage V _N is greater than voltages V _1, the voltage V ₄ of the low level L when the voltage V _N is smaller than voltages V ₁ Output. The output terminal of the voltage comparator 8 is a pulse forming circuit 11
Is connected to the reset input terminal RES.

In this embodiment, the pulse forming circuit 11 comprises an RS flip-flop comprising NAND gates 9 and 10. Therefore, when both the set input terminal SET on the NAND gate 9 side and the reset input terminal RES on the NAND gate 10 side are set to a high level voltage, the output terminal of the pulse forming circuit 11 (the NAND gate 10)
Output terminals of the) outputs a voltage P ₂ of a high level H. In this state, if the input of the set input terminal SET goes low for a moment, the output terminal of the pulse forming circuit 11 goes low.
It retains its state output voltage P _2. Further, the input of the reset input terminal RES becomes low, the output terminal of the pulse forming circuit 11 outputs a voltage P ₂ of a high level H. The output terminal of the pulse forming circuit 11 is connected to one input terminal of the AND gate 4. 3, an oscillator 5 is connected to this input terminal of the AND gate 4. In FIG. 1, instead of the oscillator 5 of FIG. 3, a sawtooth wave forming circuit 12, comparators 7, 8, and a pulse forming circuit are connected. A pulse generation circuit including a circuit 11 and the like is connected.

Next, FIG. 1 having such a configuration will be described.
2 will be described with reference to a time chart shown in FIG. Here, FIG. 2 is a time chart showing voltage waveforms of main parts of the DC motor drive circuit of FIG.

First, the case where the DC motor 1 is at rest will be described. When the DC motor 1 is at rest, the induced electromotive force E _M is because it is zero, the voltage V _M is a value of the DC voltage + V _c. Therefore, since the voltage V _M greater than the set voltage V _2, the output voltage V ₀ which voltage comparator 3 is in the low level. For this reason, the output signal of the AND gate 4 is also at a low level, so that the FET
The drain-source 2 is in an off state. Also, since the output signal of the AND gate 4 is at a low level,
The output voltage V _N of the sawtooth wave forming circuit 12 is also a low level voltage (0
V) (the state before time t _{1 in} FIG. 2).

[0027] In this case, even the charge had somewhat capacitor C _1, the charge of the capacitor C ₁ is thus discharged through a path consisting of the diode D _2, the variable resistor VR ₂ and the resistor R _4.

When the output voltage V _N of the sawtooth wave forming circuit 12 is a low level voltage, the output voltage V ₃ of the voltage comparator 7
Is a high level H voltage. Similarly, the output voltage V ₄ of the voltage comparator 8 is a low level L voltage. For this purpose, a high level H voltage V ₃ is supplied to the set input terminal SET of the pulse forming circuit 11, and a low level L voltage V ₄ is supplied to the reset input terminal RES. Pulse forming circuit 11, the voltage V ₄ is supplied to the reset input terminal RES becomes low level L, as shown in time point t ₁ in FIG. 2, the high level H to the output terminal
Outputs an output signal P _2. This high level H output signal P ₂ is supplied to the input terminal of the AND gate 4.

Next, it is assumed that the output shaft (not shown) of the DC motor 1 is rotated by an external force, and the armature connected to the output shaft is rotated. By the rotation of this armature,
As mentioned in the case of FIG. 3, because the induced electromotive force E _M is generated across the DC motor 1, the voltage V _M is the DC voltage + V _C
From the value of. Then, the voltage V _M is set voltage V
Becomes smaller than _2, the voltage comparator 3 changes the output voltage V ₀ from the low level to the high level. At this time, the output signal P ₂ pulse forming circuit 11 is in the voltage of the high level H, both the input voltage of the AND gate 4 goes high. Therefore, the output signal of the AND gate 4 becomes a high level voltage, and the drain-source of the FET 2 is turned on. As a result, the DC voltage + V _C is applied to the DC motor 1, and the output shaft of the DC motor 1 continues to rotate.

On the other hand, when the output signal of the AND gate 4 becomes a high level voltage, the sawtooth wave forming circuit 12 causes the resistance R ₄ ,
A current flows through a path composed of the variable resistor VR ₂ , the resistor R _5, and the diode D ₁ , and the capacitor C ₁ is charged (period t ₁ to t _{2 in} FIG. 2). Therefore,
Output voltage V _N of the sawtooth wave forming circuit 12 gradually increases. When this voltage V _N has reached the value of the reference voltage V _1, the voltage comparator 8 high level H output voltage V ₄ from the low level L
(Time t _{2 in} FIG. ₂ ). Pulse forming circuit 11
Since the voltage V ₄ is supplied to the reset input terminal RES goes high H, it is released from the reset state. However, in this case, the output signal P ₂ pulse forming circuit 11 is in a still higher level voltage.

After time t ₂ , the sawtooth wave forming circuit 1
The output voltage V _N of No. 2 keeps rising gradually. And
When the voltage V _N has reached the value of set voltage V _2, the voltage comparator 7 changes the output voltage V ₃ from the high level H to low level L (time t ₃ in FIG. 2). When the voltage V ₃ becomes low level L, the pulse forming circuit 11, the input of the set input terminal SET goes low voltage, and its output signal P ₂ to the voltage of the low level L to maintain this state. Therefore, the output signal of the AND gate 4 is low because one of its input signals is low, and the FET 2 is turned off.

[0032] When the output signal of the AND gate 4 goes low, the charge stored in the capacitor C _1, through a path consisting of the diode D _2, the variable resistor VR ₂ and the resistor R _4, immediately begins to discharge I do. For this reason, the output voltage V _N of the sawtooth wave forming circuit 12 immediately drops below the value of the set voltage V ₂ . Therefore, the voltage comparator 7 is changed from low level L to the output voltage V ₃ again to the high level H. At this time, the output signal P ₂ pulse forming circuit 11 is held at a voltage of low level L (between times t ₃ and t ₄ in FIG. 2).

As described above, when the output signal P ₂ of the pulse forming circuit 11 is at the low level L, the FET 2 is in the off state, and it is detected whether or not the DC motor 1 is in the locked state. In this case, the voltage V _M set voltage V ₂
If it is larger than this, the output voltage V ₀ of the voltage comparator 3 changes to a low level. Therefore, the output signal of the AND gate 4 goes low, so that the FET 2 keeps off. As a result, the DC motor 1 has a DC voltage + V _C
Is not applied, the output shaft of the DC motor 1 stops rotating.

On the other hand, the output signal P ₂ of the pulse forming circuit 11
There at the low level voltage, the smaller the voltage V _M than the set voltage V _2, the output voltage V ₀ which voltage comparator 3 holds the high level.

As described above, between the time points t ₃ and t ₄ in FIG. 2, the charge charged in the capacitor C ₁ continues to be discharged, so that the voltage V _N continues to decrease. Then, when the voltage V _N reaches the value of the reference voltage V _1, the voltage comparator 8 changes the output voltage V ₄ from the high level H to low level L (time t ₄ in FIG. 2). Pulse forming circuit 11, the voltage V ₄ is supplied to the reset input terminal RES becomes low level, and the reset state. That is, the output signal P ₂ pulse forming circuit 11 becomes a voltage of the high level H.

The AND gate 4 changes its output signal to the high level again because both input signals have the high level H voltage. For this reason, since the area between the drain and source of the FET 2 is turned on again, the output shaft of the DC motor 1 continues to rotate. When the output signal of the AND gate 4 becomes a high level voltage, the sawtooth wave forming circuit 12, a capacitor C ₁ is the resistance R _4, immediately via a path consisting of the variable resistor VR _2, resistor R ₅ and the diode D ₁ charge To start. For this, the output voltage V _N of the sawtooth wave forming circuit 12 rises above the value of the reference voltages V ₁ immediately. Therefore, the voltage comparator 8 is changed from low level L to the output voltage V ₄ again to the high level H.

Thereafter, the output signal P ₂ of the pulse forming circuit 11
There at low level L, the smaller the voltage V _M than the set voltage V _2, as shown in FIG. 2, the time t ₄ from the time t ₂
The same operation is repeated with the period up to one cycle.

In this case, the output signal P ₂ corresponds to the cutoff pulse P ₁ output from the oscillator 5 shown in FIG. However, in the present embodiment, the voltage comparator 7 is so as to set the duration of the voltage V _N and the set voltage V ₂ is compared with the high level H of the output signal P _2. Therefore, in this embodiment, the restraining torque of the DC motor 1 can be controlled in a wide range.

For example, a variable resistor V for restraining torque control
Setting R ₁ to the resistor R ₁ side (high torque side), the set voltage V ₂ becomes a large value. For this reason, even if the number of rotations of the output shaft of the DC motor 1 is slightly reduced, the output voltage V ₀ of the voltage comparator 3 is kept at a high level, so that the FET 2 is kept on. At the same time, the voltage supplied to the non-inverting input terminal of the voltage comparator 7 increases, so that the set voltage V
Periods of high level of the output signal P ₂ in response to the ₂ increases increases. That is, this output signal (cutoff pulse)
Since the cycle of P ₂ becomes longer, the constraint torque is made sufficiently large as necessary, and the maximum drive current I _M ′ = (V _C / r _M )
Can be easily obtained.

On the contrary, the variable resistor VR _{1 is connected} to the resistor R
_If it is set to the _second side (low torque side), the FET 2 is turned off even if the rotation speed of the output shaft of the DC motor 1 is slightly decreased. At the same time, because even shorter period of the output signal P _2, it is possible to sufficiently small as necessary driving current I _M during the restrictive torque.

Next, the variable resistor VR ₂ in the sawtooth wave forming circuit 12 changes the voltage rising speed and the voltage falling speed of the output voltage V _N simultaneously in opposite directions to rotate the output shaft of the DC motor 1. This is for controlling the number (speed).
That is, by changing the resistance value of the variable resistor VR _2, the voltage rise speed of the output voltage V _N (proportional to the reciprocal of the time from the time t ₂ in FIG. 2 to time t _3), the voltage lowering speed (FIG. 2 since the time of the reciprocal of the time t ₃ to time t ₄ proportional) and can be changed simultaneously in opposite directions, it is possible to vary the duty cycle of the output signal P _2. Then, by changing the duty cycle of the output signal P _2, it is possible to perform speed control of the DC motor 1.

[0042]

According to the present invention, since the restraint state of the DC motor is determined by the voltage comparator, the driving transistor and the pulse generating circuit, the structure is simple and the operation is reliable. No power loss.

Further, since the duty cycle of the cutoff pulse is changed by the speed setting means, the speed control of the DC motor can be reliably performed with a simple configuration.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of a DC motor driving circuit according to the present invention.

FIG. 2 is a time chart showing voltage waveforms of main parts of the DC motor drive circuit of FIG.

FIG. 3 is a circuit diagram showing a DC motor driving circuit proposed earlier.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 DC motor 2 Field effect transistor (FET) 3 Voltage comparator 7 Voltage comparator 8 Voltage comparator 11 Pulse formation circuit 12 Saw wave formation circuit VR ₁ Variable resistor (adjustment means of set voltage and cut-off pulse period) VR ₂ variable Resistor (speed setting means)

Claims (1)

(57) [Claims] 1. A voltage comparator for comparing an induced electromotive force generated at a terminal of a DC motor with a preset voltage, and turned on in response to an output signal of the voltage comparator to supply a drive voltage to the DC motor. A drive transistor to be applied; a pulse generating circuit for generating a cutoff pulse for periodically turning off the drive transistor instantaneously; and a speed setting means for changing a duty cycle of the cutoff pulse. DC motor drive circuit.