JPH05343874A - Heat dissipation structure of hybrid ic - Google Patents

Heat dissipation structure of hybrid ic

Info

Publication number
JPH05343874A
JPH05343874A JP4151964A JP15196492A JPH05343874A JP H05343874 A JPH05343874 A JP H05343874A JP 4151964 A JP4151964 A JP 4151964A JP 15196492 A JP15196492 A JP 15196492A JP H05343874 A JPH05343874 A JP H05343874A
Authority
JP
Japan
Prior art keywords
circuit board
heat dissipation
board
printing
conductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP4151964A
Other languages
Japanese (ja)
Inventor
Koji Kitamura
弘司 北村
Shinichiro Inui
信一郎 乾
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Materials Corp
Original Assignee
Mitsubishi Materials Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Materials Corp filed Critical Mitsubishi Materials Corp
Priority to JP4151964A priority Critical patent/JPH05343874A/en
Publication of JPH05343874A publication Critical patent/JPH05343874A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/05—Insulated conductive substrates, e.g. insulated metal substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components

Landscapes

  • Cooling Or The Like Of Electrical Apparatus (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PURPOSE:To use the rear of a circuit board as a wiring region by a method wherein an insulating glass is formed on wiring patterns excluding a heat dissipation part on the rear of the board. CONSTITUTION:Through holes are processed in an alumina board and thereafter, a through-hole printing and a printing of wiring patterns 3 on a board surface 1a are performed. After these patterns are dried, a printing of wiring patterns 3' and a printing of a cementing conductor 4 are performed on the rear 1b of the circuit board and the patterns 3' and the conductor 4 are dried and are subjected to firing. Then, a printing, drying and a firing of an insulating glass are repeated three times on a wiring region 5 formed on the circuit board rear 1b. Then, a resistor paste 6 is printed on the circuit board surface, is dried and is subjected to firing. After a laser trimming is performed, a creamy solder printing is performed on the conductor 4 on the circuit board rear 1b and a reflow is performed. Then, a preform solder is put on a copper heat dissipation board plated with nickel along the exposed conductor 4 on the circuit board rear, the heat dissipation board is aligned with the circuit board and the board 1 and the heat dissipation board are joined to each other by performing a reflow.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は、特に放熱性が要求され
るために放熱板を接合してなるハイブリッドＩＣの放熱
構造に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a heat dissipation structure for a hybrid IC in which heat dissipation plates are joined because heat dissipation is required.

【０００２】[0002]

【従来の技術】従来、高い放熱性が要求されるハイブリ
ッドＩＣにおいては、電気絶縁性と放熱性を両立させる
ために、アルミナ、ベリリア、窒化アルミニウム等のセ
ラミック基板が使用されてきた。通常、これらの回路基
板では、その片面に厚膜材料等を用いた回路が形成さ
れ、回路が形成された裏面には導体が全面印刷され、セ
ラミックス金属等からなる放熱板がはんだ等で接合され
る。2. Description of the Related Art Conventionally, in a hybrid IC requiring high heat dissipation, a ceramic substrate of alumina, beryllia, aluminum nitride or the like has been used in order to achieve both electric insulation and heat dissipation. Usually, in these circuit boards, a circuit using a thick film material or the like is formed on one surface of the circuit board, a conductor is entirely printed on the back surface on which the circuit is formed, and a heat dissipation plate made of ceramic metal or the like is joined by soldering or the like. It

【０００３】[0003]

【発明が解決しようとする課題】これらの高放熱性ハイ
ブリッドＩＣにおいては、発熱源は、主に回路基板上に
実装されたベアチップであり、ベアチップ−回路基板−
放熱板という伝熱経路は回路基板面全体の一部分であ
り、放熱に関与しない回路基板裏面までも放熱板に接合
することによって、本来配線領域として使用可能な回路
基板裏面を使用することができず、配線可能な領域が制
限されるという問題点があった。In these high heat dissipation hybrid ICs, the heat source is a bare chip mainly mounted on a circuit board, and the bare chip--circuit board--
The heat transfer path called the heat sink is a part of the entire surface of the circuit board, and even the back surface of the circuit board, which is not involved in heat dissipation, is joined to the heat sink, so that the back surface of the circuit board that can be used as the original wiring area cannot be used. However, there is a problem that the area where wiring is possible is limited.

【０００４】本発明は、上記問題点に鑑み、回路基板裏
面のなかで、放熱に関与しない部分を配線領域として積
極的に使用することのできるハイブリッドＩＣの放熱構
造を提供することを目的とする。In view of the above problems, it is an object of the present invention to provide a heat dissipation structure for a hybrid IC in which a portion of the back surface of the circuit board that does not contribute to heat dissipation can be positively used as a wiring area. ..

【０００５】[0005]

【課題を解決するための手段】上記目的を達成する本発
明のハイブリッドＩＣの放熱構造は、回路基板と、該回
路基板の表面に形成された第１配線パターンと、該回路
基板の表面に実装された回路部品と、該回路基板の裏面
の、発熱性の前記回路部品から離れた位置に形成された
第２の配線パターンと、該回路基板の裏面の伝熱経路に
形成された導体と、該第２配線パターン上に形成された
絶縁ガラスと、前記導体および前記絶縁ガラスを挟んで
前記回路基板の裏面に接合された放熱板とを備えたこと
を特徴とするものである。A heat dissipation structure for a hybrid IC according to the present invention, which achieves the above object, is a circuit board, a first wiring pattern formed on the surface of the circuit board, and mounted on the surface of the circuit board. A printed circuit part, a second wiring pattern formed on the back surface of the circuit board at a position distant from the heat-generating circuit part, and a conductor formed on the heat transfer path on the back surface of the circuit board, An insulating glass formed on the second wiring pattern and a heat radiating plate bonded to the back surface of the circuit board with the conductor and the insulating glass sandwiched therebetween are provided.

【０００６】ここで、回路基板表裏間の配線は、通常の
セラミックス配線板等で使用されているのと同様に、ス
ルーホールにより導通をとることにより行われる。Here, the wiring between the front and back of the circuit board is carried out by conducting through a through hole as in the case of being used in a usual ceramic wiring board or the like.

【０００７】[0007]

【作用】本発明においては、基板裏面の放熱部を除く配
線パターン上に絶縁ガラスを形成したことが、回路基板
裏面に形成された配線パターンと放熱板との干渉を避け
るという作用を有し、これにより、回路基板裏面を配線
領域とすることが可能となる。In the present invention, forming the insulating glass on the wiring pattern on the back surface of the substrate except for the heat radiation portion has the function of avoiding interference between the wiring pattern formed on the back surface of the circuit board and the heat radiation plate. As a result, the back surface of the circuit board can be used as the wiring area.

【０００８】回路基板表裏への配線パターン形成は通常
のセラミックス回路基板等に使用されているスルーホー
ル印刷、等の厚膜形成技術が使用可能である。また、発
熱源から放熱板に至る放熱経路については、絶縁ガラス
を形成せず、従来同様の構造となるため、本発明の放熱
構造を採用することによる放熱特性の劣化はない。For forming a wiring pattern on the front and back of the circuit board, a thick film forming technique such as through-hole printing which is used for ordinary ceramics circuit boards can be used. Further, the heat dissipation path from the heat source to the heat dissipation plate has the same structure as the conventional one without forming the insulating glass, and therefore the heat dissipation characteristics of the present invention are not deteriorated.

【０００９】[0009]

【実施例】以下、図面を参照して本発明の実施例につい
て説明する。厚み０．８ｍｍのアルミナ基板１にレーザ
加工により直径０．８ｍｍのスルーホール２を加工した
後（図１）、デュポン社の６５０２ペーストを使用し
て、スルーホール２の内壁をメタライズするためのスル
ーホール印刷と基板表面１ａの配線パターン３の印刷を
行った（図２）。１５０℃で１０分間乾燥した後に、回
路基板１の裏面１ｂに配線パターン３の印刷と接合導体
４の印刷を行い、同様にして乾燥した（図３）。回路基
板裏面１ｂの配線パターン３’（図３参照）は、後に回
路基板表面１ａのベアチップ実装領域３ａ（図２参照）
に実装される放熱源のベアチップ７（図６参照）から発
生する熱の放熱板への伝熱経路を避けて形成されてい
る。伝熱経路となる基板裏面の中央部分および放熱板と
の接合に供される周辺部分には導体４を全面印刷した
（図３）。基板表裏の配線パターンを印刷した後、８５
０℃、１０分キープ、トータル１時間の焼成プロファイ
ルで焼成した。Embodiments of the present invention will be described below with reference to the drawings. After processing the through hole 2 having a diameter of 0.8 mm by laser processing on the alumina substrate 1 having a thickness of 0.8 mm (FIG. 1), a through hole for metallizing the inner wall of the through hole 2 by using 6502 paste manufactured by DuPont. The hole printing and the wiring pattern 3 on the substrate surface 1a were printed (FIG. 2). After drying at 150 ° C. for 10 minutes, the wiring pattern 3 and the bonding conductor 4 were printed on the back surface 1b of the circuit board 1 and similarly dried (FIG. 3). The wiring pattern 3 '(see FIG. 3) on the back surface 1b of the circuit board will be later mounted on the bare chip mounting area 3a on the front surface 1a of the circuit board (see FIG. 2).
Is formed so as to avoid the heat transfer path to the heat radiating plate for the heat generated from the bare chip 7 (see FIG. 6) of the heat radiating source mounted in. The conductor 4 was printed on the entire surface in the central portion of the back surface of the substrate, which serves as a heat transfer path, and in the peripheral portion used for joining with the heat dissipation plate (FIG. 3). After printing the wiring pattern on the front and back of the board, 85
Firing was carried out with a firing profile of 0 ° C., 10 minutes keep, total 1 hour.

【００１０】次に、回路基板裏面１ｂに形成した配線領
域５（図３参照）に、デュポン社製５７０４ペーストを
使用して絶縁ガラスの印刷・乾燥・焼成を３回繰り返し
た。乾燥は１５０℃、１０分、焼成は８５０℃、キープ
１０分、トータル１時間とし、絶縁ガラスの膜厚みを５
０〜６０μｍとした。このように加工することによって
放熱板１０（図５参照）と回路基板１を接合した際に、
裏面回路と放熱板とが直接接触し電気的に導通してしま
うことを避けることができた。Next, in the wiring region 5 (see FIG. 3) formed on the back surface 1b of the circuit board, printing, drying and baking of insulating glass were repeated three times using 5704 paste manufactured by DuPont. Drying at 150 ° C. for 10 minutes, baking at 850 ° C., keeping for 10 minutes, totaling 1 hour, and insulating glass film thickness of 5
It was set to 0 to 60 μm. By processing in this way, when the heat sink 10 (see FIG. 5) and the circuit board 1 are joined,
It was possible to avoid direct contact between the backside circuit and the heat sink and electrical conduction.

【００１１】次に、導体の場合と同様に回路基板表面に
抵抗体ペースト６を印刷・乾燥・焼成した（図４）。抵
抗体ペーストにはデュポン社の６８００シリーズを使用
した。抵抗体焼成後に抵抗値を±５％以内にするため
に、レーザートリミングを行った（図６の抵抗体パター
ン６参照）。レーザートリミング後は、回路基板裏面１
ｂの導体４にクリームはんだ印刷を行い、リフローし
た。基板裏面の放熱部の導体４と絶縁ガラス形成部５と
の膜厚差は、クリームはんだ印刷により補正した。Next, as in the case of the conductor, the resistor paste 6 was printed, dried and fired on the surface of the circuit board (FIG. 4). As the resistor paste, 6800 series manufactured by DuPont was used. After the resistor was fired, laser trimming was performed to make the resistance value within ± 5% (see resistor pattern 6 in FIG. 6). After laser trimming, the back side 1 of the circuit board
The conductor 4 of b was subjected to cream solder printing and reflowed. The film thickness difference between the conductor 4 of the heat radiation portion on the back surface of the substrate and the insulating glass forming portion 5 was corrected by cream solder printing.

【００１２】次に、回路基板裏面の露出する導体４に沿
って、ニッケルメッキされた厚み４ｍｍの銅製放熱基板
１０上にプリフォームはんだ１２を置き（図５）、上記
回路基板と位置合わせし、リフローすることによって回
路基板１と放熱板１０を接合した。以上述べたはんだ及
びクリームはんだには融点が２８５℃のものを使用し
た。Next, along the exposed conductors 4 on the back surface of the circuit board, preform solder 12 is placed on the nickel-plated copper heat dissipation board 10 having a thickness of 4 mm (FIG. 5) and aligned with the circuit board. The circuit board 1 and the heat sink 10 were joined by reflowing. The solder and cream solder described above had a melting point of 285 ° C.

【００１３】放熱板１０を実装した後は、回路基板表面
１ａに、融点１８３℃のクリームはんだを印刷し、ベア
チップ７およびリード端子８を実装し、ワイヤーボンデ
ィングを行った（図６）。このように、回路基板裏面の
一部を配線領域として使用することによって、放熱特性
を犠牲にすることなく、回路基板サイズを小型化するこ
とが可能となった。After mounting the heat sink 10, cream solder having a melting point of 183 ° C. was printed on the surface 1a of the circuit board, the bare chip 7 and the lead terminals 8 were mounted, and wire bonding was performed (FIG. 6). As described above, by using a part of the back surface of the circuit board as the wiring region, it is possible to reduce the size of the circuit board without sacrificing the heat dissipation characteristics.

【００１４】なお、回路基板としては、アルミナのほ
か、ＡｌＮ、ＢｅＯ、ＳｉＣも使用可能である。In addition to alumina, AlN, BeO, or SiC can be used as the circuit board.

【００１５】[0015]

【発明の効果】本発明により、従来回路基板裏面に配線
を形成することができなかった放熱板を有する回路基板
において、放熱に関与しない部分の回路基板裏面の配線
領域としての使用が可能となり、従来不可能であった高
密度配線が可能となった。As described above, according to the present invention, in a circuit board having a heat radiating plate in which wiring cannot be formed on the back surface of the circuit board in the related art, it can be used as a wiring area on the back surface of the circuit board which is not involved in heat dissipation High-density wiring, which was previously impossible, is now possible.

【図面の簡単な説明】[Brief description of drawings]

【図１】スルーホールが加工されたアルミナ基板を表わ
した図である。FIG. 1 is a view showing an alumina substrate having a through hole processed.

【図２】スルーホール印刷および配線パターンの印刷を
行った後のアルミナ基板表面を表わした図である。FIG. 2 is a diagram showing the surface of an alumina substrate after through-hole printing and wiring pattern printing.

【図３】配線パターンおよび接合用導体の印刷を行った
後のアルミナ基板裏面を表わした図である。FIG. 3 is a diagram showing the back surface of an alumina substrate after printing a wiring pattern and a bonding conductor.

【図４】抵抗体の印刷を行った後のアルミナ基板表面を
表わした図である。FIG. 4 is a diagram showing the surface of an alumina substrate after printing a resistor.

【図５】プリフォームはんだをおいた状態の放熱板を表
わした図である。FIG. 5 is a diagram showing a heat radiating plate with preform solder placed thereon.

【図６】ベアチップおよびリード端子を実装し、ワイヤ
ボンディングを行った後のアルミナ基板表面の図であ
る。FIG. 6 is a view of the surface of an alumina substrate after mounting a bare chip and lead terminals and performing wire bonding.

【符号の説明】[Explanation of symbols]

１ アルミナ基板 ２ スルーホール ３，３’ 配線パターン ３ａ ベアチップ実装領域 ４ 接合用導体 ５ 基板裏面配線領域 ６ 抵抗体 ７ ベアチップ ８ リード端子 １０ 放熱板 １２ プリフォームはんだ DESCRIPTION OF SYMBOLS 1 Alumina substrate 2 Through hole 3,3 'Wiring pattern 3a Bare chip mounting area 4 Bonding conductor 5 Substrate backside wiring area 6 Resistor 7 Bare chip 8 Lead terminal 10 Heat sink 12 Preform solder

Claims (1)

【特許請求の範囲】[Claims] 【請求項１】 回路基板と、該回路基板の表面に形成さ
れた第１配線パターンと、該回路基板の表面に実装され
た回路部品と、該回路基板の裏面の、発熱性の前記回路
部品から離れた位置に形成された第２の配線パターン
と、該回路基板の裏面の伝熱経路に形成された導体と、
該第２配線パターン上に形成された絶縁ガラスと、前記
導体および前記絶縁ガラスを挟んで前記回路基板の裏面
に接合された放熱板とを備えたことを特徴とするハイブ
リッドＩＣの放熱構造。1. A circuit board, a first wiring pattern formed on the front surface of the circuit board, a circuit component mounted on the front surface of the circuit board, and the heat-generating circuit component on the back surface of the circuit board. A second wiring pattern formed at a position distant from the conductor, a conductor formed in a heat transfer path on the back surface of the circuit board,
A heat dissipation structure for a hybrid IC, comprising: an insulating glass formed on the second wiring pattern; and a heat dissipation plate joined to the back surface of the circuit board with the conductor and the insulating glass sandwiched therebetween.
JP4151964A 1992-06-11 1992-06-11 Heat dissipation structure of hybrid ic Withdrawn JPH05343874A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4151964A JPH05343874A (en) 1992-06-11 1992-06-11 Heat dissipation structure of hybrid ic

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4151964A JPH05343874A (en) 1992-06-11 1992-06-11 Heat dissipation structure of hybrid ic

Publications (1)

Publication Number Publication Date
JPH05343874A true JPH05343874A (en) 1993-12-24

Family

ID=15530065

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4151964A Withdrawn JPH05343874A (en) 1992-06-11 1992-06-11 Heat dissipation structure of hybrid ic

Country Status (1)

Country Link
JP (1) JPH05343874A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2734981A1 (en) * 1995-05-30 1996-12-06 Siemens Ag Double sided pcb for electronic controls in automotive applications

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2734981A1 (en) * 1995-05-30 1996-12-06 Siemens Ag Double sided pcb for electronic controls in automotive applications

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Effective date: 19990831