JPH05343688A - Manufacture of metal gate field-effect semiconductor device - Google Patents

Abstract

PURPOSE:To facilitate an etching of a part of a wiring not required by a method wherein a plurality of wiring patterns of a narrow line width are formed on a part where wire cutting is required and after these patterns are anodized, they are etched to cut the part of the wiring required for cutting. CONSTITUTION:A wiring 2 is a branch line of a wiring 1. Here, it is required to ensure a required sectional area of the wiring 2 at an etching place B. As a current, which is made to flow through wirings (gate wirings) 4 of the terminals of the wiring 2, is small, a sufficient sectional area of the wiring 2 can be ensured by merely making thin the wiring 2 at an etching place C. Moreover, it is desirable that the line width of a part to be etched of the wiring 2 is uniform as much as possible because the part to be etched can be etched evenly. Desirably, an irregularity in the line width W of the wiring 2 is limited within a width two times the width. In such a way, a plurality of wiring patterns of a narrow line width are formed on a part of the wiring 2 required for cutting and after these patterns are anodized, they are etched, whereby the part required for cutting, is cut. Thereby, an etching of a part of the wiring not required, can be easily conducted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film transistor which is suitable for forming over a large area and has excellent reliability and mass productivity. As an industrial application field of the present invention, if the present invention is applied to a thin film transistor formed on a transparent substrate, a drive circuit of an electro-optical device such as a liquid crystal display device or an image sensor will be manufactured. Further, when applied to a thin film transistor formed on a single crystal semiconductor substrate, it can be used for an integrated circuit such as a memory or a logic.

[0002]

2. Description of the Related Art In recent years, a technique for forming a semiconductor region on an insulating substrate such as a glass substrate to form a transistor or an integrated circuit has been researched and developed, and partially put to practical use. In particular, such a transistor on an insulating substrate is called a thin film transistor (TFT), and its technology is urgently established for driving a liquid crystal display device, an image sensor, and the like.

Further, similarly to the conventional semiconductor integrated circuit, a three-dimensional integrated circuit technology in which a semiconductor circuit is further formed by a thin film transistor or the like on a semiconductor circuit formed on a single crystal semiconductor substrate via an insulating layer, In recent years, it has come into practical use.

Conventionally, as a semiconductor material for such a transistor, polycrystalline silicon obtained by high temperature recrystallization or
Although amorphous silicon produced by vapor phase synthesis was used, the former requires a high temperature of nearly 1000 ° C. for its production, so the substrate is limited to expensive quartz, and the latter has a low electric field mobility. It could not be used for a large amount of information. Further, when a TFT is further formed on the semiconductor substrate, the high temperature treatment has no problem, but the mobility of the obtained polycrystalline semiconductor is low. Specifically, N
Type silicon was 10 to 50 cm / Vs. this is,
It is considered that many defects such as trap levels are generated in the process of recrystallization.

Under such circumstances, in recent years, a technique for crystallizing silicon by thermal annealing at about 600 ° C. (low temperature annealing) or annealing method using laser light (laser annealing) has been developed. By these methods, the selection range of the substrate material is expanded, and cost reduction can be expected. Above all, laser annealing has been attracting attention as a technique having excellent mass productivity. Furthermore, in these methods, it is possible to form the source and drain by ion implantation or laser doping method in a self-aligned manner with the device being a planar type, and in that case, it is also effective to reduce the parasitic capacitance.
Also, regarding the electric field mobility, it is 50 cm for N type silicon.
The characteristics above / Vs can be obtained with good reproducibility.
Particularly, laser annealing can obtain characteristics of 200 cm / Vs or more.

Based on such a background, laser annealing has been actively studied. If the laser annealing is more advantageous than the low temperature annealing, (1) a low resistance metal gate can be used. (2) Electric field mobility is large. It converges to two points. Particularly, (1) is advantageous in a large-area circuit (liquid crystal display, etc.), and (2) is advantageous in manufacturing a three-dimensional integrated circuit.

However, for example, when the laser annealing method is used in an aluminum gate TFT, it is remarkable when the purity of aluminum is low or when the grain size is large, but laser irradiation is performed with aluminum exposed. Then, the aluminum immediately expanded or melted, and the aluminum gate electrode / wiring was peeled off, scattered, or deformed. In particular, when the scale of the device becomes small and pure aluminum is affected by electromigration, etc., use an alloy with a small amount of silicon mixed in aluminum, but in that case the reflection of laser light is not sufficient. , It is easy to cause the above troubles.

This is not limited to aluminum, and the same thing can occur with metal materials such as titanium, tantalum, and chromium, and with semiconductor materials such as silicon and germanium. This is because some of these materials have a very high melting point compared to aluminium, so they rarely melt, but the reflection is not sufficient and the laser absorbs heat when it expands. This is because the temperature is significantly different from the non-irradiated portion and the thermal expansion coefficient is different, so that the coating film is easily peeled off.

As a method for solving such a problem,
The present inventors have proposed a method of covering the periphery of a metal gate wiring with an anodic oxide film (Japanese Patent Application No. 3-237100). According to this method, since the anodic oxide film has a low degree of absorbing laser light, peeling of the gate electrode was avoided.

Further, in the above-mentioned invention, by using the anodic oxide film as a mask, an arbitrary interval (offset region) is provided between the gate electrode and the source / drain regions to obtain a T-characteristic having a better characteristic.
I was able to obtain FT. Further, it was expected that defects such as short circuits in multilayer wiring could be prevented by using the anodic oxide film as a dense insulating film.

When a TFT is formed in this manner, it is usually necessary to perform anodic oxidation with all gate electrodes / wirings connected to one circuit. However, the formed gate electrode and wiring need to be electrically separated depending on the purpose. However, it is very difficult to perform the same etching on a composite of a metal (or semiconductor) and its anodic oxide, and in some cases, a thin film above and below it. For example,
Oxides and metals (or semiconductors) have different etching rates in commonly used wet etching and reactive etching.

According to the observation of the inventors of the present invention, although the reason is not clear, it took a long time to etch the wiring portion having a large line width. When the thick wiring was etched, the thin portion was over-etched. However, it was practically impossible to unify all wirings to the minimum line width. When designed in this way, the voltage during anodic oxidation decreases toward the tip,
This is because the anodization could not be performed uniformly.

[0013]

The present invention provides a technique for solving the problems associated with such anodization, and at the same time, an overall process most suitable for manufacturing a TFT by the anodization method. Is proposed.

[0014]

In the present invention, the wiring for anodic oxidation is arranged so that it becomes thicker as it gets closer to the power source (electrode). However, at this time, it is very difficult to etch thick wiring. In view of this, in the present invention, a plurality of wirings having a narrow line width are gathered in a portion requiring etching to secure a cross-sectional area that does not substantially cause a voltage drop. An example thereof is shown in FIG.

In the figure, for example, portions A, B and C are portions to be etched. These portions are composed of one or a plurality of wires having the minimum line width W. The wiring 1 is the wiring (main line) closest to the anodizing power supply. The current flowing through this wiring is proportional to the area of the wiring from that point. Fine wiring is required for etching,
If there is not a sufficient wire breakage product, a significant voltage drop will occur and the anodization of the tip will be insufficient.

Although the voltage drop will be sufficiently low if the line is thinned only in the portion to be etched to the minimum, it is desirable that such a thick line does not exist in the subsequent circuit arrangement because it reduces the parasitic capacitance. Etching is desired. Therefore, for etching, it is necessary to secure a sufficient cross-sectional area by combining a number of thin wirings as shown by A in the figure.

The wiring 2 is a branch line of the wiring 1. Here again, it is required to secure the necessary cross-sectional area at the etching location (B). The wiring 4 is a terminal wiring (gate wiring). Since the current flowing through this wiring is small, it is possible to secure a sufficient cross-sectional area at the portion to be etched only by thinning the line as indicated by C in the figure. It is desirable that the line width of the portion to be etched is as uniform as possible so that the line can be uniformly etched. Preferably, the variation of the line width W of the wiring is within 2 times (the maximum one is twice the minimum one). It means the following). In addition, a portion 3 having a large line width is provided in a part of the wiring 2 or 4 in the drawing, and this serves as a pad for making contact with the gate electrode. Area 5 is an activation area. With such wiring, all parts are connected to the power supply,
Moreover, since the anodic oxidation is performed with almost no voltage drop, the thickness of the anodic oxide is almost the same in almost all places.

FIG. 1 (B) shows that such a circuit is wired so as to be a target circuit. That is, FIG.
In (A), the portions indicated by A, B, and C are etched and the gate wiring is divided. Then, a contact hole is provided in the pad 3 of the gate wiring and the semiconductor region 5, and the upper wiring 6 connects them to each other. It should be noted that the upper wiring 6 is formed on each of the etched portions of the wiring 1. If the wiring 1 remains under the upper wiring 6, a parasitic capacitance is generated, which causes a circuit loss and a signal delay. It is impossible to eliminate such wiring intersections at all locations, but it is possible to reduce them sufficiently.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 2 is a schematic view for explaining the process of the present invention.
Shows a conceptual view of a cross section that was not well understood. The state of the circuit viewed from the top is the same as that shown in FIG. First, Corning 7059 glass was used as the substrate 201. Then, an amorphous silicon film was formed to a thickness of 150 nm by the plasma CVD method. This is 6
It was recrystallized by annealing in a nitrogen atmosphere at 00 ° C. for 60 hours. Further, this was patterned to form island-shaped semiconductor regions 202 and 203. Here, the semiconductor region 202 is a region to be a P-channel TFT later, and the semiconductor region 203 is a region to be an N-channel TFT.

Further, the gate oxide film 204 is formed by a sputtering method in an oxygen atmosphere targeting silicon oxide.
To a thickness of 115 nm, and then an aluminum film is formed by electron beam evaporation, and this is patterned to form a gate electrode 206 for the P-channel TFT, a gate electrode 207 for the N-channel TFT, and wirings 205 and 208.
Formed. In this way, the outer shape of the TFT was adjusted.
The channel size at this time is 2 μm in length and 2 in width.
It was set to 0 μm. Also, for patterning this wiring, 5w
A mixture of t% nitric acid and phosphoric acid was used. For example, when the etching temperature was 40 ° C., it was 225 nm / min. Further, all the gate electrodes / wirings are electrically connected. The state of the circuit obtained so far is shown in FIG.
Shown in.

Further, electricity is supplied to these wirings / electrodes, and an aluminum oxide film is formed around the electrodes / wirings (upper surface and side surfaces) by the anodic oxidation method. The anodization was performed using a solution in which a 3% ethylene glycol solution of tartaric acid was neutralized with 5% ammonia to a pH of 7.0 ± 0.2. First, platinum was immersed in the solution as a cathode, and further the TFT was immersed together with the substrate to connect one end of the wiring to the anode of the power supply. The temperature was kept at 25 ± 2 ° C.

In this state, a current of 0.5 mA / cm ² is first applied, and when the voltage reaches 250 V, the current is supplied with the voltage kept constant, and the current is reached when the current reaches 0.005 mA / cm ^2. Was stopped and the anodization was completed. The thickness of the anodized film thus obtained was 250 nm. Thus, the aluminum oxide film 209 is formed around the gate electrodes / wirings 205 to 208 (upper surface and side surface).
~ 212 was formed. The state of the circuit obtained thus far is shown in FIG.

Next, with the photoresist 213 covering the semiconductor region 203, a P-type impurity region (source, drain) 21 is formed in the semiconductor region 202 by an ion implantation method.
4 and 215 were formed. Boron trifluoride or boroso is used as the dopant, and the ion energy is 7
The dose was 0 to 100 keV and the dose was 1 to 5 × 10 ¹³ cm ^-2 . As a result of this ion implantation, the source and drain regions of the semiconductor region 202 have a thickness (about 25 mm) of aluminum oxide in a portion (offset region) that does not cover the gate electrode.
It is estimated that only 0 nm) was formed. The state of the circuit thus obtained is shown in FIG.

Similarly, with the semiconductor region 202 covered with the photoresist 216, the semiconductor region 20 is also removed.
3, N type impurity regions 217 and 218 were formed.
Phosphorus was used as a dopant. The dose amount and the acceleration energy were set to the same conditions as the P-type impurity doping.
The state of the circuit obtained thus far is shown in FIG.

Then, laser annealing was performed.
The laser used is a KrF excimer laser, for example, 3
50 laser pulses with a power density of 50 mJ / cm ²
Shot irradiation. The laser annealing was performed by fixing the sample on an XY stage and irradiating it in the air while moving a laser beam having a size of 1 × 300 mm ² . Next, an interlayer insulator 219 is formed by sputter deposition of silicon oxide.
Then, an electrode hole, for example, 220 was formed by a known photolithography technique to expose the surface of the semiconductor region or the gate electrode / wiring.

At this time, it is desired that the etching selectively removes only the silicon oxide that is the interlayer insulator and the aluminum oxide that covers the gate electrode / wiring. All etch rates are required to be higher for aluminum and silicon. According to the knowledge of the present inventor, a suitable etching ratio was obtained with so-called buffer hydrofluoric acid (solution in which hydrogen fluoride and ammonium fluoride are mixed). For example, high-purity hydrofluoric acid (5
0 wt%) and the same ammonium fluoride solution (40 wt%) mixed at a ratio of 1:10, the etching rate of aluminum oxide is 60 nm / min, whereas aluminum is 15 nm / min. It is suitable for this purpose. In this way, etching was performed. Then, with respect to the portion where the wiring needs to be cut, aluminum was further dissolved by phosphoric acid to complete the cutting. That is, the contact hole was formed and the wiring was cut through the above steps.

In reactive ion etching using carbon tetrafluoride, silicon oxide is etched, but aluminum oxide and aluminum are hardly etched. By utilizing this characteristic, it is possible to adopt a method of etching only silicon oxide in the vicinity of the contact of the wiring, and then etching only aluminum oxide around the wiring with buffer hydrofluoric acid. The condition of the reactive ion etching at this time is that the gas flow rate is 20 sccc.
m, pressure 0.08 torr, and RF power 100 W. The etching rate of silicon oxide was 10 nm / min.

After forming the contact holes in this way, upper metal wirings 221 to 223 were formed of aluminum. A state in which the wiring is formed in this manner is shown in FIG.

[0029]

According to the present invention, a TFT having a uniform thickness of anodic oxide in the substrate and a uniform degree of etching was produced. Such a TFT is superior to the conventional one in reliability and mass productivity. Thus, the present inventor believes that the present invention is industrially beneficial.

[Brief description of drawings]

FIG. 1 shows an example (top view) of a manufacturing process of a TFT according to the present invention.

FIG. 2 shows an example (cross-sectional view) of a manufacturing process of a TFT according to the present invention.

[Explanation of symbols]

 1 ... Wiring (main line) 2 ... Wiring (branch line) 3 ... Gate electrode pad 4 ... Wiring (gate wiring) 5 ... Semiconductor area 6 ... Upper wiring

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H01L 27/12 Z

Claims (2)

[Claims] 1. A step of forming a wiring having a portion composed of a plurality of thin lines on a substrate; a step of passing an electric current through the wiring to form an oxide of the wiring on a surface and a side surface of the wiring; And a step of etching a portion formed of a line, a method of manufacturing a metal gate field effect semiconductor device. 2. The method for manufacturing a metal gate field effect semiconductor device according to claim 1, wherein the gate electrode contains aluminum as a main component.