JP3071939B2 - Method for manufacturing insulated gate semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulating gate type semiconductor device, and more particularly to a structure of a thin film insulating gate type field effect transistor (TFT) and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, a thin film insulated gate field effect transistor (TFT) has been actively studied. For example,
Japanese Patent Application Nos. Hei 3-237100 and No. 3 which are inventions of the present inventors.
No. 238713 discloses a fabrication method in which aluminum is used as a gate electrode, its periphery is covered with aluminum oxide formed by anodization, and the source / drain regions are recrystallized by laser annealing.
T is described.

[0003] Such a TFT exhibited superior characteristics as compared with a conventional silicon gate TFT and a TFT using a high melting point metal such as tantalum or chromium as a gate electrode. However, it has been difficult to obtain the characteristics with good reproducibility.

[0004] One of the causes was due to intrusion of mobile ions such as sodium from the outside. In particular, during the formation of an aluminum gate electrode (a sputtering method or an electron beam evaporation method is used) and the subsequent anodic oxidation, there is a risk that sodium may enter from the outside. Especially in the sputtering method,
Sodium contamination was great. However, since the sputtering method is more excellent in mass productivity than the electron beam evaporation method, it has been desired to use the sputtering method for cost reduction.

[0005] It has been known that sodium is blocked and gettered by phosphorus glass or the like. Therefore, the gate insulating film is generally formed of phosphorus glass. However,
It has been difficult to produce phosphorus glass at the low temperature intended for the above patent. If phosphorus glass is to be produced at such a low temperature, many defects are generated in the gate insulating film when the gate insulating film is implanted into a silicon oxide gate insulating film by, for example, an ion doping method. There were times when it was done.

In the above patent, aluminum oxide is formed around the gate wiring. This has the function of improving the insulating property with respect to the wiring layer thereon and protecting the gate electrode during laser annealing, but it is extremely difficult to form a contact hole therethrough. That is, when aluminum oxide is etched by a wet etching method having good mass productivity, the etchant also etches silicon oxide used as an interlayer insulator, and silicon oxide has a higher etching rate. . For this reason, a gas phase etching method has to be used, such as a reactive ion etching method.

Further, anodic oxidation requires a high voltage of 100 to 300 V, and there is a concern that the gate insulating film may be destroyed.
That is, in the technical range shown in the above patent, a gate insulating film is formed on a semiconductor film, and a gate electrode is present thereon, but at the time of anodic oxidation, the gate electrode is in a floating state with a positively charged gate electrode. A voltage is generated between the semiconductor films,
As the anodic oxide film on the gate electrode becomes thicker and the resistance between the gate electrode and the electrolytic solution increases, the current flowing from the gate electrode to the electrolytic solution via the gate insulating film and the semiconductor film increases. Then, the gate electrode may be destroyed by this current.

[0008]

SUMMARY OF THE INVENTION The present invention has been made in view of such circumstances. That is, the present invention provides a structure and a manufacturing method of a TFT which prevents intrusion of mobile ions from the outside and facilitates formation of a contact with an aluminum wiring covered with an anodic oxide film. Another object is to prevent the gate insulating film from being broken and to improve reliability.

[0009]

According to one aspect of the present invention, a silicon nitride film is interposed between an aluminum gate electrode and a gate insulating film. Assuming that the composition of silicon nitride is 1, the ratio of nitrogen is preferably 1 to 4/3, more preferably 1.2 to 4/3. Of course, hydrogen or oxygen other than nitrogen and silicon may be added.

Since the silicon nitride film has an effect of blocking mobile ions such as sodium, the silicon nitride film not only has an effect of preventing mobile ions from entering the channel region from a gate electrode or the like, but also has an effect of preventing a normal gate insulating film. Also, it has a feature that since the conductivity is better than that of silicon oxide, an excessive voltage is not applied between the gate electrode and the semiconductor region (channel region) therebelow, so that the gate insulating film can be prevented from being broken. .

Therefore, a semiconductor region and a gate insulating film are formed, thereafter, the silicon nitride film is formed, and thereafter, an aluminum electrode for forming a gate electrode is formed. During the anodization of the aluminum electrode, it is desirable that the silicon nitride film be present integrally over the entire surface of the substrate, since the anodic potential is kept substantially constant over the entire surface of the substrate.

Another aspect of the present invention is that a portion of the gate electrode whose surface is to be anodized later and the wiring extending therefrom are formed of a material different from aluminum in a portion where a contact needs to be formed. done,
This is to cover with a material having a masking effect on anodic oxidation. Suitable materials include chromium, gold, titanium, silicon, indium oxide, titanium oxide, indium-titanium oxide, and zinc oxide.

In a portion covered with such a material, during anodic oxidation, either an oxide of these materials is formed on the surface or no new oxide is formed. is there. For example, chromium and titanium are the former, and gold, titanium oxide, indium oxide, and the like are the latter.

If only these materials are selectively etched after anodic oxidation, the surface of the metal aluminum of the gate wiring is exposed. Therefore, it is easy to form a contact hole. The present invention is also advantageous in performing anodic oxidation. That is,
In anodic oxidation, all the gate electrodes and wirings need to be connected and maintained at a positive potential. However, when actually used as a circuit, since all the gate electrodes and wirings do not function if they are integrated, it is necessary to cut off the wiring as necessary and connect the wiring again. This technique is typically described in Japanese Patent Application No. 3-348130, which is an invention of the present inventors.

For this purpose, (1) formation of a gate wiring,
(2) patterning of gate wiring after anodic oxidation, (3)
Three photolithography steps of reconnecting the gate wiring were required. Moreover, in the step (3), as described above, it is difficult to form a contact hole because etching of aluminum oxide is difficult.

However, if the present invention is utilized, (1) formation of a gate wiring, (2) formation of a wiring for anodic oxidation, (3)
Reconnection of the gate wiring can be covered by three photolithography steps. Here, the wiring for anodic oxidation is a wiring only for supplying a current for anodic oxidation to the gate electrode of each TFT, and is formed of the above-mentioned material, and the etching thereof can be selectively performed. So
No photolithography step is required. In addition, since the surface of the gate wiring is exposed after removing the wiring for anodic oxidation, it is easy to form a wiring for connecting the gate wiring thereon. Hereinafter, the present invention will be described in more detail with reference to Examples.

[0017]

【Example】

[Embodiment 1] FIG. 1 is a sectional view showing a manufacturing process of this embodiment. Note that the detailed conditions of this embodiment are almost the same as those of Japanese Patent Application No. 3-237100 filed by the present inventors, and thus will not be described in detail. First, N-0 glass manufactured by NEC Corporation was used as the substrate 101. Although this glass has a high strain temperature, it contains a lot of lithium,
Sodium is also present in significant amounts. Therefore, in order to prevent invasion of these mobile ions from the substrate, the silicon nitride film 102 is formed with a thickness of 10 to 50 nm by a plasma CVD method or a low pressure CVD method. Further, an underlying silicon oxide film 103 was formed by a sputtering method to a thickness of 100 to 800 nm. An amorphous silicon film was formed thereon by plasma CVD to a thickness of 20 to 100 nm, and annealed at 600 ° C. for 12 to 72 hours in a nitrogen atmosphere to crystallize. Further, this is patterned by photolithography and reactive ion etching (RIE) to form island-shaped semiconductor regions 104 (for N-channel TFT) and 105 (for P-channel TFT) as shown in FIG. And formed.

Further, the gate oxide film 106 is formed by sputtering in an oxygen atmosphere using silicon oxide as a target.
Was deposited with a thickness of 50-200 nm. Further, a silicon nitride film 107 was deposited to a thickness of 2 to 20 nm, preferably 8 to 11 nm by a plasma CVD method or a low pressure CVD method.

Next, an aluminum film was formed by a sputtering method or an electron beam evaporation method, and this was patterned by a mixed acid (a phosphoric acid solution to which 5% nitric acid was added) to form gate electrodes / wirings 108 to 111. Thus, the outer shape of the TFT was adjusted. further,
A chromium film having a thickness of 100 to
Only 300 nm was formed and patterned as shown in FIG. 1A to form chromium regions 112 and 113.

Further, in the electrolytic solution, the gate electrode / wiring 1
An electric current was passed through 08 to 111, and aluminum oxide films 114 to 117 were formed by anodic oxidation. At this time, no aluminum oxide was formed on the surface of the portion covered with chromium. As the conditions for the anodic oxidation, the method described in Japanese Patent Application No. 3-237100, which was an invention of the present inventors, was employed. The state so far is shown in FIG.

Next, the chromium regions 112 and 113 are compared, for example.
Chromium etchant such as cerium ammonium nitrate
Etched by, further, to remove the silicon nitride 107 other than those underlying the gate electrode and wiring portions by reactive ion etching. Further, an N-type impurity is implanted into the semiconductor region 104 and a P-type impurity is implanted into the semiconductor region 105 by a known ion implantation method, so that an N-type impurity region (source and drain) 118 and a P-type impurity region 119 are formed. Formed. This process used a known CMOS technology.

Thus, a structure as shown in FIG. 1C was obtained. Naturally, the crystallinity of the portion into which the impurities are implanted is remarkably degraded by such ion implantation, and is substantially in an amorphous state (amorphous state or a polycrystalline state close thereto).
Therefore, the crystallinity was recovered by laser annealing. This step may be performed by thermal annealing at 600 to 850 ° C. The conditions for laser annealing were, for example, those described in Japanese Patent Application No. 3-237100.

Thus, the shape of the element was adjusted. Thereafter, as usual, an interlayer insulator 120 is formed by sputter deposition of silicon oxide, an electrode hole is formed by a known photolithography technique, and the surface of the semiconductor region or the gate electrode / wiring is exposed, Finally, the second
The metal film (aluminum or chromium) was selectively formed and used as electrodes / wirings 121 to 125. Here, the first metal wirings 108 and 111 make contact with the second metal wirings 121 and 125 at points P and Q, respectively.

[Embodiment 2] "The thin-film insulated gate semiconductor device and its manufacturing method", filed on February 25, 1992, by the present inventors (Applicant, Semiconductor Energy Laboratory, Inc. Reference numbers P002042-01 to P0
FIG. 2 shows an example in which the present invention is applied to a TFT having two layers of channels described in 02044-03 (the above three cases).

That is, in FIG. 2, 201 is an N-channel TFT, 202 is a P-channel TFT, and the first layers 208 and 210 in the channel region are substantially made of amorphous silicon. Its thickness is 2
0 to 200 nm.

Reference numerals 207 and 209 denote substantially polycrystalline or semi-amorphous silicon having a thickness of 20 to 200 nm. Further, 204 and 206 are gate insulating films made of silicon oxide and have a thickness of 50 to 3.
00 nm. Reference numerals 203 and 205 denote silicon nitride films having a thickness of 2 to 20 nm formed in the same manner as in the first embodiment. These structures were manufactured based on the description of the above patent application or Example 1.

Embodiment 3 FIG. 3 shows an example in which anodic oxidation and subsequent wiring are performed by utilizing the present invention. First, an island-shaped semiconductor region 30 is formed on a substrate 301 as in the first embodiment.
After forming a plurality of gate electrodes 2 and forming a gate insulating film and, if necessary, a silicon nitride film of the present invention, the gate electrode / wiring 303 was patterned with aluminum. (FIG. 3
(A))

Next, a wiring 304 for anodic oxidation was formed of chromium, and a connection was made between the gate electrode and the wiring. The conditions for the chromium film were the same as in Example 1. (FIG. 3 (B)) Then, under the same conditions as in Example 1, anodization was performed while maintaining the chromium wiring 304 at a positive potential, and an anodized film 305 was formed on the surface of the gate electrode and wiring. (FIG. 3C) Next, the chromium wiring was removed under the same conditions as in Example 1, exposing the surface 306 of the gate wiring. (FIG. 3 (D))

After impurity doping, formation of an interlayer insulator, and formation of a contact hole were performed in the same manner as in Example 1, a second metal wiring 307 was formed of aluminum.
At this time, the gate wiring and the second metal wiring 307 make contact at 308 in FIG. (FIG. 3 (E))

[0030]

As described above, by forming a silicon nitride film between a gate electrode and a gate insulating film, penetration of mobile ions is prevented, and the gate insulating film is destroyed at the time of anodic oxidation of the gate electrode. Could be prevented.

Further, by selectively providing a conductive film serving as a mask for anodic oxidation in close contact with the gate electrode and wiring, performing anodic oxidation, and removing it after completion of anodic oxidation, It was possible to easily form a contact to the gate wiring after oxidation. Also, by applying this technique successfully to anodic oxidation, the subsequent wiring connection process could be simplified.

[Brief description of the drawings]

FIG. 1 is a manufacturing process diagram (cross section) of a semiconductor device according to the present invention.
Is shown.

FIG. 2 shows a structural example of a semiconductor device according to a conventional example.

FIG. 3 is a manufacturing process diagram (plan view) of a semiconductor device according to the present invention.
Is shown.

[Explanation of symbols]

Reference Signs List 101 Insulating substrate 102 Blocking layer (silicon nitride) 103 Blocking layer (silicon oxide) 104 Semiconductor region (N-channel TFT
105 semiconductor region (P-channel TFT)
106) Gate insulating film 107 Silicon nitride film 108-111 Gate electrode / wiring (aluminum) 112, 113 Chrome wiring 114-117 Anodic oxide layer 118 N-type impurity region 119 P-type impurity region 121-125 Second layer metal wiring (Aluminum) P, Q Gate electrode / wiring and second layer metal wiring contact

Claims (3)

(57) [Claims] (1) Step of forming wiring made of aluminum
When, Different from aluminum on the wiring made of aluminum
For selectively forming a second metal coating made of different materials
About Of the wiring made of aluminum by the anodic oxidation method
Oxidation of the surface of the portion not covered with the second metal coating
Forming an aluminum film; The second metal coating or an oxide of the second metal coating
Removing Of an insulated gate semiconductor device characterized by having
Manufacturing method. (2) Form a silicon nitride film over the entire surface of the substrate
Process and Forming a wiring made of aluminum on the silicon nitride film;
Process, Different from aluminum on the wiring made of aluminum
For selectively forming a second metal coating made of different materials
About Of the wiring made of aluminum by the anodic oxidation method
Oxidation of the surface of the portion not covered with the second metal coating
Forming an aluminum film; The second metal coating or an oxide of the second metal coating
Removing Of an insulated gate semiconductor device characterized by having
Manufacturing method. (3) In claim 1 or claim 2,
Metal coating of 2 is chromium, gold, titanium, silicon, oxidation
Indium, titanium oxide, indium-titanium oxide, acid
Insulating gate type characterized by being one of zinc oxide
A method for manufacturing a semiconductor device.