JP3556241B2 - Method for manufacturing insulated gate semiconductor device - Google Patents

Description

[0001]
[Industrial applications]
The present invention relates to an insulated gate semiconductor device, particularly to a structure of a thin-film insulated gate field effect transistor (TFT) and a method of manufacturing the same.
[0002]
[Prior art]
In recent years, thin film insulated gate field effect transistors (TFTs) have been actively studied. For example, in Japanese Patent Application Nos. 4-30220 and 4-38637 of the present inventors, aluminum, titanium, chromium, tantalum, and silicon were used as a gate electrode, and the periphery was formed by an anodizing method. A manufacturing method and a TFT which cover with aluminum oxide so that the source / drain and the gate electrode are not overlapped with each other but are in an offset state, and the source / drain region is recrystallized by laser annealing are described.
[0003]
Such a TFT exhibited excellent characteristics as compared with a conventional silicon gate TFT having no offset and a TFT activated by thermal annealing using a gate electrode made of a high melting point metal such as tantalum or chromium. However, it has been difficult to obtain the characteristics with good reproducibility.
[0004]
One of the causes was due to intrusion of mobile ions such as sodium from the outside. In particular, during the formation of a gate electrode made of a metal material such as aluminum (a sputtering method or an electron beam evaporation method is used) and the subsequent anodic oxidation, there is a risk that sodium may enter from the outside. In particular, sodium contamination was large in the sputtering method. However, since the sputtering method is more excellent in mass productivity than the electron beam evaporation method, it has been desired to use the sputtering method for cost reduction.
[0005]
It has been known that sodium is blocked by phosphorus glass or the like and gettered. Therefore, the gate insulating film is generally formed of phosphorus glass. However, it has been difficult to produce phosphorus glass at the low temperature intended for the above patent. If phosphorus glass is to be manufactured at such a low temperature, many defects will be generated in the gate insulating film when the gate insulating film is implanted into the silicon oxide gate insulating film by, for example, an ion doping method. There was a thing that would be done.
[0006]
Furthermore, anodic oxidation requires a high voltage of 100 to 300 V, and there is a concern that the gate insulating film may be destroyed. That is, in the technical range shown in the above patent, a gate insulating film is formed on a semiconductor film, and a gate electrode is present thereon. However, at the time of anodization, the gate electrode is in a floating state with a positively charged gate electrode. As the voltage is generated between the semiconductor films and the anodic oxide film on the gate electrode becomes thicker and the resistance between the gate electrode and the electrolytic solution increases, the current flows from the gate electrode to the electrolytic solution via the gate insulating film and the semiconductor film. The current increases. The gate electrode may be destroyed by the current.
[0007]
[Problems to be solved by the invention]
The present invention has been made in view of such a current situation. That is, an object of the present invention is to prevent the invasion of mobile ions from the outside and prevent the gate insulating film from being broken, thereby improving reliability.
[0008]
[Means to solve the problem]
The insulated gate type semiconductor device of the present invention has at least a semiconductor layer, an insulating film layer and a gate electrode made of any one of aluminum, chromium, titanium, tantalum and silicon, or an alloy thereof or a multilayer thereof on an insulating substrate. The insulating film layer is a single layer of aluminum oxide, a single layer of silicon oxide, a single layer of silicon nitride, a single layer of aluminum nitride, two layers of an aluminum oxide layer and a silicon nitride layer, two layers of an aluminum oxide layer and a silicon oxide layer, and silicon nitride. A silicon oxide layer and an aluminum oxide layer, a silicon oxide layer and a silicon nitride layer. For example, a silicon nitride film is interposed between an aluminum gate electrode and a gate insulating film. Assuming that the composition of silicon nitride is 1, the ratio of nitrogen is preferably 1 to 4/3, more preferably 1.2 to 4/3. Of course, hydrogen or oxygen other than nitrogen and silicon may be added.
[0009]
Since this silicon nitride film has an effect of blocking mobile ions such as sodium, it not only has an effect of preventing mobile ions from entering a channel region from a gate electrode or the like, but also has an effect of preventing oxidation of a normal gate insulating film. Since it has better conductivity than silicon, an excessive voltage is not applied between the gate electrode and the semiconductor region (channel region) therebelow, so that the gate insulating film can be prevented from being broken.
[0010]
Therefore, a semiconductor region and a gate insulating film are formed, thereafter, the silicon nitride film is formed, and thereafter, an aluminum electrode for forming a gate electrode is formed. During the anodization of the aluminum electrode, it is desirable that the silicon nitride film be present integrally over the entire surface of the substrate, since the anodic potential is maintained substantially constant over the entire surface of the substrate.
In addition, the method for manufacturing an insulated gate semiconductor device according to the present invention includes a step of forming a semiconductor region on an insulating substrate, and a step of forming a single layer of aluminum oxide, a single layer of silicon oxide, a single layer of silicon nitride, and a single layer of aluminum nitride on the semiconductor region. Single layer, two layers of aluminum oxide layer and silicon nitride layer, two layers of aluminum oxide layer and silicon oxide layer, two layers of silicon nitride layer and silicon oxide layer, or three layers of aluminum oxide layer, silicon oxide layer and silicon nitride layer A step of forming an insulating film layer composed of a layer, and a step of forming a metal coating mainly comprising aluminum, chromium, titanium, tantalum, silicon, or an alloy thereof or a multilayer thereof on the insulating film layer. Forming an oxide layer on the surface of the metal film by passing an electric current in an electrolytic solution.
In the insulated gate semiconductor device and the method of manufacturing the same according to the present invention, when the gate electrode (the metal film) is made of an alloy of silicon and aluminum, the gate electrode (the metal film) contains 0.5 to 3% of silicon. It consists of an added aluminum layer.
Hereinafter, the present invention will be described in more detail with reference to Examples.
[0011]
【Example】
[Example 1]
FIG. 1 shows a cross-sectional view of a manufacturing process of this embodiment. The detailed conditions of this embodiment are almost the same as those of Japanese Patent Application No. Hei 4-30220 or Japanese Patent Application No. 4-38637 filed by the present inventors, so that they will not be described in detail. First, N-0 glass manufactured by NEC Corporation was used as the substrate 101. Although the glass has a high strain temperature, it is rich in lithium and also contains significant amounts of sodium. Therefore, in order to prevent invasion of these mobile ions from the substrate, the silicon nitride film 102 is formed with a thickness of 10 to 50 nm by a plasma CVD method or a low pressure CVD method. Further, an underlying silicon oxide film 103 was formed by a sputtering method to a thickness of 100 to 800 nm. An amorphous silicon film was formed thereon by plasma CVD to a thickness of 20 to 100 nm, and annealed at 600 ° C. for 12 to 72 hours in a nitrogen atmosphere to be crystallized. Further, this is patterned by photolithography and reactive ion etching (RIE) to form island-shaped semiconductor regions 104 (for N-channel TFT) and 105 (for P-channel TFT) as shown in FIG. And formed.
[0012]
Further, a gate oxide film 106 having a thickness of 50 to 200 nm was deposited by a sputtering method in an oxygen atmosphere using silicon oxide as a target. Further, a silicon nitride film 107 was deposited to a thickness of 2 to 20 nm, preferably 8 to 11 nm by a plasma CVD method or a low pressure CVD method.
[0013]
Next, an aluminum film was formed by a sputtering method or an electron beam evaporation method, and this was patterned by a mixed acid (a phosphoric acid solution to which 5% nitric acid was added) to form gate electrodes / wirings 108 to 111. Thus, the outer shape of the TFT was adjusted.
[0014]
Further, current was passed through the gate electrodes and wirings 108 to 111 in an electrolytic solution to form aluminum oxide films 112 to 115 by anodization. As the conditions for the anodic oxidation, the method described in Japanese Patent Application No. 4-30220, which was an invention of the present inventors, was adopted. The state so far is shown in FIG.
[0015]
Next, an N-type impurity is implanted into the semiconductor region 104 and a P-type impurity is implanted into the semiconductor region 105 by a known ion implantation method, and the N-type impurity region (source and drain) 116 and the P-type impurity region 117 are implanted. Was formed. This process used a known CMOS technology. Further, silicon nitride 107 other than that existing under the gate electrode / wiring portion was removed by a reactive ion etching method. This step can be replaced by wet etching. At that time, the etching can be performed in a self-aligned manner using aluminum oxide as a mask by utilizing the difference in etching rate between aluminum oxide and silicon nitride, which are anodic oxide films.
[0016]
Thus, a structure as shown in FIG. 1D was obtained. Needless to say, the crystallinity of the portion into which the impurities have been implanted by the previous ion implantation is remarkably deteriorated, and is substantially in an amorphous state (amorphous state or a polycrystalline state close thereto). Therefore, the crystallinity was recovered by laser annealing. This step may be performed by thermal annealing at 600 to 850 ° C. The conditions for laser annealing were, for example, those described in Japanese Patent Application No. 4-30220. After laser annealing, annealing is performed for 30 minutes to 3 hours in a hydrogen atmosphere (1 to 700 torr, preferably 500 to 700 torr) at 250 to 450 ° C., hydrogen is added to the semiconductor region, and lattice defects (dangling bonds) are formed. Etc.) reduced.
[0017]
Thus, the shape of the element was adjusted. Thereafter, as usual, an interlayer insulator 118 is formed by sputter deposition of silicon oxide, an electrode hole is formed by a known photolithography technique, and the surface of the semiconductor region or the gate electrode / wiring is exposed, Finally, a second metal film (aluminum or chromium) was selectively formed and used as electrodes / wirings 119 to 121. Here, the second metal wirings 119 and 121 cross over the first metal wirings 108 and 111. As described above, NTFT 122 and PTFT 123 were formed.
[0018]
[Example 2]
FIG. 2 is a cross-sectional view showing a manufacturing process of this embodiment. The detailed conditions of the present embodiment are almost the same as those of Japanese Patent Application No. Hei 4-30220 filed by the present inventors, and thus will not be described in detail. First, N-0 glass manufactured by Nippon Electric Glass Co., Ltd. was used as the substrate 201, and a silicon nitride film 202 having a thickness of 10 to 50 nm was formed by a plasma CVD method or a low pressure CVD method. Further, a silicon oxide film 203 as a base was formed with a thickness of 100 to 800 nm by a sputtering method. An amorphous silicon film was formed thereon by plasma CVD to a thickness of 20 to 100 nm, and annealed at 600 ° C. for 12 to 72 hours in a nitrogen atmosphere to be crystallized. Further, this was patterned to form island-shaped semiconductor regions 204 (for N-channel TFT) and 205 (for P-channel TFT) as shown in FIG.
[0019]
Further, a gate oxide film 206 having a thickness of 50 to 200 nm was deposited by a sputtering method. Further, a silicon nitride film 207 was deposited to a thickness of 2 to 20 nm, preferably 8 to 11 nm by a plasma CVD method or a low pressure CVD method.
[0020]
Next, an aluminum film was formed by a sputtering method or an electron beam evaporation method, and this was patterned to form gate electrodes / wirings 208 to 211. Thus, the outer shape of the TFT was adjusted as shown in FIG.
[0021]
Further, current was passed through the gate electrodes / wirings 208 to 211 in an electrolytic solution to form aluminum oxide films 212 to 215 by anodization. As the conditions of the anodic oxidation, the method described in Japanese Patent Application No. 30220/1991, which was an invention of the present inventors, was adopted. The state up to this point is shown in FIG.
[0022]
Next, as shown in FIG. 2C, the silicon nitride 207 and the silicon oxide 206 other than those existing under the gate electrode / wiring portion are removed by reactive ion etching to expose the semiconductor regions 204 and 205. I let it. This step can be replaced by wet etching. At that time, the etching can be performed in a self-aligned manner using aluminum oxide as a mask by utilizing the difference in the etching rate between aluminum oxide, which is an anodic oxide film, silicon nitride, and silicon oxide. Further, the semiconductor region 204 is doped with an N-type impurity and the semiconductor region 205 is doped with a P-type impurity by a laser doping technique (Japanese Patent Application No. 3-283981) of the present inventors. A region (source, drain) 216 and a P-type impurity region 217 were formed. This process used CMOS technology as described in Japanese Patent Application No. 3-283981.
[0023]
Thus, a structure as shown in FIG. 2D was obtained. In the laser doping method, the implantation of the impurity and the annealing are performed at the same time, so that the steps of laser annealing and thermal annealing as in the first embodiment are unnecessary. After the laser doping, annealing is performed in a hydrogen atmosphere (1 to 700 torr, preferably 500 to 700 torr) at 250 to 450 ° C. for 30 minutes to 3 hours, hydrogen is added to the semiconductor region, and lattice defects (dangling bonds) are formed. Etc.) reduced.
[0024]
Thus, the shape of the element was adjusted. Thereafter, as usual, an interlayer insulator 218 is formed by sputter deposition of silicon oxide, an electrode hole is formed by a known photolithography technique, and the surface of the semiconductor region or the gate electrode / wiring is exposed. Finally, a second metal film (aluminum or chromium) was selectively formed and used as electrodes / wirings 219 to 221. As described above, NTFT 222 and PTFT 223 were formed.
[0025]
[Example 3]
FIG. 3 shows a cross-sectional view of a manufacturing process of this embodiment. The detailed conditions of the present embodiment are almost the same as those of Japanese Patent Application No. Hei 4-30220 filed by the present inventors, and thus will not be described in detail. First, N-0 glass manufactured by NEC Corporation was used as the substrate 301, and a silicon nitride film 302 having a thickness of 10 to 50 nm was formed by a plasma CVD method or a low pressure CVD method. Further, a silicon oxide film 303 as a base was formed to a thickness of 100 to 800 nm by a sputtering method. An amorphous silicon film was formed thereon by plasma CVD to a thickness of 20 to 100 nm, and annealed at 600 ° C. for 12 to 72 hours in a nitrogen atmosphere to be crystallized. This was further patterned to form island-shaped semiconductor regions 304 (for N-channel TFTs) and 305 (for P-channel TFTs) as shown in FIG.
[0026]
Further, a gate oxide film 306 having a thickness of 50 to 200 nm was deposited by a sputtering method. Further, a silicon nitride film 307 was deposited to a thickness of 2 to 20 nm, preferably 8 to 11 nm by a plasma CVD method or a low pressure CVD method.
[0027]
Next, an aluminum film was formed by a sputtering method or an electron beam evaporation method, and this was patterned to form gate electrodes / wirings 308 to 311. Thus, the outer shape of the TFT was adjusted as shown in FIG.
[0028]
Further, current was passed through the gate electrodes / wirings 308 to 311 in the electrolytic solution to form aluminum oxide films 312 to 315 by anodization. As the conditions for the anodic oxidation, the method described in Japanese Patent Application No. 4-30220, which was an invention of the present inventors, was adopted. The state up to this point is shown in FIG.
[0029]
Next, an N-type impurity is implanted into the semiconductor region 304 and a P-type impurity is implanted into the semiconductor region 305 by a known plasma ion doping method, and the N-type impurity region (source and drain) 316 and the P-type impurity region are implanted. 317 was formed. This process used a known CMOS technology. In addition to impurity elements, hydrogen used as a diluent for a gas source was also ionized from the plasma and injected into the semiconductor region. Although this step can be performed by a known ion implantation method, it is required to separately implant hydrogen ions for the reason described later.
[0030]
Thus, a structure as shown in FIG. 3D was obtained. Needless to say, the crystallinity of the portion into which the impurities have been implanted by the previous ion implantation is remarkably deteriorated, and is substantially in an amorphous state (amorphous state or a polycrystalline state close thereto). Therefore, the crystallinity was recovered by laser annealing. This step may be performed by thermal annealing at 600 to 850 ° C. The conditions for laser annealing were, for example, those described in Japanese Patent Application No. 4-30220. However, since the silicon nitride film 307 does not transmit short-wavelength ultraviolet light having a wavelength of 250 nm or less, an XeCl laser (308 nm) or a XeF laser (351 nm) was used.
[0031]
After the laser annealing, annealing is performed in a hydrogen atmosphere (1 to 700 torr, preferably 500 to 700 torr) at 250 to 450 ° C. for 30 minutes to 3 hours to reduce lattice defects (dangling bonds, etc.) in the semiconductor. . Actually, since the silicon nitride film 307 exists, there is almost no exchange of hydrogen inside and outside the semiconductor region. Therefore, for example, in the plasma doping method, a large amount of hydrogen atoms are implanted into the semiconductor region, but in the ion implantation method, a hydrogen ion implantation step is required separately. In the plasma doping method, if the amount of hydrogen is insufficient, hydrogen must be separately doped.
[0032]
Thus, the shape of the element was adjusted. Thereafter, as usual, an interlayer insulator 318 is formed by sputter deposition of silicon oxide, an electrode hole is formed by a known photolithography technique, and the surface of the semiconductor region or the gate electrode / wiring is exposed, Lastly, a second metal film (aluminum or chromium) was selectively formed and used as electrodes / wirings 319 to 321. As described above, NTFT 322 and PTFT 323 were formed.
[0033]
[Example 4]
“Thin-film insulated gate semiconductor device and method of manufacturing the same”, filed on February 25, 1992, by the present inventors (Applicant, Semiconductor Energy Laboratory Co., Ltd., serial numbers P002042-01 to P002044-) FIG. 2 shows an example in which the present invention is applied to a TFT having a two-layer channel described in No. 03, 3 above).
[0034]
That is, in FIGS. 4, 5, and 6, 401, 501, and 601 are N-channel TFTs, and 402, 402, and 402 are P-channel TFTs. In each of the drawings, first layers 408, 410, and 508 of a channel region are shown. , 510, 508, 510 are substantially made of amorphous silicon. Its thickness was 20-200 nm.
[0035]
In addition, 407, 409, 507, 509, 607, and 609 are substantially polycrystalline or semi-amorphous silicon, and have a thickness of 20 to 200 nm. Further, 404, 406, 504, 506, 604, and 606 are gate insulating films made of silicon oxide and have a thickness of 50 to 300 nm. 403, 405, 503, 505, 603, and 605 are silicon nitride films having a thickness of 2 to 20 nm formed in the same manner as in the first to third embodiments. These structures were manufactured based on the description of the above patent application or Example 1.
[0036]
【The invention's effect】
As described above, the penetration of mobile ions is prevented by forming a silicon nitride film, a silicon oxide film, an aluminum oxide film, an aluminum nitride film, or a multilayer film thereof between the gate electrode and the semiconductor layer (channel region). In addition, it was possible to prevent the gate insulating film from being broken at the time of anodic oxidation of the gate electrode.
[Brief description of the drawings]
FIG. 1 shows a manufacturing process diagram (cross section) of a semiconductor device according to the present invention.
FIG. 2 shows a manufacturing process diagram (cross section) of a semiconductor device according to the present invention.
FIG. 3 shows a manufacturing process diagram (cross section) of a semiconductor device according to the present invention.
FIG. 4 shows a structural example of a semiconductor device according to a conventional example.
FIG. 5 shows a structural example of a semiconductor device according to a conventional example.
FIG. 6 shows a structural example of a semiconductor device according to a conventional example.
[Explanation of symbols]
101 Insulating substrate 102 Blocking layer (silicon nitride)
103 Blocking layer (silicon oxide)
104 semiconductor region (for N-channel TFT)
105 Semiconductor area (for P-channel TFT)
106 Gate insulating film 107 Silicon nitride film 108-111 Gate electrode / wiring (aluminum)
112 to 115 Anodic oxide layer 116 N-type impurity region 117 P-type impurity region 118 Interlayer insulator 119 to 121 Second layer metal wiring 122 NTFT
123 PTFT

Claims (3)

Forming a first silicon nitride film on the insulating substrate;
Forming a first silicon oxide film on the first silicon nitride film;
Forming an island-shaped semiconductor film on the first silicon oxide film;
Forming a second silicon oxide film on the island-shaped semiconductor film and the first silicon oxide film;
Forming a second silicon nitride film on the second silicon oxide film;
Forming a gate electrode on the second silicon nitride film, anodizing the gate electrode,
Adding N-type or P-type impurities to the island-shaped semiconductor film to form a source region and a drain region,
Removing the second silicon nitride film on the source region and the drain region;
Recovering the crystallinity of the source region and the drain region,
Forming a third silicon oxide film on the second silicon oxide film and the gate electrode;
Patterning the third silicon oxide film and the second silicon oxide film to form a contact hole;
A method for manufacturing an insulated gate semiconductor device, wherein a source electrode and a drain electrode are formed using the contact holes. Forming a first silicon nitride film on the insulating substrate;
Forming a first silicon oxide film on the first silicon nitride film;
Forming an island-shaped semiconductor film on the first silicon oxide film;
Forming a second silicon oxide film on the island-shaped semiconductor film and the first silicon oxide film;
Forming a second silicon nitride film on the second silicon oxide film;
Forming a gate electrode on the second silicon nitride film, anodizing the gate electrode,
Removing a second silicon nitride film and a second silicon oxide film on a region to be a source region and a region to be a drain region in the island-shaped semiconductor film;
Adding N-type or P-type impurities to the island-shaped semiconductor film to form a source region and a drain region,
Recovering the crystallinity of the source region and the drain region,
Forming a third silicon oxide film on the island-shaped semiconductor film and the gate electrode;
Patterning the third silicon oxide film to form a contact hole;
A method for manufacturing an insulated gate semiconductor device, wherein a source electrode and a drain electrode are formed using the contact holes. Forming a first silicon nitride film on the insulating substrate;
Forming a first silicon oxide film on the first silicon nitride film;
Forming an island-shaped semiconductor film on the first silicon oxide film;
Forming a second silicon oxide film on the island-shaped semiconductor film and the first silicon oxide film;
Forming a second silicon nitride film on the second silicon oxide film;
Forming a gate electrode on the second silicon nitride film, anodizing the gate electrode,
Adding N-type or P-type impurities to the island-shaped semiconductor film to form a source region and a drain region,
Recovering the crystallinity of the source region and the drain region,
Forming a third silicon oxide film on the second silicon nitride film and the gate electrode;
Patterning the third silicon oxide film, the second silicon nitride film, and the second silicon oxide film to form a contact hole;
A method for manufacturing an insulated gate semiconductor device, wherein a source electrode and a drain electrode are formed using the contact holes.

Images