JPH05342028A - Error display circuit - Google Patents

Abstract

PURPOSE:To identify either an error signal outputted from an error detection circuit or the fault of an error display register itself at the error display circuit of an information processor. CONSTITUTION:Error display registers 30, 31, 32 and 33 hold error signals L20, L21, L22 and L23 outputted from error detection circuits 20, 21, 22 and 23. AND circuits 70 and 71 output error identification signals L70 and L71 by ANDing error signals L60 and L61 inverted by inverters 60 and 61 and error display signals L32 and L33 outputted from the error display registers 32 and 33. A fault processing control part 5 controls fault processing by recognizing the detection of a fault part or a fault corresponding to the error display signals L30, L31, L32 and L33, error report signal L4 and identification signals L80 and L81.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error display system of an information processing apparatus, and more particularly to an error display circuit effective for diagnosing a failure.

[0002]

2. Description of the Related Art FIG. 2 shows an error display circuit of a conventional information processing apparatus. Reference numerals 92 and 93 denote LSIs forming an information processing device, and the logic circuit 12 on the LSI 93.
The error detection circuit 22 for detecting the error, the logic circuit 13 on the LSI 93, and the error display register 33 for holding the error signal L23 output from the error detection circuit 23 are the LSI.
It's on 92. Numerals 10, 11, 12, 13 are logic circuits for realizing the functions of the LSI, and status signals L10, L11, L12, L13 indicating the statuses of the logic circuits necessary for error detection.
Is output. Reference numerals 20, 21, 22, and 23 are error detection circuits for checking whether or not an error has occurred in the logic circuits 10, 11, 12, and 13 and outputting error signals L20, L21, L22, and L23. 30, 31, 32, 33
Is an error display register for holding the error signals L20, L21, L22, L23 output from the error detection circuits 20, 21, 22, 23. It is held by the report signal L4. The OR circuit 4 takes the logical sum of the output error display signals L30, L31, L32, L33 of the error display registers 30, 31, 32, 33 to generate an error of at least 1 bit in the error display registers 30, 31, 32, 33. The error report signal L4 indicating that is held is output. By holding the error display register with this error report signal L4, it is possible to know in which logic circuit the error first occurred. The failure processing control unit 5 uses the error display signals L30, L31, L
32, L33, and the error report signal L4 are used to detect the fault and the fault location, and perform fault processing.

[0003]

In the conventional error display circuit described above, when an error is held in the error display register, whether the cause is the error signal output from the original error detection circuit or not. Since there is no effective means for discriminating whether or not it is due to its own failure, a part for mounting an error display register is always added to the suspected parts pointed out in the failure diagnosis. Therefore, there is a drawback that the failure diagnosis dictionary file increases, and since the number of parts replaced due to failures is large, the failure recovery time (M
There was a major drawback of increasing TTR).

[0004]

According to a first aspect of the present invention, an error display register having a plurality of bits for holding an error signal output from an error detection circuit of a plurality of logic circuits and an error of at least 1 bit in the error display register. And an error reporting circuit that outputs an error reporting signal when the error is held, and an identification signal reporting mechanism that outputs an identification signal when at least one bit of the error display register fails. An identification flag register that holds the identification signal, and a failure processing control unit that performs failure processing control by referring to an output value of the identification flag register when the error report signal is received.

[0005]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention.

Reference numerals 90 and 91 are LSs constituting an information processing device.
I, the error detection circuit 22 for detecting an error in the logic circuit 12 on the LSI 91 and the logic circuit 1 on the LSI 91.
3. The error display register 33 that holds the error signal L23 output from the error detection circuit 23 is on the LSI 90. Numerals 10, 11, 12, and 13 are logic circuits for realizing the functions of the LSI, and output status signals L10, L11, L12, and L13 indicating the states of the logic circuits necessary for error detection. 20, 21, 22, 23 are logic circuits 10, respectively.
An error detection circuit that checks whether an error has occurred in 11, 12, and 13 and outputs error signals L20, L21, L22, and L23. Reference numerals 30, 31, 32, and 33 are error display registers for holding the error signals L20, L21, L22, and L23 output from the error detection circuits 20, 21, 22, and 23, and are ORed when an error of at least 1 bit is held. It is held by the error reporting signal L4 output from the circuit 4. The OR circuit 4 outputs the error display signals L30, L30 from the error display registers 30, 31, 32 and 33.
By taking the logical sum of L31, L32, and L33, an error report signal L4 indicating that at least one bit error is held in the error display registers 30, 31, 32, and 33 is output.

Therefore, by holding the error display register, it is possible to know in which logic circuit the error first occurred. A failure processing control unit 5 controls failure processing by knowing that a failure location or failure is detected by the error display signals L30, L31, L32, L33 and the error report signal L4 and the identification signals L80, L81. The inverters 60 and 61 are the error detection circuits 22 and 23, respectively.
The error signals L22 and L23 output by are inverted. A
The ND circuits 70 and 71 have error signals L60 and L61 inverted by the inverters 60 and 61 and the error display register 3
Error display registers 32 and 33 are obtained by taking the logical product of the error display signals L32 and L33 which are the outputs of 2 and 33.
Outputs an error identification signal L70, L71 which becomes 1 only when a failure occurs and an error is detected. 80 and 81 are AN
Error identification signals L70, L output from the D circuits 70, 71
An identification flag register for holding 71 is held by the error report signal L14 output from the OR circuit 4.

In this embodiment, the error display signals L32, L
Although the AND circuits 70 and 71 corresponding to 33 are provided and described, it is clear that in an actual circuit, it is more effective to provide AND circuits corresponding to the error display signals L30 and L31.

[0010]

As described above, according to the present invention, the identification flag register corresponding to the error display register is provided separately from the error display register so that the failure of the error display register can be detected. This has the effect of reducing the number of parts pointed out in the diagnosis.
Furthermore, since the number of parts can be reduced, the failure recovery time (MTTR) can be shortened.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing an example of a conventional technique.

[Explanation of symbols]

 10, 11, 12, 13 Logic circuit 20, 21, 22, 23 Error detection circuit 30, 31, 32, 33 Error display register 4 OR circuit 5 Fault processing control unit 60, 61 Inverter 70, 71 AND circuit 80, 81 Identification Flag register 90, 91, 92, 93 LSI L10, L11, L12, L13 Status signal L20, L21, L22, L23 Error signal L30, L31, L32, L33 Error display signal L4 Error report signal L60, L61 Inversion error signal L70, L71 error identification signal L80, L81 identification signal

Claims (1)

[Claims] 1. An error display register having a plurality of bits for holding error signals output from error detection circuits of a plurality of logic circuits, and an error report signal is output when an error of at least 1 bit is held in the error display register. In an error display circuit having an error reporting mechanism for performing an error report by means of at least one of the error display registers.
An identification signal reporting mechanism that outputs an identification signal when a bit fails, an identification flag register that holds the identification signal, and an output value of the identification flag register when the error reporting signal is received to perform failure handling control. An error display circuit having a failure processing control means for performing the error processing.