JPS62262147A - Fault detecting device - Google Patents

Abstract

PURPOSE:To improve the accuracy for detecting a data bit error in a register, by deciding that a genuine fault has been generated, when an error existence detecting signal has been generated in even one of all the outputs of an error existence detecting signal generating circuit. CONSTITUTION:Only when a parity error has been detected truly by an AND function of error existence detecting signal generating circuits 81-8n, an error existence detecting signal is generated from one of the corresponding circuits 81-8n. In this case, when the device is constituted so that this error existence detecting signal is detected by an AND function of a total error detecting circuit 9, generation of a true parity error can be detected. By an output timing of the circuit 9, down of a system and a unit, and also, an error processing procedure are started first, a scan bus 6 is driven against each register 21-2n, all the contents are stored in a saving register 7 and a fault analysis is executed.

Description

DETAILED DESCRIPTION OF THE INVENTION 1. Distortion and 1. Field of the Invention The present invention relates to a fault detection device, and particularly to an information processing system. This invention relates to failure detection\Ara, which detects failures by detecting errors in information stored in data registers in devices.

BACKGROUND OF THE INVENTION Conventionally, this type of failure detection device has a configuration as shown in FIG. Data 11 to 1n (n
is a positive integer) is supplied to and stored in the corresponding n registers 21 to 2n, respectively. Parity error detection circuits 31 to 3n are provided corresponding to each of these registers 21 to 2n, and determine whether a binary number is odd or even as the sum of the data bits of each register. For example, in the case of even parity, , a register output with an odd number of bits is regarded as a parity error, and the presence of an error is detected.

The respective outputs of these parity error detection circuits 31 to 3n are all introduced to the representative error detection circuit 5 via data paths such as corresponding gates 41 to 4n, respectively. In the representative error detection circuit 5, all of these inputs are subjected to logical processing and if even one is detected to have a parity error, an error presence signal (ie, a fault presence signal) is generated.

That is, if an error presence signal is generated from the representative error detection circuit 5, it is assumed that there is a fault, and this signal is used as a starting signal for system down or unit down. Thereafter, an error handling procedure is carried out, and the data contents of each register 21 to 2n are serially transmitted through the scan path 6 and are all saved in the scan register 7. The data of this scan pasta 7 is compared with data that should be normal and analyzed to investigate the contents of the failure point. This failure analysis investigation is normally performed by an operator.

In such a conventional device, the representative error detection circuit 5 logically ORs all the parity error detection information from each register and uses this OR output to determine that there is a failure. 31~3n
If there are failures in various gates or signal paths from to the representative error detection circuit 5, there is a drawback that the number of such failures is not taken into account. Therefore, even in such a case, there is a drawback that even if the system down or unit down processing is performed and the contents of the individual registers are checked using the above-mentioned analysis procedure, no error is found in any of them, resulting in a waste of effort.

OBJECTS OF THE INVENTION It is an object of the present invention to provide a failure detection device that can perform accurate data error detection to effectively detect failures.

1 and 1 A failure detection device according to the present invention includes a plurality of parity error detection circuits provided corresponding to a plurality of registers each storing data and detecting parity errors of data bits of the corresponding registers, and the like. A representative error detection circuit is provided corresponding to the plurality of parity error detection circuits, and a representative error detection circuit that receives all of the outputs of the parity error detection circuit as input and generates an error presence signal if any parity error is detected. a plurality of error existence detection signal generation circuits each receiving the output of the parity error detection circuit and the output of the representative error detection circuit and generating error existence detection signals when both outputs both indicate the existence of an error;
The present invention is characterized in that when any one of the outputs of these error detection signal generation circuits generates an error detection signal, it is determined that a true fault has occurred.

Example Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, and parts equivalent to those in FIG. 2 are designated by the same reference numerals.

To describe the difference from the conventional example in FIG. 2, nl error existence detection signal generation circuits 81 to 8n are provided corresponding to the parity error detection circuits 31 to 3n, respectively. The parity error detection outputs of the corresponding parity error detection circuits 31 to 3n are applied to each of the input terminals 8n to 8n, and the output of the representative error detection circuit 5 is branched and supplied to each input terminal. These error presence detection signal generation circuits 81 to 8n have a two-manual AND operation function, and generate an error presence detection signal when both inputs indicate the presence of an error. These error existence detection signal generation circuits 81 to 8n
All outputs are input to the total error detection circuit 9, and all the outputs are logically summed. This OR output becomes a true failure detection signal.

The other configurations are the same as those shown in FIG. A presence detection signal is generated. Therefore, this error existence detection signal is combined with the logical sum I! of the total error detection circuit 9. If the detection is performed based on the function, it becomes possible to detect the occurrence of a true parity error.

It is only at this output timing of the total error detection circuit that the system or unit is brought down, and furthermore, the error processing procedure is started, and the scan path 6 is applied to each register 21 to 2n.
is driven to store all contents in the save register 7 and perform failure analysis.

By doing this, the representative error detection circuit 5
Compared to the case where the output is directly entered into the error processing procedure as a system or unit down, the accuracy of error detection of data bits in the register can be improved, and subsequent system or unit down, error processing, etc. are not as wasteful. Efficiency can be improved.

As described above, according to the present invention, the final total error detection is performed by comparing the detection results of the representative error detection circuit with the parity error individual detection results of each register. This has the effect of improving the accuracy of data bit error detection. Therefore, it is possible to improve the efficiency of subsequent operations such as error processing.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram showing a conventional technique. Explanation of symbols of main parts

Claims (1)

[Claims] A plurality of parity error detection circuits are provided corresponding to a plurality of registers that respectively store data and detect parity errors of data bits of the corresponding registers, and one of the plurality of parity error detection circuits receives all of the outputs of these parity error detection circuits as input. a representative error detection circuit that generates an error presence signal if even one parity error is detected; and a representative error detection circuit that is provided corresponding to the plurality of parity error detection circuits and that outputs the output of the corresponding parity error detection circuit and the output of the representative error detection circuit. A plurality of error existence detection signal generation circuits are provided, each of which receives an output and generates an error existence detection signal when both of these outputs indicate the existence of an error. A failure detection device characterized in that when any one of the error detection signals is generated, it is determined that a true failure has occurred.