JPH04352241A - Fault diagnostic system - Google Patents

Abstract

PURPOSE:To know how a fault is generated in a device in any process by providing a timing decision circuit provided on a flip-flop and a storage means for storing the output result of the timing decision circuit. CONSTITUTION:Signals 8 and 10 of EIF are 1 when a fault is generated and 0 when not. When no fault occurs to this unit, the value of the signal 8 and 0 and the value of a signal 15 inverted through an inverter 6 is 1; and AND gates 4 and 5 make logic product with EIF signals 16 and 17 of the other unit and send the results to flip-flops 2 and 3 through signal lines 11 and 12. If a fault occurs to this unit, on the other hand, the signal 15 is 1 and even when the EIF of the other unit is set, 1 is set in neither of the flip-flops 2 and 3. Namely, what place in the order this unit sets the EIF in is known from the values of the flip-flops 1, 2, and 3. A flow of fault occurrence is therefore known.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fault diagnosis system for data processing equipment.

0002

[Prior Art] Conventionally, the EIF (Error Indication Flag) signal of each unit is reported to a diagnostic device that manages device failures independently of the EIF signals of other units. Information such as whether an error occurred could not be obtained.

0003

[Problems to be Solved by the Invention] In the conventional fault diagnosis method described above, only the presence or absence of a fault is investigated using the EIF signal of each unit. The drawback was that it was unclear what caused the failure.

0004

[Means for Solving the Problems] The present invention is a fault diagnosis method for a data processing device having an EIF for each unit, and when the EIF of one unit is in a state indicating the occurrence of a fault, it becomes one state. The first flip-flop that holds the EIF of the other unit is provided corresponding to the EIF of the other unit, and when the corresponding EIF of the other unit becomes the state indicating the occurrence of a failure first, it enters the state of 1. and a second flip-flop that holds the state.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.

FIG. 1 shows an embodiment for implementing the present invention.

[0007] The data processing device has an EIF for each unit. A flip-flop 1 is a circuit that holds one unit of its own EIF signal 8, an inverter 6 and AND gates 4 and 5.
1 is a timing determination circuit for information on signal lines 8, 16, and 17, and the flip-flops 2, 3 and diagnostic device 7 function as storage means for storing timing determination results.

Next, the operation of this embodiment will be explained. E
IF signals 8 and 10 take a value of 1 when a failure occurs, and take a value of 0 otherwise. If no failure has occurred in the own unit, the value of signal 8 takes 0, and the value of signal 15 inverted via inverter 6 becomes 1, and EIF signals 16 and 17 of other units are output by AND gates 4 and 5. The logical product is ANDed and transmitted to the flip-flops 2 and 3 via signal lines 11 and 12. If EIF is set in another unit, the value 1 is set in flip-flops 2 and 3. Furthermore, each of the flip-flops 1, 2, and 3 can hold the value 1 by using the output signals 9, 13, and 14 as hold signals.

On the other hand, if a failure occurs in the own unit, the signal 15 takes the value 0, and later the EIF of the other unit
Even if , the value 1 is not set in flip-flops 2 and 3. In other words, it is possible to predict which unit has set EIF based on the values of flip-flops 1, 2, and 3.

0010

Effects of the Invention As explained above, the present invention includes a timing judgment circuit in a flip-flop and a storage means for storing the output result of the timing judgment circuit. This has the effect of letting you know if it has occurred.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention.

[Explanation of symbols]

1 Flip-flop 4,5 And gate 6 Inverter 7 Diagnostic equipment

Claims (1)

[Claims] Claim 1. In a fault diagnosis method for a data processing device having an EIF for each unit, the EI of one unit is
A first flip-flop that becomes one state and maintains that state when F enters a state indicating the occurrence of a failure, and a first flip-flop that is provided in correspondence with the EIF of another unit and that is designed to be more sensitive to the corresponding EIF of the other unit than its own EIF. and a second flip-flop that becomes one state and maintains that state when the first flip-flop becomes a state indicating that a failure has occurred.