JPH0534042Y2 - - Google Patents

Description

[Detailed Description of the Invention] <Industrial Field of Application> The present invention relates to improving the hit rate of a small-capacity, high-speed cache memory device.

<Prior Art> FIG. 2 shows a block diagram of a conventional direct mapping type cache memory device.

In this figure, reference numeral 1 denotes a tag memory section which is connected to the address bus AB and is provided with a tag section and an index section of the address information output from the central processing unit CPU2, and stores the last accessed tag value; 3 is a valid bit setting section in which a valid bit indicating whether or not the tag section specified by the given index section is valid is set; 5 is a valid bit setting section in which a valid bit indicating whether the tag section specified by the given index section is valid; 6 is a gate circuit which inputs the output of the comparator 5 and the valid bit and outputs hit/miss information; and 7 is a data section for storing data.

In addition, the address information given from CPU1 is
As shown in FIG. 3, it consists of a tag section (TAG), an index section (INDEX), and a data block length section (BLOCK).

In such a cache memory device, when the CPU 2 starts a memory access operation, address information (tag section, index section) is given to the tag memory section 1 from the address bus AB, and the index section is further provided with valid data. The bit setting section 3 receives the bit setting section 3.

Here, the tag memory section 1 stores the tag value when accessed the previous time, and provides the comparator 5 with the tag value specified by the index section this time. On the other hand, the index section is also applied to the valid bit setting section 3, and the corresponding valid bit is read out and applied to one input of the gate circuit 6.

Further, the comparator 5 compares the tag value from the tag memory section 1 with the tag value of the address information given this time, and provides the comparison output to the other input of the gate circuit 6.

The gate circuit 6 outputs hit information or miss information to the cash controller 4 through two inputs. The cache control unit 4 validates or invalidates the data on the data bus DB output from the data unit 7 based on this hit/miss information, and if it is valid, the contents of the data unit 7 of the cache memory are used. , if invalid, the contents of the main memory (not shown) are used.

In this way, the cache memory device is controlled, but for example, due to switching or relocation of programs, there is a possibility that the contents of the cache memory and the contents of the main memory will not match. When there was a rewrite, the entire cache memory was cleared.

<Problems to be Solved by the Invention> However, the above method has a problem in that the hit rate decreases because the entire cache memory is cleared.

The present invention attempts to solve this problem, and aims to improve the hit rate of a cache memory device with a simple hardware configuration.

<Means for solving the problem> The present invention, which solves the above problems, stores the tag value accessed up to the previous time by giving the tag part and the index part of the address information given by the central processing unit. It has a tag memory section, and includes a valid bit indicating whether the tag value in the tag memory section designated by the index section is valid, and an output that compares the previous tag value with the currently given tag value. In a cache memory device that outputs hit/miss information by a CPU, an operating mode signal M indicating whether the central processing unit operates in a supervisor mode or a user mode is provided to indicate a supervisor mode. a cache control unit that outputs a signal _M1 and a signal _M2 representing a user mode; and the cache control unit sets or resets a valid bit in a supervisor mode valid bit setting unit or a user mode valid bit setting unit. action mode·
a valid bit setting section; an operation mode selection means for selecting one of the valid bits set in the operation mode valid bit setting section by the operation mode signal M given from the central processing unit; The cache memory device has clear request generating means for outputting a cache memory clear request signal for each operation mode to the cache control section based on address information of a processing device.

<Function> When rewriting the cache memory, the cache memory device of the present invention sets the valid bit corresponding to the current operation mode among the plurality of operation mode valid bit setting units,
When clearing the cache memory, the clearing operation is performed for each specified operating mode, and data for other operating modes remains.

<Embodiment> FIG. 1 is a block diagram of a cache memory device embodying the present invention.

In this figure, parts having the same symbols as the conventional device shown in FIG. 2 have functions.

The device of the present invention is characterized by being provided with an operation mode/valid bit setting section 8, an operation mode selection means 9, and a clear request generation means 10.

The operation mode valid bit setting section 8 is a supervisor mode valid bit setting section 8.
₁ and user mode valid bit setting section 8 ₂
The operation mode selection means 9 is composed of an AND gate and an OR gate, and switches the bit outputs from the valid bit setting sections 8 ₁ and 8 ₂ and supplies it to the gate circuit 6.

The clear request generating means 10 is composed of an address decoder, etc., and uses data on the data bus DB or address information from the CPU 2 to cause the cache control unit 4 to enter supervisor mode,
Outputs a cache memory clear request signal for each user mode.

The operation of the apparatus of the present invention constructed in this way will be described next.

When CPU2 starts memory access operation,
Address information from address bus AB (tag section,
The index section) is provided to the tag memory section 1, and the index section is further provided to the operation mode valid bit setting section 8. CPU at the same time
2 runs in supervisor mode or user
An operation mode signal M indicating which mode is to be operated is outputted, and this operation mode signal M is transmitted to the cash controller 4 and the operation mode selection means 9.

The operation mode valid bit setting unit 8 is provided with the index portion of the address, and is provided with operation mode signals _M1 , _M2 from the cache control unit 4. In response to this, a valid bit is set in the supervisor mode valid bit setting unit ₈₁ or the user mode valid bit setting unit ₂ , indicating whether the provided tag portion is valid in the supervisor mode or the user mode, and this is output to the operation mode selection means 9.

The operation mode selection means 9 selects one of the valid bits provided from the operation mode valid bit setting section 8 according to the operation mode signal M provided from the CPU 2, and provides open/close information to the gate circuit 6. That is, when accessing in supervisor mode, bit setting section ₈₁ is selected and the user
When accelerating in this mode, the output of the bit setting section ₈₂ is selected.

Here, if the cache access is a hit (if the output of comparator 5 matches and the valid bit on the side specified by the operating mode of CPU2 is valid), CPU2 accesses the data indicated by this index section. Read the contents of section 7.

In the case of a mistake (comparator 5 output does not match, CPU
2), the CPU 2 reads data from the main memory section (not shown), and at the same time the cache control section 4 reads the data from the index section in the tag memory section 1. Adds the tag value to the specified address and the data
Write the data on the bus DB to the data section 7, and if it is in supervisor mode, bit setting section 8 ₁
"1" is set in the bit setting section ₈₂ , and "0" is set in the bit setting section 82. At this time, if it is the user mode, "0" is set in the bit setting section ₈₁ and "1" is set in the bit setting section ₈₂ . This specifies whether the value of the tag part is valid in supervisor mode or user mode.

Additionally, when a program or data in main memory is changed or rearranged, it is necessary to clear the cache memory so that the contents of main memory and cache memory match.
2 gives a clear signal to the clear request generating means 10, and the clear request generating means 10 gives an operation mode and a clear instruction signal to the cash controller 4. Further, the cache control section 4 outputs a valid bit reset signal (M ₁ , M ₂ ) to the bit setting section 8 ₁ or the bit setting section 8 ₂ or both to clear the cache memory.

In this way, even when clearing the cache memory, the clearing operation is performed only for the operating mode specified by the CPU 2, so data for other operating modes remains, and the necessary data cannot be cleared. This eliminates the need to do so, increasing the hit rate.

<Effects of the invention> When rewriting the cache memory, the cache memory device of the invention sets the valid bit corresponding to the current operation mode among the plurality of operation mode valid bit setting sections,
If a program is rearranged on the main memory, a task is switched, etc., by clearing only the valid bits of the operating mode that needs to be cleared, the data of other operating modes will remain, making it easy to do so. The hit rate of the cache memory device can be improved with a simple hardware configuration.

[Brief explanation of the drawing]

Figure 1 is a block diagram of a cache memory device embodying the present invention, Figure 2 is a block diagram of a conventional cache memory device, and Figure 3 is a block diagram of a conventional cache memory device.
FIG. 3 is a configuration diagram of addresses given from the CPU. 1...Tag memory section, 2...Central processing unit
CPU, 3... Valid bit setting section, 4...
Cash control section, 5... Comparator, 6... Gate circuit, 7... Data section, 8... Operating mode/valid bit setting section, 8 ₁ ... Supervisor mode/valid bit setting section, 8 ₂ ...User mode valid bit setting unit, 9...Operation mode selection means, 10...Clear request generation means, AB...Address bus, DB...Data bus
bus.

Claims (1)

[Scope of utility model registration request] Of the address information given by the central processing unit, a tag part and an index part are given, and the tag memory part stores the tag values accessed previously, and the data in the tag memory part specified by the index part is given. In a cache memory device that outputs hit/miss information based on a valid bit indicating whether a tag value is valid or not, and an output that compares the previous tag value with the tag value given this time, the central processing a cache controller which is given an operating mode signal M indicating whether the device operates in a supervisor mode or a user mode and outputs a signal _M1 indicating the supervisor mode and a signal _M2 indicating the user mode; , an operation mode valid bit setting unit for setting or resetting a valid bit in the supervisor mode valid bit setting unit or the user mode valid bit setting unit by the cache control unit; an operation mode selection means for selecting one of the valid bits set in the operation mode valid bit setting section by an operation mode signal M; and an operation mode selection means for selecting one of the valid bits set in the operation mode valid bit setting section; a cache memory device having a clear request generating means for outputting a cache memory clear request signal to the cache memory device.