JP3070056B2 - Information processing device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus, and more particularly, to a presettable high-speed conversion index buffer mechanism dedicated to task switching, and an input / output port to the high-speed conversion index buffer mechanism. And an information processing apparatus having the same.

[Prior Art] As a conventional information processing apparatus, as shown in FIG.
Dynamic address translation mechanism 2 and high-speed translation index buffer mechanism (TBL:
Translation Look-aside Buffer) 13a is operated at the same time, and the real address 11 is obtained by setting the one for which the real address 11 was obtained first as the base pointer 9 of the page address, and setting the lower part of the virtual address 1 as the page offset address 10. I have. Here, if there is no data that matches the translation address in the high-speed translation index buffer 13a, the address obtained by the dynamic address translation mechanism 2 is set in the high-speed translation index buffer 13a. This high-speed conversion index buffer mechanism 1
The setting method for 3a is the LRU method (Least Recently Used Rul
e). This LRU method writes on the table that has not been accessed most recently.

[Problems to be solved by the invention]

In the conventional information processing apparatus described above, since the high-speed conversion index buffer mechanism 13a is one-way traffic, the contents of the high-speed conversion index buffer mechanism 13a are rewritten every time a page is changed (registered in the high-speed conversion index buffer mechanism). If the task is not switched, the probability that the real address 11 of the task is registered in the high-speed translation look-up buffer 13a when the task is switched is low, and it is necessary that the real address 11 be calculated by the dynamic address translator 2 every time. There is a disadvantage that the switching time becomes longer.

It is an object of the present invention to provide an information processing apparatus in which a task switching time is reduced by providing a preset high-speed conversion index buffer mechanism dedicated to task switching and a high-speed conversion index buffer mechanism having an input / output port. is there.

[Means for solving the problem]

The configuration of the information processing apparatus of the present invention includes a first high-speed conversion index buffer mechanism normally accessed, and a position of a task necessary for task switching and an OS resident, which are provided separately from the first high-speed conversion index buffer mechanism. It is characterized in that it has a second high-speed conversion index buffer mechanism dedicated to task switching, which can set a program address in advance, and an input / output port to these first and second high-speed conversion index buffer mechanisms.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention. In the present embodiment, in addition to the conventional high-speed conversion index buffering mechanism 13, a presettable high-speed conversion index buffering mechanism 12, 13 for task switching is set.
And a switching control circuit 14 serving as an input / output port of
High-speed conversion index buffering mechanism dedicated to task switching from I / O ports
In 12, the position of the task required for task switching and the address of the program resident in the operating system are set in advance, and when the task switching process is performed,
The task switching dedicated high-speed translation index buffer mechanism 12 and the dynamic address translation mechanism 2 are operated at the same time. And seeks the real address 11.

If there is no data that matches the translation address in the task switching dedicated high speed translation index buffer 12, the address obtained by the dynamic address translation mechanism 2 is set in the task switching dedicated high speed translation index buffer 12. The setting method of the high-speed conversion index buffer mechanism 12 is performed based on the LRU method.

The virtual address 1 is translated into a real address 11 by the dynamic address translation mechanism 2 or the high-speed translation index buffering mechanism 12, 13. The dynamic address translation mechanism 2 translates the virtual address 1 into the real address 11 by the following method.

FIG. 2 is a layout diagram showing the configuration of the address space of the present embodiment. The virtual space A is composed of four sections B, and one section B is composed of 1024 areas C.

Section ID 3 by upper 2 bits of virtual address 1
And the corresponding area table register pair 4 is selected. An area table entry is selected from the area table 6 with the area ID 5 indicated by the bits “20 to 29” of the virtual address 1 as an index number based on the base address specified by the area table register pair 4. Based on the base address specified in the area table entry, bits “12 to
A page table entry is selected from the page table 8 using the page ID 7 indicated by "19" as an index number. Finally, the virtual address 1 is added to the page table entry.
Are connected to obtain the real address 11 of the data to be accessed.

On the other hand, in the high-speed conversion index buffering mechanisms 12 and 13, first, the high-speed conversion index buffering mechanism 12 is dedicated to the task switching, and the position of the task and the address of the program resident in the operating system required for the task switching are input and output from the input / output port 16 in advance. Set in advance. The task switching control circuit 14 determines whether or not the conversion from the virtual address to the real address is a task switching. If the task switching is not a task switching, the real address page base pointer 9 is obtained from the normal high-speed translation and indexing mechanism 13. In the case of task switching, the page base pointer 9 of the real address is obtained from the task switching dedicated high-speed conversion indexing mechanism 12. If there is no data matching the virtual address 1 in the high-speed translation index buffer 12 or 13, the real address 11 is obtained from the dynamic address translator 2 which has been activated at the same time. The virtual address 1 and the page base pointer 9 of the real address obtained here are stored in the high-speed translation index buffer 12 or
Set to. This setting method is performed by the LRU method.

〔The invention's effect〕

As described above, the present invention has a presettable high-speed conversion index buffering mechanism dedicated to task switching and an input / output port to the high-speed conversion index buffering mechanism. The address of the program resident in the operating system can be set in the high-speed index buffer, and the high-speed index buffer for task switching is rewritten every time a page is changed. When the task is switched, the probability that the real address of the task is registered in the high-speed translation look-up buffer mechanism is increased, so that the task switching time can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a layout diagram showing a configuration of an address space, and FIG. 3 is a block diagram of an example of a conventional information processing apparatus. 1 virtual address 2 dynamic address translation mechanism 3
... section ID, 4 ... area table register pair, 5 ... area ID, 6 ... area table, 7 ... page ID, 8 ... page table, 9 ... real address page base pointer, 10 ... page Offset address,
11: real address, 12: high-speed conversion index buffer mechanism dedicated to task switching, 13, 13a: high-speed conversion index buffer mechanism, 14: task switching control circuit, 15: task switching signal, 16: input / output port , A ... virtual space, B ... section, C ...
Area, D ... page.

Continuation of front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 12/10

Claims (1)

(57) [Claims] 1. A first high-speed conversion index buffer which is normally accessed, and a position of a task necessary for task switching and an address of an OS-resident program which are provided separately from the first high-speed conversion index buffer are provided in advance. An information processing apparatus comprising: a second high-speed conversion index buffer mechanism dedicated to task switching that can be set; and an input / output port to the first and second high-speed conversion index buffer mechanisms.