JPH05335320A - Silicon semiconductor substrate and manufacture thereof - Google Patents

Silicon semiconductor substrate and manufacture thereof

Info

Publication number
JPH05335320A
JPH05335320A JP14381992A JP14381992A JPH05335320A JP H05335320 A JPH05335320 A JP H05335320A JP 14381992 A JP14381992 A JP 14381992A JP 14381992 A JP14381992 A JP 14381992A JP H05335320 A JPH05335320 A JP H05335320A
Authority
JP
Japan
Prior art keywords
semiconductor substrate
silicon semiconductor
ions
carbon
ion implantation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP14381992A
Other languages
Japanese (ja)
Inventor
Kazunori Ishizaka
和紀 石坂
Tsuneo Nakashizu
恒夫 中静
Jun Sasaki
純 佐々木
Kenji Sugiyama
賢司 杉山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Steel Corp
Original Assignee
Nippon Steel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Steel Corp filed Critical Nippon Steel Corp
Priority to JP14381992A priority Critical patent/JPH05335320A/en
Publication of JPH05335320A publication Critical patent/JPH05335320A/en
Withdrawn legal-status Critical Current

Links

Abstract

PURPOSE:To impart an effect of eliminating heavy metal impurities mixed in the manufacturing process of a semiconductor integrated circuit. CONSTITUTION:Carbon ions of more than 1X10<14> ions/cm<2> are implanted in the rear side of a silicon semiconductor substrate, and the semiconductor substrate forms crystal defects of more than 1X10<5> pieces/cm on the rear of the silicon semiconductor substrate by heat treatment of oxidizing atmosphere. On the basis of the defects generated at the time of ion implantation, secondary defects are generated by oxidizing heat treatment. By utilizing the rear of the semiconductor substrate as a gettering site, a gettering wafer can be manufactured with higher productivity than that of the conventional technology in which an ion-implantation layer is used as the gettering site.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、集積回路などの半導体
デバイス製造に用いられるシリコン半導体基板に関する
ものである。特に、本発明はデバイス製造中に受ける重
金属不純物をシリコン基板内のデバイス領域から除去す
る効果を有するシリコン半導体基板およびその製造方法
に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a silicon semiconductor substrate used for manufacturing semiconductor devices such as integrated circuits. In particular, the present invention relates to a silicon semiconductor substrate having an effect of removing heavy metal impurities received during device manufacturing from a device region in a silicon substrate, and a manufacturing method thereof.

【0002】[0002]

【従来の技術】集積回路の高集積化に伴い、ダイナミッ
クメモリ(DRAM)において微少リーク電流の減少は
重要課題となっている。この微小リーク電流は半導体集
積回路製造中に混入する鉄、ニッケル、銅に代表される
重金属不純物に起因する。
2. Description of the Related Art With the high integration of integrated circuits, reduction of a minute leak current in a dynamic memory (DRAM) has become an important issue. This minute leak current is caused by heavy metal impurities represented by iron, nickel, and copper that are mixed in during the manufacture of semiconductor integrated circuits.

【0003】この重金属不純物を除去するためにゲッタ
リング法が用いられる。このゲッタリング法には炭素イ
オンをイオン注入する方法が公知である(特開昭58−
93334、特開昭62−235741、Appl. Phys.
Lett. Vol. 52,889(1988)、Appl. Phys. Lett. Vol. 5
7,798 (1988)。
A gettering method is used to remove the heavy metal impurities. As this gettering method, a method of implanting carbon ions is known (Japanese Patent Laid-Open No. 58-58-58).
93334, JP-A-62-235741, Appl. Phys.
Lett. Vol. 52,889 (1988), Appl. Phys. Lett. Vol. 5
7,798 (1988).

【0004】特開昭58−93334では、シリコン半
導体基板の表面または裏面の全面または一部に1017
cm3 を越えるピーク濃度で炭素イオンを注入する。炭
素を注入した領域をゲッタリングサイトとしている。
In Japanese Patent Application Laid-Open No. 58-93334, a total of 10 17 / s of the front surface or the back surface of a silicon semiconductor substrate is partially or completely formed.
Carbon ions are implanted at a peak concentration exceeding cm 3 . The region where carbon is injected is used as the gettering site.

【0005】特開昭62−235741では、シリコン
半導体基板裏面に炭素を含んだシリコン単結晶を形成す
る。炭素を含む領域をゲッタリングサイトとしている。
In Japanese Patent Laid-Open No. 62-235741, a silicon single crystal containing carbon is formed on the back surface of a silicon semiconductor substrate. The gettering site is a region containing carbon.

【0006】Appl. Phys. Lett. Vol. 52, 889(1988)お
よびAppl. Phys. Lett. Vol. 57,798 (1988)では、イオ
ン注入した炭素を含む領域では結晶欠陥が形成され、金
および銅のゲッタリングサイトとなっていることが明ら
かにされている。
[0006] Appl. Phys. Lett. Vol. 52, 889 (1988) and Appl. Phys. Lett. It has been revealed that it has become a gettering site.

【0007】[0007]

【発明が解決しようとする課題】炭素イオン注入法は、
室温でイオン注入を行うことができ、イオン注入域から
のパーティクルの発生による副作用もない。しかしなが
ら低エネルギーでイオン注入した場合、炭素イオン注入
領域が浅く、炭素イオン注入領域をゲッタリングサイト
とする方法では、酸化熱処理工程において炭素イオン注
入領域が酸化膜中に取り込まれることによりゲッタリン
グサイトがなくなる問題点がある。この問題を解決する
ために、裏面の炭素イオン注入領域に窒化シリコン膜や
シリコン酸化膜などの酸化されない保護膜を形成して保
護するか、炭素イオンの注入エネルギーを大きくして炭
素イオン注入領域を表面より深い領域に形成し、酸化熱
処理によっても取り込まれないようにしている。裏面に
非酸化性膜を形成する方法は、余分なプロセスを含み生
産性が悪い。高エネルギーで炭素イオンを注入する方法
は注入装置が大型になり生産性が悪い。本発明は、生産
性よく高いゲッタリング能力を有するシリコン半導体基
板およびその製造方法を提供することにある。
The carbon ion implantation method is
Ion implantation can be performed at room temperature, and there is no side effect due to generation of particles from the ion implantation region. However, when the ion implantation is performed with low energy, the carbon ion implantation region is shallow, and in the method of using the carbon ion implantation region as the gettering site, the gettering site is formed by incorporating the carbon ion implantation region into the oxide film in the oxidation heat treatment step. There is a problem that disappears. In order to solve this problem, a protective film that is not oxidized such as a silicon nitride film or a silicon oxide film is formed on the back surface of the carbon ion implantation area to protect it, or the carbon ion implantation energy is increased to increase the carbon ion implantation area. It is formed in a region deeper than the surface so that it is not taken in even by an oxidative heat treatment. The method of forming the non-oxidizing film on the back surface includes an extra process and has poor productivity. The method of implanting carbon ions with high energy requires a large-sized implanter, resulting in poor productivity. It is an object of the present invention to provide a silicon semiconductor substrate having high productivity and high gettering ability, and a method for manufacturing the same.

【0008】[0008]

【課題を解決するための手段】上記課題は、シリコン半
導体基板の裏面にイオン注入により導入された炭素およ
び酸化誘起結晶欠陥を有するシリコン半導体基板により
達成される。
The above object can be achieved by a silicon semiconductor substrate having carbon and oxidation-induced crystal defects introduced by ion implantation into the back surface of the silicon semiconductor substrate.

【0009】上記課題は、シリコン半導体基板の裏面に
炭素をイオン注入した後、酸化性雰囲気にて熱処理を行
い、イオン注入により導入した炭素およびイオン注入に
より生じた欠陥を核に酸化誘起結晶欠陥を形成すること
により達成される。
The above problem is that after carbon is ion-implanted into the back surface of the silicon semiconductor substrate, heat treatment is performed in an oxidizing atmosphere, and the carbon introduced by the ion implantation and the defects caused by the ion implantation serve as nuclei for the oxidation-induced crystal defects. It is achieved by forming.

【0010】[0010]

【作用】本発明によるシリコン基板は、シリコン半導体
基板と該基板の裏面に、1×1014イオン/cm2 以上
の炭素イオンを注入し、注入した炭素およびイオン注入
により生じた欠陥を核とする1×105 個/cm2 以上
の酸化誘起結晶欠陥が形成されているシリコン半導体基
板である。シリコン半導体基板の裏面に炭素イオンを1
×1014イオン/cm2 以上注入する。このシリコン半
導体基板を酸素ガスを含むガス雰囲気または水蒸気を含
むガス雰囲気にて800℃以上の温度で熱処理を行い、
注入された炭素とイオン注入により生じた欠陥を核とす
る1×105 個/cm2 以上の酸化誘起結晶欠陥を形成
する。シリコンを酸化性雰囲気で熱処理を行った場合、
シリコン半導体基板内に格子間シリコンが注入され、格
子間シリコンの濃度が熱平衡濃度よりも多く過飽和状態
になる。シリコン半導体基板表面に炭素原子による格子
歪やイオン注入により形成された微小な結晶欠陥が存在
する場合には、そのような欠陥を核に酸化誘起結晶欠陥
が形成され有効なゲッタリングサイトになる。格子間シ
リコンの注入にはシリコンの酸化熱処理が必須である。
In the silicon substrate according to the present invention, carbon ions of 1 × 10 14 ions / cm 2 or more are implanted into the silicon semiconductor substrate and the back surface of the substrate, and the implanted carbon and the defects caused by the ion implantation serve as nuclei. The silicon semiconductor substrate has 1 × 10 5 / cm 2 or more oxidation-induced crystal defects. 1 carbon ion on the back surface of silicon semiconductor substrate
× 10 14 ions / cm 2 or more is implanted. This silicon semiconductor substrate is heat-treated at a temperature of 800 ° C. or higher in a gas atmosphere containing oxygen gas or a gas atmosphere containing water vapor,
Oxidation-induced crystal defects of 1 × 10 5 / cm 2 or more are formed with the implanted carbon and the defects generated by the ion implantation as nuclei. When heat-treating silicon in an oxidizing atmosphere,
Interstitial silicon is injected into the silicon semiconductor substrate, and the concentration of interstitial silicon becomes higher than the thermal equilibrium concentration and becomes supersaturated. In the case where a lattice strain due to carbon atoms or minute crystal defects formed by ion implantation exist on the surface of the silicon semiconductor substrate, oxidation-induced crystal defects are formed with such defects as nuclei, and become effective gettering sites. Oxidation heat treatment of silicon is essential for implanting interstitial silicon.

【0011】シリコン半導体基板の裏面に炭素イオンを
1×1014イオン/cm2 よりも少ない注入量で注入し
た場合、1×105 個/cm2 未満の酸化誘起結晶欠陥
しか形成されず、ゲッタリング能力は弱い。
When carbon ions are implanted into the back surface of the silicon semiconductor substrate at a dose of less than 1 × 10 14 ions / cm 2, only less than 1 × 10 5 / cm 2 of oxidation-induced crystal defects are formed, and the getter is used. Ring ability is weak.

【0012】[0012]

【実施例】つぎに実施例を挙げて本発明を詳細に説明す
る。
EXAMPLES Next, the present invention will be described in detail with reference to examples.

【0013】シリコン半導体基板の裏面に炭素イオンを
面方位(100)に対して、真空アーク放電型イオン発
生装置を用いて発生させた炭素イオンビームを7度傾け
た条件で、加速電圧40keV、ドーズ量1×1013
オン/cm2 、1×1014イオン/cm2 、1×1015
イオン/cm2 、1×1016イオン/cm2 、1×10
17イオン/cm2 のイオン注入を行った。このようにイ
オン注入を行った基板に、1100℃にて水蒸気ガス雰
囲気にて1時間熱処理を行い、その後、熱処理によって
形成された酸化膜を弗酸を含む水溶液にて除去した。
Under the condition that the carbon ion beam generated by using the vacuum arc discharge type ion generator is tilted by 7 degrees with respect to the plane orientation (100) on the back surface of the silicon semiconductor substrate, the acceleration voltage is 40 keV and the dose is. Amount 1 × 10 13 ions / cm 2 , 1 × 10 14 ions / cm 2 , 1 × 10 15
Ions / cm 2 , 1 × 10 16 ions / cm 2 , 1 × 10
Ion implantation of 17 ions / cm 2 was performed. The ion-implanted substrate was heat-treated at 1100 ° C. in a steam gas atmosphere for 1 hour, and then the oxide film formed by the heat treatment was removed with an aqueous solution containing hydrofluoric acid.

【0014】このシリコン基板をライトエッチング液に
て選択エッチングを行い、イオン注入面を光学顕微鏡に
て観察を行い評価した。表1に結果を示す。イオン注入
に伴い酸化誘起結晶欠陥が発生している。
This silicon substrate was selectively etched with a light etching solution, and the ion-implanted surface was observed and evaluated with an optical microscope. The results are shown in Table 1. Oxidation-induced crystal defects are generated along with the ion implantation.

【0015】[0015]

【表1】 [Table 1]

【0016】次に上述のシリコン半導体基板のゲッタリ
ング能力を、銅で意図的に汚染し、銅の拡散熱処理後、
酸化誘起結晶欠陥に捕獲された銅の量を原子吸光法によ
り分析し、銅の回収率により評価した。銅の故意汚染
は、シリコン基板を回転させ、その基板表面上に銅を含
む水溶液を滴下することにより行った。本方法では均一
に基板上に付着させることができる。
Next, the gettering ability of the above-mentioned silicon semiconductor substrate is intentionally contaminated with copper, and after the diffusion heat treatment of copper,
The amount of copper captured by the oxidation-induced crystal defects was analyzed by an atomic absorption method and evaluated by the copper recovery rate. The intentional contamination of copper was performed by rotating a silicon substrate and dropping an aqueous solution containing copper onto the surface of the substrate. According to this method, it is possible to uniformly attach the substrate.

【0017】銅の初期表面汚染量は1×1014イオン/
cm2 である。汚染後拡散処理条件は、1000℃、2
5分窒素雰囲気である。注入面にゲッタリングされた銅
の量は注入面から10μmを弗酸と硝酸の混酸で溶解
し、本溶液の銅濃度を原子吸光法により分析し求めた。
表2にその結果を示す。銅の回収率が90%を越えた場
合を十分なゲッタリング効果があるとみなす。表2から
明らかなように、炭素イオン注入量が1×1014/cm
2 以上のものが良好なゲッタリング効果のあることが分
かる。
The initial surface contamination amount of copper is 1 × 10 14 ions /
cm 2 . Post-contamination diffusion treatment conditions are 1000 ° C,
5 minutes nitrogen atmosphere. The amount of copper gettered on the injection surface was determined by dissolving 10 μm from the injection surface with a mixed acid of hydrofluoric acid and nitric acid, and analyzing the copper concentration of this solution by an atomic absorption method.
The results are shown in Table 2. A case where the copper recovery rate exceeds 90% is considered to have a sufficient gettering effect. As is clear from Table 2, the carbon ion implantation amount is 1 × 10 14 / cm 3.
It can be seen that two or more have a good gettering effect.

【0018】[0018]

【表2】 [Table 2]

【0019】[0019]

【発明の効果】以上述べたように、本発明は、注入され
た炭素とイオン注入により生じた欠陥を核に酸化熱処理
により2次欠陥である酸化誘起結晶欠陥を生じさせ、そ
こをゲッタリングサイトとして利用していることによ
り、イオン注入エネルギーがという低エネルギーであっ
ても、炭素イオン注入層自体をゲッタリングサイトとし
て利用している従来技術のように、炭素イオン注入後、
非酸化性膜を形成するなどの余分なプロセスを必要とせ
ず、良好なゲッタリング能力をシリコン基板に付与でき
るため、生産性の著しい改善を行うことができる。
As described above, according to the present invention, the oxidation-induced crystal defects, which are the secondary defects, are generated by the oxidation heat treatment using the implanted carbon and the defects generated by the ion implantation as the nuclei, and the gettering sites are generated there. Therefore, even if the ion implantation energy is as low as that, as in the prior art in which the carbon ion implantation layer itself is used as a gettering site, after the carbon ion implantation,
Since a good gettering ability can be imparted to the silicon substrate without requiring an extra process such as forming a non-oxidizing film, the productivity can be remarkably improved.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 杉山 賢司 神奈川県相模原市淵野辺5−10−1 新日 本製鐵株式会社エレクトロニクス研究所内 ─────────────────────────────────────────────────── ─── Continued front page (72) Inventor Kenji Sugiyama 5-10-1, Fuchinobe, Sagamihara-shi, Kanagawa Nippon Steel Corporation Electronics Research Laboratory

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 シリコン半導体基板と該基板の裏面に、
1×1014イオン/cm2 以上の炭素イオンと1×10
5 個/cm2 以上の酸化誘起結晶欠陥が形成されている
ことを特徴とするシリコン半導体基板。
1. A silicon semiconductor substrate and a back surface of the substrate,
1 × 10 carbon ions of 1 × 10 14 ions / cm 2 or more
A silicon semiconductor substrate having 5 or more oxidation-induced crystal defects formed per cm 2 .
【請求項2】 シリコン半導体基板の裏面に、1×10
14イオン/cm2 以上の炭素イオンを注入し、酸化性雰
囲気を含む熱処理を行うことによりシリコン半導体基板
裏面に1×105 個/cm2 以上の酸化誘起結晶欠陥を
形成することを特徴とするシリコン半導体基板の製造方
法。
2. The back surface of the silicon semiconductor substrate is 1 × 10.
It is characterized by forming 14 × 10 5 / cm 2 or more oxidation-induced crystal defects on the back surface of a silicon semiconductor substrate by implanting 14 ions / cm 2 or more of carbon ions and performing a heat treatment containing an oxidizing atmosphere. Manufacturing method of silicon semiconductor substrate.
JP14381992A 1992-06-04 1992-06-04 Silicon semiconductor substrate and manufacture thereof Withdrawn JPH05335320A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14381992A JPH05335320A (en) 1992-06-04 1992-06-04 Silicon semiconductor substrate and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14381992A JPH05335320A (en) 1992-06-04 1992-06-04 Silicon semiconductor substrate and manufacture thereof

Publications (1)

Publication Number Publication Date
JPH05335320A true JPH05335320A (en) 1993-12-17

Family

ID=15347698

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14381992A Withdrawn JPH05335320A (en) 1992-06-04 1992-06-04 Silicon semiconductor substrate and manufacture thereof

Country Status (1)

Country Link
JP (1) JPH05335320A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19980060633A (en) * 1996-12-31 1998-10-07 김영환 Semiconductor Wafer Manufacturing Method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19980060633A (en) * 1996-12-31 1998-10-07 김영환 Semiconductor Wafer Manufacturing Method

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Effective date: 19990831