JPH053303A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To enhance the integration of a semiconductor integrated circuit provided with a NOR type mask ROM of the cross point cell structure and increase the information readout rate. CONSTITUTION:In a semiconductor integrated circuit provided with a NOR type mask ROM of the cross point structure, the gate electrode 6 of one of adjacent memory cells QE in a memory cell array is formed in one gate layer; and the gate electrode 10 of the other of adjacent memory calls QE in the same array is formed in another gate layer. In addition, the gate electrodes 6 and 10 are partially overlapped.

Description

Detailed Description of the Invention

[0001]

The present invention relates to relates to a semiconductor integrated circuit device, particularly to a technique effectively applied to a semiconductor integrated circuit device including a mask ROM (R ead O nly M emory ).

[0002]

2. Description of the Related Art As a mask ROM mounted on a semiconductor integrated circuit device such as a microprocessor or a gate array,
A NOR type (horizontal type) mask ROM that employs a so-called cross-point cell structure capable of high-speed read operation has been reported. For example, Sharp Technical Report, "Large-capacity 16Mb CM
OS Mask ROM ", Volume 40, 1988, 71st
Pages 75 to 75.

In a mask ROM adopting a cross point cell structure, a plurality of MOSFETs (for example, 16) are arranged in the gate width direction, and a plurality of MOSFs arranged in this arrangement.
The source regions (diffusion layers) of the ETs and the drain regions are electrically connected to each other. The plurality of arranged MOSFETs each store 1 [bit] of information. In other words, in the mask ROM adopting the cross-point cell structure, the bit line and the source line formed in the semiconductor region are arranged so as to be separated from each other and extend substantially in parallel in the same direction. A plurality of word lines that cross each of the bit lines and the source lines are arranged in the extending direction of the bit lines and the source lines.

The MOSFET, which is the memory cell, is of n-channel conductivity type and has a drain region (bit line),
Each of the source regions (source lines) is composed of an n-type semiconductor region. The gate electrode (word line) of the MOSFET adopts a single-layer gate structure, and has a plurality of arranged MOSFs.
The respective gate electrodes of the ET are separated from each other by a predetermined distance.

In the array of the plurality of memory cells, the first-stage memory cell is connected to the main bit line through the select MOSFET, and the last-stage memory cell is connected to the virtual source line through the select MOSFET. Connected.
Each of the main bit line and the virtual source line is formed of an aluminum alloy film of the same conductive layer arranged above the word line connected to the memory cell. This main bit line,
Each of the virtual source lines extends in the same direction as the arrangement direction of the plurality of memory cells, is arranged alternately in the extending direction of the word lines, and crosses over some of the arranged memory cells.

A mask ROM adopting this cross-point cell structure is a memory cell which is a memory cell for all memory cells.
The threshold voltage is set so that the FET becomes conductive when the word line is selected, and the threshold voltage of the MOSFET, which is a predetermined number of memory cells, does not become conductive even when the word line is selected. As a result, the information is written.

The information read operation is performed as follows.

First, a current flows from the selected main bit line to the bit line (n-type semiconductor region) through the select MOSFET. Next, when a memory cell is selected and the memory cell becomes conductive, the current flowing in the bit line flows in the source line and the virtual source line through the selected memory cell. This change in the amount of current is detected by the sense amplifier circuit connected to the selected main bit line,
Information 1 of the selected memory cell is determined.

Further, if the memory cell is not turned on even if it is selected, the current flowing through the bit line does not flow through the selected memory cell to the source line and the virtual source line. In this case, since the amount of current does not change, the information 0 of the memory cell is determined in the sense amplifier circuit.

The NOR type mask ROM adopting the cross point cell structure configured as described above has the following features.

(A) Since the connection between the memory cell and each of the main bit line and the virtual source line is made for each of a plurality of arranged memory cells, the area occupied by the connection region is reduced and the mask ROM The degree of integration can be improved. Since the mask ROM adopting the cross point cell structure is similar to the memory cell array of the NAND type (vertical) mask ROM,
An integration degree close to that of the NAND type mask ROM can be obtained.

(B) Memory cells are connected in parallel between a bit line and a source line (both of which are n-type semiconductor regions), and a plurality of memory cells arranged in an information read current path all have a series resistance (channel). Since the resistance of the region is not added as the main component), the information read operation speed of the mask ROM is high.

(C) Since the MOSFET as the memory cell has the single-layer gate structure, the number of steps in the mask ROM manufacturing process can be reduced. As a result, the mask ROM
The product cost can be reduced.

[0014]

However, the mask ROM employing the above-mentioned cross-point cell structure does not consider the following points.

(A) Since the mask ROM adopting the above-mentioned cross-point cell structure has a single-layer gate structure, a plurality of arranged memory cells are provided between adjacent memory cells.
Specifically, the gate electrodes (corresponding to word lines) are separated from each other for the purpose of electrical separation. The distance between the gate electrodes corresponds to, for example, the minimum resolution (processing size) of the photolithography technique used in the manufacturing process. Therefore, by the amount corresponding to the distance between the memory cells,
The integration density of the mask ROM is reduced.

(B) The above-mentioned distance between the memory cells simultaneously increases the lengths of the bit line and the source line (both n-type semiconductor regions). Therefore, a resistance (diffusion layer resistance) and a parasitic capacitance (mainly a pn junction capacitance formed with the substrate) are added to the bit line and the source line (both of which are information read current paths). The information read operation speed decreases.

(C) Both the main bit line and the virtual source line extend above the memory cell. A thick insulating film corresponding to the field insulating film is not basically formed between the plurality of arranged memory cells, and the information read operation speed is increased (parasitic capacitance is reduced). For the purpose, the threshold voltage of the parasitic MOS cannot be so high.
Therefore, based on the field effect from the selected main bit line or the selected virtual source line, the selected memory cell arranged in the lower layer and the non-selected memory cell adjacent thereto are short-circuited. To do. That is, the mask RO
Since a malfunction occurs in the information read operation of M,
Operation reliability is reduced.

An object of the present invention is to provide a technique capable of increasing the degree of integration and increasing the information read operation speed in a semiconductor integrated circuit device equipped with a NOR type mask ROM. .

Another object of the present invention is to provide a technique capable of achieving the above object and improving the operation reliability in a semiconductor integrated circuit device equipped with the NOR type mask ROM.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0021]

Among the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

(1) A plurality of MISFETs are arranged in the gate width direction, and the source region and the drain region of the MISFETs located adjacent to the front side and the rear side of this arrangement are electrically connected to each other. In a semiconductor integrated circuit device having a mask ROM adopting a NOR type structure, in which each of the plurality of MISFETs arranged in series is used as a memory cell for storing information.
Among a plurality of memory cells arranged in a mask ROM adopting the R-type structure, a gate electrode of one MISFET adjacent to each other in the arrangement direction is a gate electrode of another MISFET adjacent to each other in the arrangement direction. It is composed of a gate layer of a different layer with respect to the electrode and is overlapped with a part of the gate electrode of the MISFET which is the other memory cell.

(2) In the mask ROM adopting the NOR type structure of the above-mentioned means (1), all or a part of the memory cells arranged in a plural number are arranged in the first stage memory cell of the arrangement for selecting. A bit line connected via a MISFET or a virtual source line connected via a select MISFET is arranged in the last-stage memory cell of the array.

[0024]

According to the above-mentioned means (1), the following operational effects can be obtained.

(A) In the mask ROM adopting the NOR type structure (horizontal type structure), by adopting the two-layer gate structure, the distance between the memory cells adjacent in the arrangement direction can be eliminated, so that the degree of integration can be improved. .

(B) Due to the action and effect (1), the source line (diffusion layer wiring) connecting the source regions of the MISFETs, which are a plurality of memory cells in the array direction, and the bit line connecting the drain regions in the same manner. Since any wiring length of the (diffusion layer wiring) can be shortened and the parasitic resistance of each of the source line and the bit line and the parasitic capacitance formed between the wiring and the substrate can be reduced, a read current flows in the information read operation. The speed can be increased and the operation speed can be increased. Also, NOR
Since the mask ROM adopting the die structure has the memory cells connected in parallel between the source line and the bit line,
The operation speed can be increased as compared with the mask ROM adopting the NAND type structure (vertical type structure).

According to the above-mentioned means (2), by the means (1), there is substantially no element isolation region between the memory cells adjacent to each other in the arrangement direction (no open field exists), or Since the plurality of arranged memory cells and the space between the memory cells are covered with the gate electrode, the electric field effect from the main bit line or virtual source line on the memory cells is reduced, and the memory cells selected at the time of the information read operation It is possible to prevent a short circuit due to punch-through between adjacent non-selected memory cells and a malfunction of the information reading operation due to this short circuit.

The structure of the present invention will be described below with reference to an embodiment in which the present invention is applied to a semiconductor integrated circuit device having a NOR type mask ROM adopting a cross point cell structure.

In all the drawings for explaining the embodiments, those having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted.

[0030]

EXAMPLE A NOR type mask RO which is an example of the present invention
FIG. 1 (equivalent circuit diagram) shows the configuration of the NOR type mask ROM mounted on the M or semiconductor integrated circuit device.

As shown in FIG. 1, the NOR type (horizontal type) mask ROM is a memory cell Q _E for storing 1 [bit] information.
Is an n-channel MISFET. Memory cell Q
_A plurality of _Es are electrically connected and arranged in parallel in the gate width direction (vertical direction in FIG. 1) of the n-channel MISFET to form a memory cell column. Although not limited to this array number, 16 (16 [bi
A memory cell Q _{E (} of information [t]) is arranged. A plurality of memory cell columns are arranged in the vertical and horizontal directions,
A memory cell array (memory cell mat) is configured.

In each of the memory cells Q _E of the memory cell column, the drain regions of the n-channel MISFETs adjacent in the array direction are electrically connected to each other, and the drain regions connected to each other are arranged in the memory cell column. Configure the bit line. Further, in each of the memory cells Q _E of the memory cell column, the source regions of the n-channel MISFETs adjacent in the array direction are electrically connected to each other, and the source regions connected to each other form a source line in the memory cell column. Constitute. Both the bit line and the source line are separated from each other along the arrangement direction of the memory cells Q _E of the memory cell column and extend substantially parallel to the arrangement direction.

The word line W is formed on each gate electrode of the n-channel MISFET which is the memory cell Q _E of the memory cell column.
L is connected. The word line intersects with the array direction of the memory cells Q _E of the memory cell column (in FIG. 1,
A plurality of them are arranged in the arrangement direction.

The memory cell Q _E (bit line) located at the first stage of the array of memory cell columns is an n-channel MI for selection.
It is electrically connected to the main bit line BL through the SFETQ _S1 . The memory cell Q _E located at the final stage of the array of memory cell columns is an n-channel MIS for selection.
It is connected to the same main bit line BL via the FET Q _S2 . The main bit line BL is connected to the sense amplifier circuit SA.

The memory cell Q _E (source line) located at the first stage of the arrangement of another memory cell column adjacent to the memory cell column connected to the main bit line BL in the horizontal direction or in the vertical direction is , Select n-channel MISFE
It is connected to the virtual source line SL via TQ _S1 . Further, the memory cells Q _E located at the final stage of the array of memory cell columns are connected to the same virtual source line SL through the n-channel MISFET for selection Q _S2 . The virtual source line SL is connected to the ground power supply GND through the switch n-channel MISFET.

Of the plurality of memory cells Q _E arranged in the memory cell array, the memory cell Q _E1 set to the threshold voltage which becomes conductive when the selection signal is applied to the word line WL is, for example, Information 1 is stored. Further, for example, information 0 is stored in the memory cell Q _E2 set to the threshold voltage, which becomes non-conductive when the selection signal is applied to the word line WL.

Next, the specific structure of the NOR-type mask ROM will be briefly described with reference to FIGS. 2 (plan view of relevant parts) and 3 (cross-sectional view taken along the line AA of FIG. 2). explain.

As shown in FIGS. 2 and 3, the NOR mask ROM or the NOR mask ROM mounted on the semiconductor integrated circuit device is a p--type semiconductor substrate 1 made of single crystal silicon.
It is composed mainly of.

Memory cells Q _E arranged in a memory cell column
Among them, the memory cells Q _E arranged in even-numbered stages from the first stage to the last stage of the array are formed on the main surface of the p − type semiconductor substrate 1 (or p type well region). That is, the memory cells Q _E arranged in the even-numbered stages mainly include the gate insulating film 5, the gate electrode 6, and the pair of n + type semiconductor regions 3 used as the source region and the drain region.

The gate electrode 6 is a NOR type mask RO.
In the manufacturing process of M, it is formed in the first layer gate material forming step and is formed of, for example, a polycrystalline silicon film.

N which is each of the source region and the drain region
The + type semiconductor region 3 is formed on the main surface of the p − type semiconductor substrate 1, and an insulating film 2 having a thickness larger than that of the gate insulating film 5 is formed on the surface of the n + type semiconductor region 3 to form a word. Line (WL) 6 extends. The word line 6 connected to the gate electrode 6 of the n-channel MISFET which is the memory cell Q _E arranged in the even-numbered stages is formed of the same conductive layer as the gate electrode 6 and is integrally formed.

Memory cells Q _E arranged in a memory cell column
Among them, the memory cells Q _E arranged in odd stages from the first stage to the last stage of the array are similarly formed on the main surface of the p − type semiconductor substrate 1. That is, the memory cells Q _E arranged in the odd-numbered stages mainly include the gate insulating film 8, the gate electrode 10, and the pair of n + type semiconductor regions 3 used as the source region and the drain region.

The gate insulating film 8 and the gate electrode 10 are formed on the main surface of the p--type semiconductor substrate 1 along the side walls and bottom surfaces of the pores 7 formed in the depth direction from the main surface. To be done.

The gate electrode 10 is a NOR type mask R
In the OM manufacturing process, it is formed in the second layer gate material forming step, and is formed of, for example, a polycrystalline silicon film. In the present embodiment, the gate electrode 10 is partially overlapped with the gate electrode 6 of the n-channel MISFET which is the memory cell Q _E arranged in even stages. In other words, the gate electrodes 6 and 10 are arranged without a separation dimension therebetween (within a dimension smaller than the separation dimension between the gate electrodes 6). In other words, each of the even-numbered-stage memory cells Q _E and the odd-numbered-stage memory cells Q _E arranged in the memory cell column is
They are arranged close to each other without setting a separation dimension corresponding to the minimum processing dimension in the manufacturing process (minimum resolution in the photolithography technique).

The word line (WL) 10 connected to the gate electrode 10 of the n-channel MISFET which is the memory cell Q _E arranged in an odd number of stages is similarly formed of the same conductive layer as the gate electrode 10 and is integrally formed. Composed.

The memory cells Q _E arranged in the even-numbered stages described above.
Among them, the memory cell Q _E1 for storing the information 1 has a threshold voltage determined, for example, by the impurity concentration on the surface of the p − type semiconductor substrate 1 (actually the threshold voltage adjusting impurity is introduced). . The memory cell Q _E2 for storing the information 0 has, for example, a threshold voltage determined by the p-type semiconductor region 4 formed on the main surface of the p − -type semiconductor substrate 1.

In addition, the memory cells Q _E arranged in odd stages
Among them, the memory cell Q _E1 for storing the information 1 has, for example, the impurity concentration on the side wall and the bottom surface of the pore 7 of the p − type semiconductor substrate 1 having a threshold voltage (actually, the threshold voltage adjusting impurity is Will be introduced). The memory cell Q _E2 for storing information 0 has, for example, a p − -type semiconductor substrate 1 with a threshold voltage.
Is determined by the p-type semiconductor region 9 formed on the main surface of the pore 7.

The select n-channel MISFET Q _S1 arranged on the initial stage side of the memory cell column is formed on the main surface of the p − type semiconductor substrate 1, and has the gate insulating film 5 and the gate electrode 6.
The first layer gate material, the n + type semiconductor region 3 and the n + type semiconductor region 11 are mainly constituted. N for this select
In the n + type semiconductor region 11 of the channel MISFET Q _S1, the main bit line (BL) 14 or the virtual source line (S
L) 14 is connected. Main bit line 1
4. Each of the virtual source lines 14 extends on the interlayer insulating film 12 and is connected to the n + type semiconductor region 11 through the connection hole 13 formed in the interlayer insulating film 12. Each of the main bit line 14 and the virtual source line 14 is formed of the same conductive layer, for example, an aluminum alloy film.

The select n-channel MISFET Q _S2 arranged on the final stage side of the memory cell column is formed on the main surface of the p--type semiconductor substrate 1, and has the gate insulating film 8 and the gate electrode 10.
(Second layer gate material), n + type semiconductor region 3 and n + type semiconductor region 11 are mainly constituted. N for this select
In the n + type semiconductor region 11 of the channel MISFET Q _S2, the virtual source line (SL) 14 or the main bit line (B
L) 14 is connected.

Next, a method of manufacturing the NOR-type mask ROM described above will be briefly described with reference to FIGS. 4 to 11 (cross-sectional views of the essential part shown in each predetermined manufacturing process).

First, a p--type semiconductor substrate 1 made of single crystal silicon is prepared.

Next, a silicon oxide film 16 formed by a thermal oxidation method is formed on the entire main surface of the p--type semiconductor substrate 1, and the silicon oxide film 16 is formed in a region where a channel formation region is formed.
A silicon nitride film 17 is formed on top. This silicon nitride film 17 is used as an impurity introduction mask and an oxidation resistant mask, respectively.

Next, as shown in FIG. 4, using the silicon nitride film 17 as an impurity introduction mask, an n-type impurity 3N is introduced into the main surface portion of the p--type semiconductor substrate 1. The n-type impurity 3N is introduced into the main surface portion of the p − type semiconductor substrate 1 through the silicon oxide film 16 by using the ion implantation method.

Next, as shown in FIG. 5, using the silicon nitride film 17 as an oxidation resistant mask, p- in the formation regions of the source region and the drain region of the n-channel MISFET which is the memory cell Q _E. The thick insulating film 2 is formed on the main surface of the mold semiconductor substrate 1. Insulating film 2 is formed of a silicon oxide film formed by subjecting the main surface of p − type semiconductor substrate 1 to thermal oxidation. Along with the step of forming the insulating film 2, the n previously introduced on the lower side of the insulating film 2.
The type impurities 3N are diffused, and the source region, the drain region,
An n + type semiconductor region 3 used as either a bit line or a source line is formed.

Next, after removing the silicon nitride film 17,
Impurities for adjusting the threshold voltage are introduced into the entire main surface of the p-type semiconductor substrate 1. The threshold voltage adjusting impurities are introduced for the purpose of adjusting the threshold voltage of the memory cell Q _E storing the information 1.

Next, as shown in FIG. 6, of the memory cells Q _E arranged in even stages, the p-type impurity 4P is introduced into the region where the memory cell Q _E2 for storing information 0 is formed. This p-type impurity 4P is introduced by the ion implantation method using the impurity introduction mask 18 as shown by the dashed line in FIG.

Next, a gate insulating film 5 is formed on the main surface of the p--type semiconductor substrate 1 which will be a channel forming region, and thereafter,
As shown in FIG. 7, the gate electrode 6 is formed. The gate electrode 6 is patterned by anisotropic etching using an etching mask formed by a photolithography technique on the polycrystalline silicon film formed by the CVD method in the first layer gate material forming step of the manufacturing process. It is formed by applying. In the same step as the step of forming the gate electrode 6, the word line 6 and the n channel MISFET for selection are formed.
The gate electrode 6 of Q _S1 is also formed.

Further, the p-type impurity 4P introduced in advance is diffused, and the information 0 of the memory cells Q _E arranged in even-numbered stages is 0.
A p-type semiconductor region 4 is formed which determines the threshold voltage of the memory cell Q _E2 in which is stored.

By completing these steps, the memory cells Q _E arranged in even stages are completed.

Then, as shown in FIG. 8, the gate electrode 6 is used as a main body of the etching mask, and p- is formed in the channel formation region of the memory cells Q _E arranged in odd stages.
Pores 7 are formed in the main surface of the mold semiconductor substrate 1. This pore 7
Is formed by anisotropic etching, for example, and is formed in self-alignment with the gate electrode 6. When the pores 7 are formed, the n + type semiconductor region 3 used as any one of a drain region, a source region, a bit line, and a source line has an insulating film 2 with a thick film thickness formed on the n + type semiconductor region 3. Since this insulating film 2 serves as a stopper layer against etching, it is not etched.

Next, a silicon oxide film (not shown) is formed on the surface of the p--type semiconductor substrate 1 on the side wall and side surface of the pore 7. After that, in the formation region of the memory cells Q _E arranged in odd stages, the p-type semiconductor substrate 1 is formed.
A threshold voltage adjusting impurity for adjusting the threshold voltage of the memory cell Q _E1 for storing the information 1 is introduced into the main surface portion of.

Next, as shown in FIG. 9, of the memory cells Q _E arranged in odd stages, in the region where the memory cell Q _E2 for storing information 0 is formed, the p--type semiconductor substrate 1 is formed.
A p-type impurity 9P is introduced into the main surface portion of. p-type impurity 9P
9 is introduced by ion implantation using an impurity introduction mask 19 as shown in FIG.

Next, a gate insulating film 8 is formed on the main surface of the p − type semiconductor substrate 1 which will be a channel forming region on the side walls and bottom surface of the pores 7, and thereafter, as shown in FIG. The gate electrode 10 is formed. The gate electrode 10 is
In the second layer gate material forming step of the manufacturing process, C
The polycrystalline silicon film formed by the VD method is patterned by anisotropic etching using an etching mask formed by a photolithography technique. In the same step as the step of forming the gate electrode 10,
Word line 10, n channel MISFET for selection Q _S2
The gate electrode 10 is also formed.

Further, the p-type impurity 9P introduced in advance is diffused, and the information 0 of the memory cells Q _E arranged in odd stages is 0.
A p-type semiconductor region 9 that determines the threshold voltage of the memory cell Q _E2 in which is stored is formed.

By completing these steps, the memory cells Q _E arranged in odd stages are completed.

Next, the select n-channel MISF
The ETQ _S1 and the n + type semiconductor region 11 for the n-channel MISFET Q _S2 for selection are formed.

Next, the interlayer insulating film 12 and the connection hole 13 are sequentially formed, and then the main bit line 14 and the virtual source line 14 shown in FIGS. 2 and 3 are formed.

The NOR type mask ROM of the present embodiment is completed by performing these series of manufacturing processes.

Next, the information read operation of the NOR type mask ROM described above will be briefly described with reference to FIG.

First, the main bit line BL1 and the virtual source line SL1 are arranged at the intersections of the word lines WL2,
The case of reading information from memory cell Q _{E1 in} an even column (memory cell column) will be described.

Select n-channel MI on the first stage side of the array
The SFETQ _S1 is selected (made conductive), and the select n-channel MISFET Q _S2 on the final stage side is deselected (made nonconductive). Next, the word line WL2 is selected, the memory cell Q _E1 is selected (made conductive), and the other word lines WL are deselected. In this state, the information read current i1 is passed through each of the selected main bit line BL1, bit line, memory cell Q _E1 , source line, and selected virtual source line SL1, and the change amount of this information read current i1 is selected. The sense amplifier circuit SA connected to the selected main bit line BL1 detects. As a result, since the information read current i1 changes in the sense amplifier circuit SA, the information 1 stored in the memory cell Q _E1 is determined.

Next, the main bit line BL1 and the virtual source line SL1 are arranged at the intersections of the word lines WL2,
A case where the information in the memory cell Q _{E2 in} the odd column (memory cell column) is read will be described.

Select n-channel MI on the first stage side of the array
The SFETQ _S1 is deselected, and the final n-channel select n-channel MISFET Q _S2 is selected. Next, word line WL2
, The memory cell Q _E2 is selected, and other word lines WL are not selected. In this state, the information read current i2 is passed through each of the selected main bit line BL1, the bit line, and the memory cell Q _E2 , and the change amount of the information read current i2 is changed to the selected main bit line BL1.
It is detected by the sense amplifier circuit SA connected to. As a result, in the sense amplifier circuit SA, the information read current i
Since there is little change in 2, the information 0 stored in memory cell Q _E2 is determined.

In this way, a plurality of n-channel MISFs are
The ETs are arranged in the gate width direction, and both the source regions and the drain regions (n + type semiconductor regions 3) of the n-channel MISFETs adjacent to the front side and the rear side of the array are mutually connected. In a mask ROM having a NOR type structure or a semiconductor integrated circuit device including the same, which is electrically connected and each of the plurality of arranged n-channel MISFETs is used as a memory cell Q _E for storing information Mask ROM adopting the NOR type structure
Of a plurality arrayed memory cells Q _E, while adjacent to the arrangement direction (for example the even-numbered stage) gate electrode 6 of the n-channel MISFET is a memory cell Q _E is the other adjacent to the arrangement direction (e.g. together are composed of the gate layer of the different layers with respect to the gate electrode 10 of the n-channel MISFET is an odd stage) memory cells Q _E, part of the gate electrode 10 of the n-channel MISFET is this other memory cell Q _E Overlaid on. With this configuration, the N
In the mask ROM adopting the OR type structure, the memory cells Q adjacent in the array direction are adopted by adopting the two-layer gate structure.
_Since the separation dimension between _E can be eliminated, the degree of integration can be improved. In addition, n which is a plurality of memory cells Q _E in the array direction
The source line (n + type semiconductor region 3) connected to each source region of the channel MISFET and the bit line (n + type semiconductor region 3) similarly connected to the drain region can both have short wiring lengths. Since the parasitic resistance of each bit line and the parasitic capacitance formed between the bit line and the p-type semiconductor substrate 1 can be reduced, the read current flow speed can be increased and the operation speed can be increased in the information read operation. Further, in the mask ROM adopting the NOR type structure, since the memory cells Q _E are connected in parallel between the source line and the bit line, compared with the mask ROM adopting the NAND type structure (vertical type structure). The operating speed can be increased.

Further, on all or a part of the memory cells Q _E in which a plurality of mask ROMs adopting the NOR type structure are arranged, a select n-channel is provided for the memory cells Q _E in the first stage of the arrangement. An n-channel MISFET for selection is connected to the main bit line BL connected via the MISFET Q _S or the memory cell Q _E at the final stage of the array.
A virtual source line SL connected via Q _S is arranged. With this configuration, the memory cells Q adjacent in the array direction are
There is no substantial element isolation region between _E (no open field exists), and a plurality of memory cells Q are arranged.
_{Since the area} between _E and the memory cell Q _E is covered with the gate electrodes 6 and 10, the electric field effect from the main bit line BL or the virtual source line SL on the memory cell Q _E is reduced, and the memory cell selected during the information read operation. and Q _E, the malfunction of the information reading operation by a short circuit and the short circuit based on the punch-through between the non-selected memory cells Q _E adjacent thereto can be prevented.

As described above, the invention made by the present inventor is
Although the present invention has been specifically described based on the above-mentioned embodiments, the present invention is not limited to the above-mentioned embodiments, and it goes without saying that various modifications can be made without departing from the scope of the invention.

For example, according to the present invention, in a mask ROM adopting the NOR type structure, an n--type semiconductor substrate and a p-type well region formed in the main surface portion thereof are used instead of the p--type semiconductor substrate. Good.

In the mask ROM adopting the NOR type structure, the n-channel MI which is the memory cell Q _E is also used.
The gate electrode of the SFET is formed of a single layer of a refractory metal film or a refractory metal silicide film, or a laminated film in which a refractory metal film or a refractory metal silicide film is laminated on a polycrystalline silicon film. May be.

[0079]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

In the semiconductor integrated circuit device provided with the NOR type mask ROM, high integration can be achieved and information read operation speed can be increased.

In the semiconductor integrated circuit device equipped with the NOR type mask ROM, the operation reliability can be improved.

[Brief description of drawings]

FIG. 1 is a NOR type mask ROM according to an embodiment of the present invention.
Alternatively, a NOR type mask R mounted on a semiconductor integrated circuit device
The equivalent circuit diagram which shows the structure of OM.

FIG. 2 is a plan view of an essential part of the NOR type mask ROM.

FIG. 3 is a sectional view of an essential part of the NOR type mask ROM.

FIG. 4 is a sectional view of a principal portion in a first step showing the NOR mask ROM in each manufacturing step.

FIG. 5 is a sectional view of a main part in a second step.

FIG. 6 is a sectional view of a main part in a third step.

FIG. 7 is a sectional view of an essential part in a fourth step.

FIG. 8 is a sectional view of an essential part in a fifth step.

FIG. 9 is a sectional view of an essential part in a sixth step.

FIG. 10 is a sectional view of an essential part in a seventh step.

FIG. 11 is a sectional view of an essential part in an eighth step.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... Insulating film, 3, 4, 9, 11 ... Semiconductor region, 5, 8 ... Gate insulating film, 6, 10 ... Gate electrode or word line, 7 ... Pore, 14 ... Main bit line or Virtual source line, Q _E ... Memory cell, WL ... Word line, BL
... main bit line, SL ... virtual source line.

Claims (2)

[Claims] 1. A plurality of MISFETs are arranged in the gate width direction, and the source regions and the drain regions of the MISFETs located adjacent to the front side and the rear side of the arrangement are electrically connected to each other. And a mask RO that is connected to a plurality of MISFETs and is used as a memory cell for storing information.
In the semiconductor integrated circuit device having M, the gate electrode of the MISFET, which is one of the memory cells arranged in the mask ROM adopting the NOR type structure and adjacent in the array direction, is arranged in the array direction. A semiconductor integrated circuit characterized by being constituted by a gate layer of a different layer from the gate electrode of the MISFET which is the other adjacent memory cell and being overlapped with a part of the gate electrode of the MISFET which is the other memory cell. Circuit device. 2. A mask ROM adopting the NOR type structure according to claim 1, wherein all or a part of a plurality of memory cells arranged in a mask ROM are used for selecting a memory cell at a first stage of the arrangement. A semiconductor integrated circuit device characterized in that a bit line connected via a MISFET or a virtual source line connected via a select MISFET is arranged in a memory cell at the final stage of the array.