JP3194759B2 - Method for forming semiconductor integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit device.
In particular, an electrically erasable nonvolatile memory circuit (EEPR)
OM:ElectricallyErasableProgrammableRead
OnlyMemory)
And effective technology.

[0002]

2. Description of the Related Art An EEPROM having a memory cell having a structure optimal for high integration is reported in the following literature. IEEE Journal of Solid-State Circuit
s, Vol sc-22, No. 5, October 1987, pp. 6
76-683.

The memory cell of the EEPROM reported in this document is arranged between a data line and a source line, and is composed of a series connection circuit of an information storage field effect transistor and a cell selection field effect transistor.

[0004] The information storage field effect transistor has a charge storage gate electrode (floating gate electrode) and a control gate electrode (control gate electrode) disposed thereon. The EEPROM employs a two-layer gate structure, wherein the charge storage gate electrode is formed of a first-layer gate material forming step, for example, a polycrystalline silicon film in a manufacturing process, and the control gate electrode is formed of a second-layer gate material forming step, for example, a polycrystalline silicon film. It is formed of a crystalline silicon film. The information storage field effect transistor has a semiconductor region corresponding to a drain region,
Through this semiconductor region, it is electrically connected to a data line.

The cell selection field effect transistor has a selection gate electrode integrally formed with and electrically connected to the control gate electrode of the information storage field effect transistor, and has a source through a semiconductor region corresponding to the source region. Electrically connected to the wire. The select gate electrode is formed in the same manufacturing process as the control gate electrode, that is, in the second-layer gate material forming process.

The method of forming the memory cell is as follows.

First, a first gate insulating film of a field effect transistor for information storage and a charge storage gate electrode are sequentially formed on one main surface of a semiconductor substrate.

Next, a second gate insulating film is formed on the surface of the charge storage gate electrode, and a cell is formed on one main surface of the semiconductor substrate at a position adjacent to an end of the charge storage gate electrode in the gate length direction. A third gate insulating film of the selection field effect transistor is formed.

Next, a control gate electrode of the information storing field effect transistor is formed on the second gate insulating film, and a select gate electrode of the cell selecting field effect transistor is formed on the third gate insulating film. Each of the control gate electrode and the selection gate electrode is formed by depositing a polycrystalline silicon film by a CVD method and then patterning the polycrystalline silicon film by etching using an etching mask formed by a photolithography technique. I do. Anisotropic etching such as RIE is used for this patterning. When patterning the data line side of the control gate electrode in the gate length direction, the end of the lower charge storage gate electrode on the data line side is also so-called overlap-cut, so that the information storage field-effect transistor and the cell selection. The total gate length of the field effect transistor is made uniform in the plurality of memory cells.

Next, semiconductor regions corresponding to the drain region of the information storage field effect transistor and the source region of the cell selection field effect transistor are formed. This semiconductor region is formed by using a control gate electrode of the information storage field effect transistor and a selection gate electrode of the cell selection field effect transistor as an impurity introduction mask, and introducing an impurity by an ion implantation apparatus. The semiconductor region formed by this method can be formed by self-alignment with each of the control gate electrode and the select gate electrode.

The thus formed EEPROM memory cell reported in the above-mentioned document corresponds to a semiconductor region corresponding to a source region of a field effect transistor for information storage and a drain region of a field effect transistor for cell selection. Each of the semiconductor regions is abolished, and both channel forming regions are directly connected. That is, the area occupied by the memory cells can be reduced by an amount corresponding to the abolished semiconductor region, so that the integration density of the EEPROM can be improved.

[0012]

However, the above-mentioned EEPROM does not take the following points into consideration.

(1) The select gate electrode of the field effect transistor for cell selection of the EEPROM memory cell is patterned by photolithography and etching. Therefore, the select gate electrode varies from the charge storage gate electrode of the information storage field effect transistor by an amount corresponding to the mask alignment allowance in the manufacturing process. Dimensions vary.

(2) The charge storage gate electrode of the information storage field effect transistor of the EEPROM memory cell is re-patterned when the upper control gate electrode is patterned. In contrast to the first patterning of the charge storage gate electrode, the second patterning of the charge storage gate electrode overlapped with the control gate electrode has a variation corresponding to the mask alignment allowance. For this reason, the gate length dimension of the information storage field effect transistor varies.

(3) Based on the problem (1), the gate length of the cell-selecting field-effect transistor is increased by an amount corresponding to the mask alignment allowance, and information is stored based on the problem (2). Since the gate length dimension of the field effect transistor for use is increased by an amount corresponding to the margin for mask alignment, the occupied area of the memory cell increases,
The degree of integration is reduced.

(4) The variation in the gate length of the information storage field effect transistor is such that the capacitance or the like parasitically generated between the charge storage gate electrode and the control gate electrode differs in each of the plurality of memory cells. That means, EEPR
A change occurs in each of the information writing characteristic, the information erasing characteristic, and the information reading characteristic of the OM. For this reason, the characteristics of the EEPROM become unstable, and the electrical reliability is reduced.

The objects of the present invention are as follows.

(1) an information storage field effect transistor,
In a semiconductor integrated circuit device provided with an EEPROM in which each series connection circuit of cell selection field effect transistors is a memory cell, variations in the gate length of the cell selection field effect transistor of the memory cell are reduced.

(2) In the semiconductor integrated circuit device of the above-mentioned object (1), variations in the gate length of the information storage field effect transistor of the memory cell are reduced.

(3) The object (1) or the objects (1) and (2) are achieved, the area occupied by the memory cells is reduced, and the integration degree of the EEPROM, that is, the integration degree of the semiconductor integrated circuit device is improved. I do.

(4) In the semiconductor integrated circuit device of the above object (1), the operating characteristics of the EEPROM are stabilized,
Improve electrical reliability.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0023]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, typical ones will be briefly described as follows.

(1) An information storage field effect transistor having a charge storage gate electrode and a control gate electrode, adjacent to an end of the charge storage gate electrode in the gate length direction, and integrally formed with the control gate electrode. In an EEPROM equipped with an electrically erasable nonvolatile memory circuit in which each series connection circuit of cell selection field effect transistors having a selection gate electrode is used as a memory cell, a first gate insulating film is formed on one main surface of a semiconductor substrate. Forming a charge storage gate electrode of the information storage field effect transistor, and providing a drain of the information storage field effect transistor at one end of the charge storage gate electrode on one main surface of the semiconductor substrate in the gate length direction. Forming a first semiconductor region to be a region or a source region; and forming a first storage region on a main surface of the semiconductor substrate. Forming an impurity introduction mask at the other end in the gate length direction in a self-aligned manner with respect to the charge storage gate electrode; and using the impurity introduction mask, forming a charge accumulation gate electrode on one main surface of the semiconductor substrate. At the other end of
Forming a second semiconductor region to be a source region or a drain region of the cell selection field effect transistor, removing the impurity introduction mask, and thereafter forming a second gate insulating film on the charge storage gate electrode Along with
Forming a third gate insulating film in a region of the one main surface of the semiconductor substrate from which the impurity introduction mask has been removed; and forming a control gate electrode of an information storage field effect transistor on the second gate insulating film. together, and a third gate insulating film wherein Ru selection gate electrode shapes formed to <br/> the control gate electrode and the field-effect transistor cell selection is formed integrally on the process.

(2) The control gate electrode of the information storage field effect transistor of the means (1) is patterned in a separate step from the patterning step of the charge storage gate electrode in the gate length direction. .

[0026]

(3) The above-mentioned means (1) or means (2)
A memory cell formed by the method has a cross-point cell structure in which a control gate electrode of an information storage field-effect transistor is integrally formed with and electrically connected to a word line whose extending direction coincides with its gate length direction. It consists of.

[0028]

According to the above-mentioned means (1), the gate length (channel length) of the cell selection field effect transistor of the memory cell of the EEPROM is self-aligned with respect to the charge storage gate electrode of the information storage field effect transistor. Since it is defined by the impurity introduction mask formed by the alignment, it is possible to reduce the variation in the gate length dimension corresponding to the mask alignment margin dimension generated in the manufacturing process.

Also, since the variation in the gate length of the field effect transistor for cell selection can be reduced, the gate length can be reduced by an amount corresponding to the mask alignment allowance in the manufacturing process.

According to the above means (2), the gate length dimension of the charge storage gate electrode of the information storage field effect transistor is set to a mask alignment margin dimension in the manufacturing process at the time of patterning the upper control gate electrode. Since there is no influence from the corresponding variation, the variation in the gate length dimension can be reduced.

Further, since the variation in the gate length of the charge storage gate electrode of the information storage field effect transistor can be reduced, the gate length can be reduced by an amount corresponding to the mask alignment margin in the manufacturing process.

According to the above means (1) or (2) , the gate length of the cell selection field effect transistor, or the gate length of the cell selection field effect transistor and the gate of the information storage field effect transistor are determined. Since the long dimension can be reduced by an amount corresponding to the mask alignment allowance in the manufacturing process, the occupied area of the memory cell can be reduced, and the degree of integration of the semiconductor integrated circuit device can be improved.

According to the above-described means (1) or (2) , the memory cell having the cross-point cell structure has all of the upper surface and side surfaces in the gate length direction of the charge storage gate electrode of the information storage field effect transistor. Is covered with a control gate electrode, and the amount of superposition of the charge storage gate electrode and the control gate electrode is always constant irrespective of mask misalignment in the manufacturing process, so that variations in information writing characteristics or information erasing characteristics can be reduced. . As a result, EEP
The reliability of the operation performance of the ROM can be improved.

The configuration of the present invention will be described below together with an embodiment in which the present invention is applied to a semiconductor integrated circuit device having a NOR type (horizontal structure) EEPROM.

In all the drawings for describing the embodiments, parts having identical functions are given same symbols and their repeated explanation is omitted.

[0036]

(Embodiment 1) FIG. 2 (equivalent circuit diagram) shows a configuration of a NOR type EEPROM mounted on a semiconductor integrated circuit device which is Embodiment 1 of the present invention.

As shown in FIG. 2, a NOR type EEPROM
The memory cell M which stores the information of 1 [bit] is composed of a series connection circuit of a field effect transistor for information storage and a field effect transistor for cell selection. As will be described in a specific cross-sectional structure described later, in the memory cell M, the source region of the information storage field effect transistor and the drain region of the cell selection field effect transistor are not substantially formed, and both channel formation regions are formed. As it is directly connected,
As shown in FIG. 7, it can be apparently represented as one field effect transistor. Each of the information storage field-effect transistor and the cell selection field-effect transistor is of an n-channel conductivity type.

The memory cell M has a gate width direction (in FIG. 2,
A plurality of cells are electrically connected in parallel (in the vertical direction) and arranged to form a memory cell column. Although not limited to this number, 16 memory cells M (of 16 [bit] information) are arranged in the memory cell column. A plurality of memory cell columns are arranged in the vertical direction and the horizontal direction, respectively, to form a memory cell array (memory cell mat).

In each of the memory cells M in the memory cell column, the drain regions of the information storage field effect transistors adjacent in the arrangement direction (vertical direction in FIG. 2) are electrically connected to each other. The mutually connected drain regions form a data line DL or a source line SL in a memory cell column. In each of the memory cells M in the memory cell column, the source regions of the cell selection field effect transistors adjacent in the arrangement direction are electrically connected to each other. The source regions connected to each other constitute a source line SL or a data line DL in a memory cell column. The data line D
Both L and the source line SL extend substantially in parallel with each other along the arrangement direction of the memory cells M in the memory cell column.

In the memory cell M of the memory cell column, the control gate electrode of the information storage field effect transistor and the selection gate electrode of the cell selection field effect transistor are integrally formed and electrically connected. The gate electrode is connected to a word line WL. The word line WL is
The memory cells M of the memory cell column extend in a direction (lateral direction in FIG. 2) crossing the arrangement direction of the memory cells M, and a plurality of the memory cells are arranged in the arrangement direction.

The data line DL is connected to a select signal line L1.
In intervening select-purpose MISFET Q _S1 to be controlled, it is connected to the sense amplifier circuit SA. The source line SL is a select MISFET controlled by the select signal line L2.
Fixed power supply (ground potential, for example, 0 [V]) with Q _S2 interposed
Connected to. Which select MISFET Q _S1 ,
Q _{S2 is} also of the n-channel conductivity type.

The memory cell M of this type of NOR type EEPROM is generally called a split gate structure.

Next, a specific structure of the NOR type EEPROM will be briefly described with reference to FIG. 1 (a plan view of a main part) and FIG. 3 (a cross-sectional view taken along the line AA in FIG. 1). I do.

As shown in FIGS. 1 and 3, a NOR type EE
A semiconductor integrated circuit device equipped with a PROM is mainly composed of a p- type semiconductor substrate 1 made of single crystal silicon.

In the memory cell M of the NOR type EEPROM, the gate width of the information storage field effect transistor Qm is defined by the element isolation insulating film 2 and the p-type channel stopper region 3. It is composed of That is, the information storage field effect transistor Qm corresponds to a channel forming region formed by the p − type semiconductor substrate 1, the gate insulating film 4, the charge storage gate electrode 5, the gate insulating film 6, the control gate electrode 7, and the drain region. The semiconductor device is mainly composed of an n + type semiconductor region 8.

The charge storage gate electrode 5 is a NOR type E
In the manufacturing process of the EPROM, it is formed in a first layer gate material forming step, and is formed of, for example, a polycrystalline silicon film.

The control gate electrode 7 is formed in a second-layer gate material forming step in the manufacturing process, and is formed of, for example, a polycrystalline silicon film. The control gate electrode 7 is integrally formed with the word line (WL) 7 in the gate length direction (directly connected to the drain region side, and connected to the selection gate electrode 7 of the cell selection field effect transistor at the source region side). Connected via). That is, the word line 7 is formed in the same step as the control gate electrode 7. Since the word line 7 extends in the same direction as the gate length direction in the cross point cell structure, the upper surface of the charge storage gate electrode 5 is covered with the control gate electrode 7, and the side surface in the gate length direction is the word line 7 (source). The region side is covered with a select gate electrode 7), and the entire surface is covered.

Each of the control gate electrode 7 and the charge storage gate electrode 5 is patterned by anisotropic etching using an etching mask (a photoresist mask formed by photolithography) having the same gate width direction. It is cut into layers.

The control gate electrode 7, the word line 7, and the like, that is, the second-layer gate material may be formed of a single layer of a high melting point metal film or a high melting point metal silicide film in order to increase the information reading operation speed of the EEPROM. Alternatively, a composite film in which a high melting point metal film or a high melting point metal silicide film is stacked on a polycrystalline silicon film may be used.

The n + type semiconductor region 8 corresponding to the drain region is formed on the main surface portion of the p − type semiconductor substrate 1 on the side of the charge storage gate electrode 5 on the drain region side in the gate length direction. It is formed in self-alignment with the storage gate electrode 5. Specifically, n + type semiconductor region 8
Is formed by using the charge storage gate electrode 5 as a main body of an impurity introduction mask and introducing an n-type impurity by an ion implantation apparatus. When the memory cell M is viewed as one transistor as described above, the n-type impurity in the n + -type semiconductor region 8 is slightly diffused from the end face of the charge storage gate electrode 5 to the channel forming region side. A part of each of the type semiconductor region 8 and the charge storage gate electrode 5 is superimposed and has a non-offset structure.

In the memory cell column, n + -type semiconductor regions 8 corresponding to the drain regions of information storage field effect transistors Qm of each memory cell M are integrally formed and electrically connected to each other in the gate width direction. , Data lines or source lines.

The n + type semiconductor region 8 corresponding to the drain region of the information storage field effect transistor Qm of each of the memory cells M at the first stage and the last stage of the memory cell column is connected to the connection formed on the interlayer insulating film 10. The hole 11 is connected to a data line (DL) or a source line (SL) 12. The data line 12 is mainly configured to reduce the resistance of the data line formed by the n + -type semiconductor region 8 in the memory cell column. The data line or the source line 12 is formed in a first-layer wiring material forming step in the manufacturing process, and is formed of, for example, any of an aluminum film and an aluminum alloy film. The aluminum alloy film is an aluminum film to which at least one of Cu for improving migration resistance and Si for improving alloy spike resistance is added.

Of the memory cells M, the cell-selecting field-effect transistor Qs has a gate width of the element isolation insulating film 2.
And is defined by the p-type channel stopper region 3 and is formed on the main surface of the p − type semiconductor substrate 1. That is, the cell-selecting field-effect transistor Qs mainly includes a channel-forming region formed on the p − -type semiconductor substrate 1, a gate insulating film 6, a selection gate electrode 7, and an n + -type semiconductor region 9 corresponding to a source region. Is done.

The select gate electrode 7 is formed integrally with and electrically connected to the control gate electrode 7 of the information storage field effect transistor Qm in the gate length direction.

The n + type semiconductor region 9 corresponding to the source region is located at a predetermined distance from the side of the charge storage gate electrode 5 on the side of the source region in the gate length direction.
The charge storage gate electrode 5 is formed on the main surface of the p − type semiconductor substrate 1 in a self-aligned manner. Although the formation method will be described later, the n + -type semiconductor region 9 is ion-implanted with an n-type impurity by using an impurity introduction mask (16) formed on the side of the charge storage gate electrode 5 in a self-aligned manner. It is formed by introduction with an apparatus. When the memory cell M is viewed as a single transistor as described above, the n + -type semiconductor region 9 and the charge storage gate electrode 5 are each separated at a fixed interval.
Each of the charge storage gate electrodes 5 has an offset structure that does not overlap.

In the memory cell column, n + -type semiconductor regions 9 corresponding to the source regions of cell selection field-effect transistors Qs of each memory cell M are integrally formed and electrically connected in the gate width direction. , Source lines or data lines.

The n + -type semiconductor region 9 corresponding to the source region of the cell-selecting field effect transistor Qs of each of the memory cells M at the first stage and the last stage of the memory cell column is connected to the connection formed on the interlayer insulating film 10. The hole 11 is connected to a source line or a data line 12. The source line 12 is formed mainly for the purpose of reducing the resistance value of the source line formed by the n + type semiconductor region 9 in the memory cell column.

Next, each of the information writing operation, the information erasing operation and the information reading operation of the NOR type EEPROM will be briefly described.

[Information Writing Operation] The information writing operation will be described with reference to FIG. 4 (equivalent circuit diagram) and FIG. 5 (modeled sectional view).

The writing of information in the memory cell M is performed by injecting channel hot electrons from the source region (or drain region) side so that the information storage field-effect transistor Qm
This is performed by injecting electrons into the charge storage gate electrode 5 of FIG.

That is, the control gate electrode 7 of the information storage field effect transistor Qm of the memory cell M has a high voltage _VCG, for example, 10 to 15 [V], and the n + type semiconductor region 8 corresponding to the drain region has a high voltage _Vd. for example 5 to 10 [V], is applied to each of the ground voltage V _s for example 0 [V] to the n + -type semiconductor region 9 which corresponds to the source region of the cell selection field effect transistor Qs. A ground voltage V _sub, for example, 0 [V] is applied to the p − type semiconductor substrate 1. Since the selection gate electrode 7 of the cell selection field effect transistor Qs is integrally formed with the control gate electrode 7 of the information storage field effect transistor Qm, when the high voltage V _CG is applied to the control gate electrode 7, the selection gate electrode 7 is selected. 7, the high voltage V _CG is also applied, and the cell selection field effect transistor Qs is turned on. In this case, the lateral electric field intensity on the surface of the p @-type semiconductor substrate 1 between the charge storage gate electrode 5 of the information storage field effect transistor Qm and the selection gate electrode 7 of the cell selection field effect transistor Qs increases, and the hot field increases. Electrons are generated and injected into the charge storage gate electrode 5 by a vertical electric field.

The information storage field effect transistor Qm
When the electrons are injected into the charge storage gate electrode 5, the threshold voltage increases. When the memory cell M in which the threshold voltage of the information storage field-effect transistor Qm has become high is information 1, the memory cell M in which information is not written becomes information 0.

In the memory cell M, when information is written from the source region side, the impurity concentration profile of the drain region side, that is, the n + type semiconductor region 8 of the field effect transistor Qm for information storage is relaxed, and the lateral region on the drain region side is relaxed. Reduce the directional electric field.

Further, in the memory cell M, when information is written on the drain region side, the impurity concentration profile on the drain region side is sharpened, and the lateral electric field is increased.

FIG. 4 shows a method for writing information in a large number of bits simultaneously.

Information is written in even columns (memory cell columns).
-Odd column order or Odd column-Even column order. For example, when writing information to the memory cell Ma arranged second from the top of the even column (i) and not writing information to the memory cell Mb of the next even column (i + 2), the following is performed.

The second word line W from the top of each column
A high voltage V _CG is applied to L (high level H), and a ground voltage is applied to other word lines WL. On the other hand, the high voltage _Vd is applied to the data line DL of the even column (i), and the ground potential is applied to each of the data line DL of the next even column (i + 2), the other data lines DL, and the source line SL. I do. Under such conditions, information is written to memory cell Ma, and no information is written to memory cell Mb. Also,
The high voltage _Vd is applied to the source region side of the memory cell Ma ′, but erroneous writing of information is not performed if the impurity concentration profile of the source region is relaxed.

[Information Erasing Operation] Regarding the information erasing operation,
This will be described with reference to FIG. 6 (equivalent circuit diagram) and FIG. 7 (modeled cross-sectional view).

Information is erased from the memory cell M by extracting electrons from the charge storage gate electrode 5 of the information storage field effect transistor Qm by the FN tunnel current from the drain region side.

That is, the ground voltage V _{CG is} applied to the control gate electrode 7 of the information storage field effect transistor Qm of the memory cell M, the ground voltage V _{sub is} applied to the p − type semiconductor substrate 1, and the n + type semiconductor region 8 corresponding to the drain region is provided. To each of high voltage _Vd, for example, 10 to 15 [V]. While the n + -type semiconductor region 9 which corresponds to the source region of the cell selection field effect transistor Qs high voltage V _s equal to the high voltage V _d is applied to the select gate electrode 7 is the ground voltage is applied to the cell selection Since the field effect transistor Qs is in a non-conducting state, erasing on the source region side does not occur.

FIG. 6 shows a case where a large number of bits of information are erased at the same time. The ground voltage _VCG is applied to all word lines WL, and the high voltage _Vd is applied to all data lines DL.

The negative high voltage V _{CG is} applied to the control gate electrode 7 of the information storage field effect transistor Qm of the memory cell M.
For example -5 to-10 [V], p-type semiconductor substrate 1 to the ground voltage V _sub, by applying a voltage of the voltage V _d for example 3-6 to n + -type semiconductor region 8 corresponding [V] to the drain region Is also good.

8 and 9 (modeled cross-sectional views of main parts) show another embodiment of the information erasing method.

In the memory cell M shown in FIG. 8, a negative high voltage _VCG is applied to the control gate electrode 7 of the information storage field effect transistor Qm, and pN is applied to the charge storage gate electrode 5 from almost the entire surface by the FN tunnel current. The information is erased by emitting electrons to the type semiconductor substrate 1.

Memory cell M shown in FIG. 9 is formed on the main surface of p-type well region 1W provided on the main surface of n- type semiconductor substrate 1, and a high voltage V _well is applied to p-type well region 1W. Then, by erasing electrons from almost the entire surface of the charge storage gate electrode 5 to the p-type well region 1W by the FN tunnel current, information is erased.

[Information Read Operation] The information read operation will be described with reference to FIG. 10 (equivalent circuit diagram) and FIG. 11 (modeled sectional view).

The information is read from the memory cell M by controlling the control gate electrode 7 of the information storage field effect transistor Qm of the selected memory cell M and the cell selection field effect transistor Qm.
The read voltage V _CG, for example, 5
[V] is applied. Further, an n + type semiconductor region 8 corresponding to the drain region of the information storage field effect transistor Qm.
Low voltage _Vd, for example, 1
[V], each of the ground voltage V _s is applied to the n + -type semiconductor region 9 which corresponds to the source region of the cell selection field effect transistor Qs. The selected memory cell M is turned off when electrons are injected into the charge storage gate electrode 5 of the information storage field-effect transistor Qm, and turned on when electrons are not injected.

FIG. 10 shows a method for simultaneously reading many bits of information.

Information is read out in the order of even columns-odd columns.
Alternatively, the processing is performed in the order of odd-numbered columns-even-numbered columns. Selection of an even column is carried out in the select-purpose MISFET Q _S1, selection of the odd columns is carried out in the select-purpose MISFET Q _S2. For example, when reading information from the memory cells M arranged second from the top in an even-numbered column, a selection signal (for example, 5 [V]) is applied to the select signal line L1 and a non-selection signal (for example, 0 [V] is applied to the select signal line L2). V], a read voltage V _{CG is} applied to the data lines DL of the even columns, a selection signal (for example, 5 V) to the selected word line WL, and a ground voltage to the unselected word lines. by detecting and amplifying the amount of change in the applied read voltage V _CG in DL by the sense amplifier circuit, information written it is read.

Next, a method for forming a NOR type EEPROM will be briefly described with reference to FIGS. 12 to 18 (cross-sectional views showing main parts in respective manufacturing steps).

First, a p − type semiconductor substrate 1 made of single crystal silicon is prepared.

Next, an element isolation insulating film 2 and a p-type channel stopper region 3 are respectively formed on the main surface of the p- type semiconductor substrate 1 which will be an inactive region.

Next, a gate insulating film 4 is formed on the main surface of the p @-type semiconductor substrate 1 which will be an active region.
As shown in FIG. 5, a charge storage gate electrode 5 is formed on the gate insulating film 4 in which a part of the information storage field effect transistor Qm in the gate length direction is patterned. The charge storage gate electrode 5 is formed by performing anisotropic etching such as RIE on the polycrystalline silicon film deposited by the CVD method as described above.

Next, a thermal oxidation treatment is performed to form a thin silicon oxide film on the exposed region of the main surface which will be the active region of the p − type semiconductor substrate 1, and thereafter, as shown in FIG. An n @ + -type semiconductor region 8 corresponding to the drain region of the field effect transistor Qm is formed. n + type semiconductor region 8
Uses the charge storage gate electrode 5 as an impurity introduction mask, and uses the impurity introduction mask 15 formed on the source region side (the region where the cell selection field-effect transistor Qs is formed) to form an n-type impurity (As or P). ) Formed by introducing 8n with an ion implantation device. This n + type semiconductor region 8 is formed in self-alignment with the charge storage gate electrode 5.

Next, as shown in FIG. 14, an impurity introduction mask 16 is formed at least on the side of the source region side of the charge storage gate electrode 5 of the information storage field effect transistor Qm.
To form The impurity introduction mask 16 is formed, for example, by depositing a silicon oxide film on the upper layer of the charge storage gate electrode 5 by a CVD method, and by anisotropic etching such as RIE on the entire surface of the silicon oxide film by an amount corresponding to the deposited film thickness. To form only on the side surface of the charge storage gate electrode 5. Impurity introduction mask 16
Corresponds to a so-called sidewall spacer. The impurity introduction mask 16 is formed in a self-aligned manner with respect to the charge storage gate electrode 5, and the variation in the etching amount is smaller than the mask misalignment amount in the manufacturing process, so that the film thickness can be controlled with high accuracy. The thickness of the impurity introduction mask 16 corresponds to the gate length of the cell selection field effect transistor Qs. It should be noted that the impurity introduction mask 16 may be a silicon nitride film instead of the silicon oxide film.
Any material can be used as long as it has a certain etching selectivity with respect to the mold semiconductor substrate 1.

Next, a thermal oxidation treatment is performed to form a thin silicon oxide film on the exposed region of the main surface of the p − type semiconductor substrate 1 as shown in FIG. 15, and thereafter, as shown in FIG. As shown in FIG. 7, an n @ + -type semiconductor region 9 corresponding to the source region of the cell selection field effect transistor Qs is formed. n
The + type semiconductor region 9 is formed by mainly using the impurity introduction mask 16 and introducing an n type impurity (As or P) by an ion implantation device. That is, the n + -type semiconductor region 9 is formed in self-alignment with the impurity introduction mask 16, so that the n + -type semiconductor region 9 is formed in self-alignment with the charge storage gate electrode 5. The distance between the n + -type semiconductor region 9 and the charge storage gate electrode 5 which are separated via the impurity introduction mask 16 corresponds to the gate length of the cell selection field effect transistor Qs.

Next, as shown in FIG. 17, the impurity introduction mask 16 is removed.

Next, a gate insulating film 6 is formed on the surface of the charge storage gate electrode 5, and the gate insulating film 6 is formed in a region where the impurity introduction mask 16 is removed, that is, in a region where the cell selection field effect transistor Qs is formed. To form

Next, as shown in FIG. 18, the gate insulating film 6 is formed in the region of the information storage field effect transistor Qm.
The control gate electrode 7 is formed thereon, and the select gate electrode 7 is formed on the gate insulating film 6 in the region of the cell selection field effect transistor Qs. Further, the word line 7 is formed in the same step as the step of forming each of the control gate electrode 7 and the selection gate electrode 7. As described above, each of the control gate electrode 7 and the select gate electrode 7 is formed by performing anisotropic etching on a polycrystalline silicon film deposited by, for example, a CVD method. When patterning the control gate electrode 7,
Another part of the charge storage gate electrode 5 is patterned so as to match the gate width of the control gate electrode 7. That is, each of the control gate electrode 7 and the charge storage gate electrode 7 is cut and overlapped. When this step is completed, each of the cell selection field effect transistor Qs and the cell selection field effect transistor Qs is completed, and as a result, the memory cell M is completed.

Next, each of the interlayer insulating film 10 and the connection hole 11 is formed, and thereafter, as shown in FIGS.
Each of the data line 12 and the source line 12 is formed.

By performing these series of manufacturing steps,
The NOR EEPROM of the first embodiment is completed.

As described above, the NOR type EEP of the first embodiment is
According to the ROM, the following effects can be obtained.

(1) Field effect transistor Q for information storage having charge storage gate electrode 5 and control gate electrode 6
m, each series-connected circuit of a cell selection field effect transistor Qs having a selection gate electrode 7 adjacent to an end of the charge storage gate electrode 5 in the gate length direction and integrated with the control gate electrode 7 Is a memory cell M
In a semiconductor integrated circuit device equipped with an EPROM, p
Forming a charge storage gate electrode 5 of an information storage field effect transistor Qm on one main surface of a semiconductor substrate 1 with a gate insulating film 4 interposed therebetween;
Forming an n + -type semiconductor region 8 serving as a drain region of an information storage field-effect transistor Qm at one end in the gate length direction of the charge storage gate electrode 5 on one main surface of the p-type semiconductor substrate 1 Forming an impurity introduction mask 16 by self-alignment with the charge accumulation gate electrode 5 at the other end in the gate length direction of the charge accumulation gate electrode 5 on one main surface; , The p-
Forming an n + semiconductor region 9 serving as a source region of the cell selection field effect transistor Qs at the other end of the charge storage gate electrode 5 on one main surface of the type semiconductor substrate 1, and removing the impurity introduction mask 16 Thereafter, a gate insulating film 6 is formed on the charge storage gate electrode 5 and a gate insulating film 6 is formed on one main surface of the p − type semiconductor substrate 1 in a region where the impurity introduction mask 16 is removed. And forming the control gate electrode 7 of the information storage field effect transistor Qm on the one gate insulating film 6 and integrally forming the control gate electrode 7 on the other gate insulating film 6. Forming the select gate electrode 7 of the selected cell effect transistor Qs. With this configuration, the gate length (channel length) of the cell selection field-effect transistor Qs of the memory cell M of the EEPROM is set to the information storage field-effect transistor Qs.
Since it is defined by the impurity introduction mask 16 formed in a self-alignment manner with respect to the m charge storage gate electrode 5, the variation in the gate length dimension corresponding to the mask alignment margin dimension generated in the manufacturing process can be reduced. Further, since the variation in the gate length of the cell selection field effect transistor Qs can be reduced, the gate length can be reduced by an amount corresponding to the mask alignment allowance in the manufacturing process.

(2) The control gate electrode 7 of the information storage field effect transistor Qm is
The patterning of the charge storage gate electrode 5 is performed in another independent process. With this configuration, the influence of the variation in the gate length dimension of the charge storage gate electrode 5 of the information storage field effect transistor Qm corresponding to the mask alignment allowance dimension in the manufacturing process at the time of patterning the upper control gate electrode 7 is reduced. Because I do not receive
Variations in the gate length can be reduced. Further, since the variation in the gate length of the charge storage gate electrode 5 of the information storage field effect transistor Qm can be reduced, the gate length can be reduced by an amount corresponding to the mask alignment margin in the manufacturing process.

(3) The memory cell M formed by the above method
Is provided in the semiconductor integrated circuit device. With this configuration, the gate length of the cell selection field-effect transistor Qs, or the gate length of the cell selection field-effect transistor Qs and the gate length of the information storage field-effect transistor Qm are reduced to the mask alignment margin in the manufacturing process. Since the size can be reduced by a corresponding amount, the area occupied by the memory cells M can be reduced, and the degree of integration of the semiconductor integrated circuit device can be improved.

(4) In the memory cell M, the control gate electrode 7 of the information storage field effect transistor Qm is formed integrally with and electrically connected to the word line 7 whose extending direction coincides with the gate length direction. It has a cross-point cell structure. With this configuration, in the memory cell M having the cross-point cell structure, all of the upper surface and side surfaces of the charge storage gate electrode 5 of the information storage field effect transistor Qm in the gate length direction are covered with the control gate electrode 7, and the charge storage Since the respective overlapping amounts of the gate electrode 5 and the control gate electrode 7 are always constant irrespective of the mask misalignment in the manufacturing process, it is possible to reduce the variation in the information writing characteristic or the information erasing characteristic. As a result, the reliability of the operation performance of the EEPROM can be improved.

(Embodiment 2) The present embodiment 2 employs the above-described N
In the OR-type EEPROM, each of a data line and a source line (diffusion layer wiring) in a memory cell column is formed in a self-aligned manner with respect to a charge storage gate electrode of an information storage field effect transistor of a memory cell. These are two embodiments.

FIG. 19 shows a configuration of a NOR type EEPROM mounted on a semiconductor integrated circuit device according to a second embodiment of the present invention.
A brief description will be given using (a plan view of a main part) and FIG. 20 (a cross-sectional view taken along line BB in FIG. 19).

As shown in FIGS. 19 and 20, the NOR type EEPROM according to the second embodiment has a data line (for example, n + type semiconductor region 8) and a source line (n + type semiconductor) extending in a memory cell column. Each of the regions 9) is a charge storage gate electrode 5 of the information storage field effect transistor Qm of the memory cell M.
Are formed in a self-aligned manner. That is, the memory cell M
After using the charge storage gate electrode 5 of the information storage field effect transistor Qm as an etching mask and removing the element isolation insulating film 2 over the entire surface of the p − type semiconductor substrate 1, the n + type semiconductor region corresponding to the drain region is removed. 8 are formed, and the n + type semiconductor region 8 is used as the data line. Similarly, the element isolation insulating film 2 on the source region side of the charge storage gate electrode 5 of the information storage field effect transistor Qm
Also, after the charge storage gate electrode 5 is used as an etching mask and removed by self-alignment, the n + -type semiconductor region 9 corresponding to the source region of the cell selection field effect transistor Qs is removed.
Is formed, and this n + type semiconductor region 9 is used as the source line.

Next, a method of forming the NOR type EEPROM will be briefly described with reference to FIGS. 21 to 25 (a cross-sectional view of a main part showing each manufacturing process).

First, a p − type semiconductor substrate 1 is prepared, and an element isolation insulating film 2 and a p type channel stopper region 3 are formed on the main surface of the p − type semiconductor substrate 1.

Next, as shown in FIG. 21, a gate insulating film 4 of the information storage field effect transistor Qm and a charge storage gate electrode 5 partially patterned are formed.

Next, as shown in FIG. 22, using the charge storage gate electrode 5 as an etching mask, the element isolation insulating film 2 and the gate insulating film 4 on the main surface of the p − type semiconductor substrate 1 are removed.

Next, as shown in FIG. 23, an n + type semiconductor region 8 corresponding to each of the drain region of the information storage field effect transistor Qm and the data line in the memory cell column is formed. The n @ + type semiconductor region 8 uses the charge storage gate electrode 5 as an impurity introduction mask and also uses an impurity introduction mask 18 covering the region of the cell selection field effect transistor Qs. It is formed by introducing impurities.

Next, an impurity introduction mask 16 is formed on the side of the charge storage gate electrode 5 and on the side wall of the element isolation insulating film 2, and thereafter, as shown in FIG. The n + -type semiconductor region 9 corresponding to the source region of the cell-selecting field-effect transistor Qs is formed in self-alignment with the impurity introduction mask 16.

Next, the impurity introduction mask 16 is removed, and a gate insulating film 6 is formed on the surface of the charge storage gate electrode 5 in each of the formation regions of the cell selection field effect transistor Qs. As shown, the control gate electrode 7,
Each of the select gate electrodes 7 is formed. When this step is completed, each of the information storage field effect transistor Qm and the cell selection field effect transistor Qs is completed.

Thereafter, an interlayer insulating film 10, a connection hole 11, a data line 12, and a source line 12 (not shown) are formed, thereby forming the NOR shown in FIGS.
The type EEPROM is completed.

As described above, the NOR type EEP of the second embodiment
According to the ROM, in addition to the effects of the first embodiment, n is self-aligned to the side of the charge storage gate electrode 5 of the information storage field effect transistor Qm of the memory cell M.
A + type semiconductor region 8 is formed, a data line of a memory cell column is formed, and an n + type semiconductor region 9 is formed to form a source line. With this configuration, the distance between the charge storage gate electrode 5 of the information storage field effect transistor Qm of the memory cell M and each of the data line and the source line in the memory cell column is almost eliminated.
The degree of integration of the OM can be improved.

As described above, the invention made by the present inventor is:
Although the present invention has been specifically described based on the embodiment, the present invention is not limited to the embodiment, and it is needless to say that various changes can be made without departing from the gist of the present invention.

[0110]

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

(1) Field effect transistor for storing information
In a semiconductor integrated circuit device having an EEPROM in which each series connection circuit of cell selection field effect transistors is a memory cell, variations in the gate length of the cell selection field effect transistor of the memory cell can be reduced.

(2) In the semiconductor integrated circuit device,
Variations in the gate length of the information storage field effect transistor of the memory cell can be reduced.

(3) The area occupied by the memory cells can be reduced, and the integration degree of the EEPROM, that is, the integration degree of the semiconductor integrated circuit device can be improved.

(4) In the semiconductor integrated circuit device,
The operating characteristics of the EEPROM can be stabilized, and the electrical reliability can be improved.

[Brief description of the drawings]

FIG. 1 is a plan view of an EEPROM according to a first embodiment of the present invention.

FIG. 2 is an equivalent circuit diagram of the EEPROM.

FIG. 3 is a sectional view of the EEPROM.

FIG. 4 is an equivalent circuit diagram illustrating an information writing operation of the EEPROM.

FIG. 5 is a modeled cross-sectional view.

FIG. 6 is an equivalent circuit diagram illustrating an information erasing operation.

FIG. 7 is a cross-sectional view modeled.

FIG. 8 is a modeled cross-sectional view of another example.

FIG. 9 is a modeled cross-sectional view of another example.

FIG. 10 is an equivalent circuit diagram illustrating an information reading operation.

FIG. 11 is a cross-sectional view modeled.

FIG. 12 is a sectional view of the EEPROM in a first manufacturing step.

FIG. 13 is a sectional view in a second manufacturing step.

FIG. 14 is a sectional view in a third manufacturing step.

FIG. 15 is a sectional view in a fourth manufacturing step.

FIG. 16 is a sectional view in a fifth manufacturing step.

FIG. 17 is a sectional view in a sixth manufacturing step.

FIG. 18 is a sectional view in a seventh manufacturing step.

FIG. 19 is a plan view of an EEPROM according to a second embodiment of the present invention.

FIG. 20 is a sectional view of the EEPROM.

FIG. 21 is a sectional view of the EEPROM in a first manufacturing step.

FIG. 22 is a sectional view in a second manufacturing step.

FIG. 23 is a sectional view in a third manufacturing step.

FIG. 24 is a sectional view in a fourth manufacturing step.

FIG. 25 is a sectional view in a fifth manufacturing step.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 4, 6 ... Gate insulating film, 5, 7 ... Gate electrode, 12, DL, SL ... Data line or source line, 8, 9 ... Semiconductor region, 16 ... Mask, WL ... Word line, Qm ... Information storage field effect transistor, Qs: cell selection field effect transistor, M: memory cell.

────────────────────────────────────────────────── ─── Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI H01L 29/792 (56) References JP-A-2-254760 (JP, A) JP-A-2-110981 (JP, A) JP-A-4-367279 (JP, A) JP-A-4-176172 (JP, A) JP-A-4-14880 (JP, A) JP-A-3-268364 (JP, A) JP-A-3-76163 (JP JP, A) JP-A-2-295169 (JP, A) JP-A-2-240968 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/8247 H01L 21/8234 H01L 27/088 H01L 27/115 H01L 29/788 H01L 29/792

Claims (2)

(57) [Claims] 1. An information storage field-effect transistor having a charge storage gate electrode and a control gate electrode, a selection element adjacent to an end of the charge storage gate electrode in a gate length direction and integrated with the control gate electrode. In a method of forming a semiconductor integrated circuit device equipped with an electrically erasable nonvolatile memory circuit using a series connection circuit of cell selection field effect transistors each having a gate electrode as a memory cell , the memory cell is an information storage field effect transistor. Control game
When the gate electrode extends in the same direction as its gate length,
Cross, which is integrated with and electrically connected to
It has a point cell structure, and has a first gate insulating film interposed on one main surface of a semiconductor substrate,
Forming a charge storage gate electrode of the information storage field effect transistor; and forming a drain region or a source region of the information storage field effect transistor at one end in the gate length direction of the charge storage gate electrode on one main surface of the semiconductor substrate. Forming a first semiconductor region to be formed, and forming an impurity introduction mask at the other end in the gate length direction of the charge storage gate electrode on one main surface of the semiconductor substrate by self-alignment with the charge storage gate electrode. Forming a second semiconductor region to be a source region or a drain region of a cell selection field effect transistor at the other end of the charge storage gate electrode on one main surface of the semiconductor substrate using the impurity introduction mask. And removing the impurity introduction mask. Thereafter, a second gate insulating film is formed on the charge storage gate electrode. Forming a third gate insulating film in a region of the main surface of the semiconductor substrate from which the impurity introduction mask has been removed; forming a control gate electrode of an information storage field effect transistor on the second gate insulating film; ,
And forming a select gate electrode of the third gate insulating film and the control gate electrode and the field-effect transistor cell selection is formed integrally on, information by emitting electrons from substantially the entire surface of the charge storage gates
A method of forming a semiconductor integrated circuit device, wherein information is erased . 2. A control gate electrode of the information storage field effect transistor according to claim 1, which is patterned in a gate length direction in a separate step from a patterning step of a charge storage gate electrode. Forming a semiconductor integrated circuit device.