JPH053293A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To realize effective integration of a longitudinal PNP transistor and a DMOSFET which are suitable for an output step inverter circuit. CONSTITUTION:First and second epitaxial layers 15, 16 are formed on a substrate 14, an N<+>-type buried layer 17 is formed on a surface of the substrate 14 and a P<+>-type collector buried layer 26 is formed on a surface of the first epitaxial layer 15. A P<+>-type emitter region 28 is formed on a surface of a region which becomes a base as a longitudinal PNP transistor 12. A body region 31 of a P<+>-type diffusion region 30 is formed simultaneously with the P<+>-type emitter region 28. A P<+>-type channel region 32 is formed integrally with the P<+>-type body region 31, and an N<+>-type source region 33 and a gate electrode 34 are formed as a DMOSFET 13.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a vertical PNP transistor and a DMOSFET (diffusion self-a).
The present invention relates to a semiconductor integrated circuit for forming an output stage inverter circuit in combination with an output MOSFET.

[0002]

2. Description of the Related Art With the development of Bi-CMOS technology in which bipolar elements and MOS elements are mixed, there is a movement to use DMOSFETs in the final stage of the output circuit of a semiconductor device.
As the output circuit, a CMOS inverter circuit in which a P-channel MOS and an N-channel MOS are combined is generally used, but a pMOSFET having the same size and size is usually used.
And nMOSFET are compared, the driving capability of pMOSFET is low due to the relation of carrier mobility.
The driving capability of T is only 1/3 to 1/2 that of nMOSFET.

Therefore, in the conventional output circuit, pMOSF is used.
In order to have the same driving capability for ET and nMOSFET, p
Since the size of the MOSFET is increased, the area of the output circuit is increased. In order to solve the above-mentioned problems, a method of replacing the pMOSFET with an NPN transistor has been proposed as described in, for example, Japanese Patent Laid-Open No. 2-264519. That is, as shown in FIG.
An inverter output circuit is formed by combining the OSFET (1) and the NPN transistor (2), and the nMOSF is connected to the base of the NPN transistor (2) via the inverter (3).
ET (1) is configured to give an input signal of opposite phase.

As another method, as shown in FIG. 15, the pMOSFET is replaced with an nMOSFET (4),
An nMOSFE in which a negative phase signal is input to the other nMOSFET (5) via an inverter (6) and replaced via a boot circuit ( 8 ) by an external capacitor (7).
It has been proposed to apply a gate voltage corresponding to V _DD + V _C (V _C is a voltage due to charges accumulated in an external capacitor) to the gate of T (4). In addition, nMOSF
The gate voltage of V _DD + V _C is applied to the gate of ET (4) by setting the source to the voltage of (V _DD −I _DS r _DS ) when the nMOSFET (4) is turned on. This is for obtaining a large output waveform.

[0005]

[Problems to be Solved by the Invention]
In the method, the emitter potential of the NPN transistor (2) is V
_B-V_BE(V_BIs the base potential, V_BEBetween base and emitter
Voltage) and V_BECannot be reduced
Therefore, there is a drawback that the output amplitude cannot be increased. One latter
Then the boot circuit (8) Eliminates the same drawbacks
Yes, but circuit to add an external capacitor (7)
Has the drawback of increasing complexity and costing the set
There is.

[0006]

The present invention has been made in view of the above-mentioned drawbacks, and a vertical PNP transistor (12) is provided.
And an n-channel DMOSFET (13) constitute an inverter output circuit. The first and second epitaxial layers (15) and (16) are laminated and a vertical PNP transistor (12) is formed at the boundary between the two. A P ⁺ -type collector buried layer (26) is formed, and the region surrounded by the collector lead-out region (27) is used as the base of the vertical PNP transistor (12), and the vertical PNP transistor (1
2) P ⁺ type emitter region (28) is formed, and simultaneously with the emitter region (28) of the vertical PNP transistor (12), the P ⁺ type diffusion region (3) of the DMOSFET (13) is formed.
0) body region (31) and body region (3
The channel region (32) of the DMOSFET (13) is formed so as to be integrated with 1), and the P ⁺ type diffusion region (30) is formed.
The N ⁺ type source region (33) is formed on the surface of and the gate electrode (34) is formed on the channel region (32).

[0007]

According to the present invention, the first epitaxial layer (1
5) By forming the collector buried layer (26) on the surface, the collector series resistance is reduced and the saturation voltage V _{CE (sat)}
The vertical PNP transistor (12) having a small Further, since the emitter region (28) of the vertical PNP transistor (12) is formed with a high impurity concentration, the carrier (hole) emitter injection efficiency is increased, and the collector current can be increased (driving capability is increased). Type PNP transistor (12) can be provided.

Further, a vertical PNP transistor (12)
P ⁺ type emitter region (28) and DMOSFET (1
Since the P ⁺ type body region (31) of 3) is formed at the same time, the process can be simplified.

[0009]

An embodiment of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a sectional view showing an NPN transistor (11), a vertical PNP transistor (12), and a DMOSFET (13) in the semiconductor integrated circuit of the present invention.

In the figure, (14) is a P-type silicon semiconductor substrate, (15) is an N-type first epitaxial layer laminated on the substrate (14), and (16) is a first epitaxial layer (15). ), An N-type second epitaxial layer laminated on the substrate, (17) is an N ⁺ -type buried layer buried in the surface of the substrate (11), and (18) is the first and second epitaxial layers (15). ) An isolation region for penetrating an island region through (16), (19) a lower part of the isolation region (18) formed from the surface of the first epitaxial layer (15), and (20) a second part. The upper part of the isolation region (18) formed from the surface of the epitaxial layer (16).

The main constituent elements of the NPN transistor (11) are formed from the surface of the first epitaxial layer (15) and are formed so as to be in contact with the N ⁺ type buried layer (17). An N ⁺ type buried layer (21), an N ⁺ type collector low resistance region (22) formed so as to reach the second N ⁺ type buried layer (21) from the surface of the second epitaxial layer (16), P formed on the surface of the island area
The base region (23) of the type and the N ⁺ type emitter region (24) formed on the surface of the base region (23).
(25) is a P ⁺ type base contact region formed for taking out the base. By forming the second N ⁺ type buried layer (21) on the entire lower surface of the base region (23), this NPN transistor (11) is selected as a high speed type and only in a portion corresponding to the collector low resistance region (22). These NPN transistors (11) can be formed to have high withstand voltages, respectively.

The main components forming the vertical PNP transistor (12) are formed simultaneously with the lower part (19) of the isolation region (18) on the surface of the first epitaxial layer (15) and N ^The substrate (1
4) and a P ⁺ -type collector buried layer (26) electrically isolated from the second epitaxial layer (16) and the upper part (20) of the isolation region (18) from the surface of the second epitaxial layer (16) at the same time. P ⁺ -type collector lead-out region (27) reaching the layer (26) and collector buried layer (26)
And a second completely enclosed by the collector lead-out area (27)
The epitaxial layer (16) is used as a base, and includes a P ⁺ -type emitter region (28) formed on the surface of the base and an N ⁺ -type base contact region (29) for taking out the base. A second N ⁺ -type buried layer (21) is arranged on both sides of the P ⁺ -type collector buried layer (26) to separate the collector buried layer (26) by autodoping and the collector buried layer (18). 26) to prevent short circuit. Further, if the N-type impurity is diffused from the surface into the region serving as the base, the speed of the vertical PNP transistor (12) is increased.

The vertical DMOSFET (13) shown in FIG.
The main component that forms the island is the vertical PNP on the surface of the island region.
The body region (31) of the P ⁺ type diffusion region (30) formed at the same time as the P ⁺ type emitter region (28) of the transistor (12) and the P ⁺ type body region (31) are integrated with D
A MOSFET (13) P-type channel region of the channel portion to become P ⁺ -type diffusion region (30) of (32), a P ⁺ -type diffusion region (30) N ⁺ -type source region formed on the surface of (33) , A polysilicon gate electrode (34) disposed on the channel region (32) via a gate oxide film.

The drain current is equal to the N ⁺ type buried layer (1
7) via the second N ⁺ type buried layer (21) formed on the surface of the first epitaxial layer (15) and the N ⁺ type low resistance region (35 formed on the surface of the second epitaxial layer (16). ) And take out from the surface at the drain electrode. The region for extracting the drain current is formed so as to surround the unit cell for each individual unit cell or for each unit cell. A source electrode that makes ohmic contact with both the N ⁺ type source region (33) and the P ⁺ type body region (31) is formed on the P ⁺ type diffusion region (30). Incidentally, D
N ⁺ type low resistance region (35) of MOSFET (13) and N
PN transistor (11) collector low resistance region (2
2) is an area in which the process is shared.

A method of manufacturing the semiconductor integrated circuit shown in FIG. 1 will be described. (A) First, antimony (Sb) for forming the N ⁺ type buried layer (17) on the surface of the P type semiconductor substrate (14)
Are selectively diffused (FIG. 2). (B) By the epitaxial growth method, the N-type first epitaxial layer (1
5) are laminated. Then, the first epitaxial layer (1
Boron (B) is selectively diffused on the surface of 5) to form a lower portion (19) of the isolation region (18) and a collector buried layer (26) of the vertical PNP transistor (12) (FIG. 3). .

(C) Next, antimony (Sb) is diffused on the surface of the first epitaxial layer (15) to form NP.
The second N ⁺ type buried layer (2
1), a second N ⁺ -type buried layer of the vertical PNP transistor (12) (21), and a second N ⁺ -type buried layer of DMOSFET (13) to form a (21) (Fig. 4). (D) An N-type second epitaxial layer (16) having a thickness of 8 to 12 μ is laminated on the surface of the first epitaxial layer (15) by the epitaxial growth method. Then, the surface of the second epitaxial layer (16) is selectively doped with phosphorus (P) or arsenic (As) to form an NPN transistor (1).
The collector low resistance region (22) of 1) and the low resistance region (35) of the DMOSFET are formed (FIG. 5). If a heat treatment for diffusing the lower part (19) of the separation region (18) upward is performed after this, the diffusion depth of the upper part (20) of the separation region (18) can be made shallow.

(E) Selectively diffusing boron (B) forming the upper portion (20) of the isolation region (18) on the surface of the second epitaxial layer (16), and performing extension diffusion by heat treatment. Connects the upper part (20) and the lower part (19) of the separation area (18) (FIG. 6). The N ⁺ -type buried layer (17) and the N ⁺ -type second buried layer (21), and the second N ⁺ -type buried layer (21) and the collector low resistance region (22) are also connected, respectively. Also,
The P ⁺ type collector buried layer (26) of the vertical PNP transistor (12) reaches the N ⁺ type buried layer (17).

(F) A gate oxide film having a film thickness of 200 to 600 Å is formed on the surface of the second epitaxial layer (16),
Polysilicon having a film thickness of 1.0 to 2.0 μ is deposited thereon,
Photoetching is performed to form a gate electrode (34) (FIG. 7). (G) By forming a selective mask on the surface of the second epitaxial layer (16) and selectively diffusing boron (B) by an ion implantation method or the like, the base contact region (25) of the NPN transistor (11) and the vertical type Emitter region (28) of PNP transistor (12), and DMOSFE
A body region (31) of T (13) is formed (FIG. 8).
These areas have a surface sheet resistance of 10 to 20 Ω · c.
m and a sufficiently high impurity concentration region. The order of forming the gate electrode (34) and this step can be reversed.

(H) Change the selection mask and change the DMOSFE
At T (13), the gate electrode (34) is used as a part of the mask, and boron (B) is selectively diffused to form the base region (23) of the NPN transistor (11) and the DMOSFET (13). Forming a channel region (32) (FIG. 9). NPN transistor (1
Boron (B) forming the base region (23) of 1) is P
^{In the +} type base contact region (25), DMOSFET
Boron (B) forming the channel region (32) of (13) is introduced to the P ⁺ type body region (31) in an overlapping manner. In addition, P ^{+ of} the vertical PNP transistor (12)
It may be overlaid on the mold emitter region (28). The impurity concentration of boron (B) introduced in this step is lower than that of the emitter region (28) of the vertical PNP transistor (12).

(I) The selection mask is changed and DMOSFE
At T (13), again using the gate electrode (34) as a part of the mask, phosphorus (P) or arsenic (As) is selectively diffused from the surface, and the emitter region (24) of the NPN transistor (11) and the vertical PNP are formed. The base contact region (29) of the transistor (12) and the DMOSFET (1
The source region (33) of 3) is formed (FIG. 10). After that, the Al electrode and the like are arranged to manufacture the semiconductor integrated circuit of the present invention.

FIG. 11 shows an output stage inverter circuit which can be constructed by the device of the present invention. This circuit includes a PNP transistor (40) replaced by a vertical PNP transistor (12) instead of a pMOSFET, and a DMOSFET.
In combination with the nMOSFET (41) formed by (13), an input signal of the same phase is applied to the base of the PNP transistor (40) and the gate of the nMOSFET (41), and the collector of the PNP transistor (40) and the nMOSFET (41). The output signal is taken out from the connection point with the drain of 41), and when the input signal is positive, n
When the MOSFET (41) is on, negative polarity
The transistor (40) is turned on to drive the load. In this case, the minimum level of the output waveform is determined by the on-resistance R _DS of the nMOSFET (41), and the maximum level of the output waveform is determined by the saturation voltage V _{CE (sat)} of the PNP transistor (40). The output amplitude that makes the most effective use of the difference (V _DD −V _SS ) is obtained, and the drive capability of the output circuit is high.

In the vertical PNP transistor (12) of the present invention, the collector buried layer (26) is formed from the surface of the first epitaxial layer (15),
Since the collector buried layer (26) can be thickened to reduce the collector series resistance r _C , its saturation voltage V
_{CE (sat)} can be made sufficiently small. Therefore, the amplitude of the output waveform can be further increased.

In the vertical PNP transistor (12) of the present invention, the emitter is a P ⁺ -type emitter region (28) having a higher impurity concentration than the base region (23) of the NPN transistor (11), so that The carrier (hole) injection efficiency to the base can be increased and the collector maximum current I _Cmax of the transistor can be increased. Therefore P
By increasing the driving capability of the NP transistor (40), n
PNP when matching the driving capability with MOSFET (41)
The area occupied by the transistor (40) can be reduced.

Further, a vertical PNP transistor (12)
P ⁺ type emitter region (28) and DMOSFET (1
Since the step of 3) is shared with the P ⁺ type body region (31), the step can be simplified. FIG. 12 shows a second embodiment of the present invention. A vertical DM in which the DMOSFET (13) of FIG. 1 takes out a drain current through the buried layer (17).
In contrast to the OS, the channel area (3
N ⁺ type drain region (3
It is a lateral DMOS which takes out the drain current by 6). The N ⁺ type drain region (36) is formed simultaneously with the emitter region (24) of the NPN transistor (11),
It is called a lateral DMOS because a channel current flows laterally from the channel region (32) through the surface of the second epitaxial layer (16) below the gate electrode (34). Other configurations and operational effects are the same as in FIG.

The NPN transistor (11) and the vertical P
NP transistor (12), and DMOSFET (1
Although the integrated circuit 3) has been described, the semiconductor integrated circuit of the present application is an n-channel MOSFET shown in the figure.
(50) and the P-channel MOSFET (51) coexist in the same manner. n-channel MOSFE
The T (50) is an N ⁺ type source / drain region (53) and a gate electrode (34) on the P type well region (52) in which the process is shared with the emitter region (24) of the NPN transistor (11). Consisting of a P-channel MOSFET
(51) is a DMOS on the surface of the N-type well region (54)
It is composed of a P ⁺ type body region (31) of the FET (13), a P ⁺ type source / drain region (55) and a gate electrode (34) whose process is shared. n-channel MOSFET
The P ⁺ type buried layer (56) of (50) is shared with the collector buried layer (26) of the vertical PNP transistor (12) in the same process, and reaches the substrate (14).

[0026]

As described above, according to the present invention, P
This has the advantage that an inverter output circuit combining the NP transistor (40) and the nMOSFET (41) can be configured in an integrated circuit. Moreover, since the saturation voltage V _{CE (sat)} of the vertical PNP transistor (12) can be reduced by _{adopting the} two-stage epitaxial structure, the amplitude of the output waveform can be further increased and the emitter can be the base region of the NPN transistor (11) ( 23) The region having a higher impurity concentration has an advantage that the driving ability of the PNP transistor (40) can be improved and the occupied area thereof can be reduced.

Further, a vertical PNP transistor (12)
Emitter region (28) and DMOSFET (13) P
Sharing the process with the ⁺ type body region (31) also has an advantage that the manufacturing process can be simplified.

[Brief description of drawings]

FIG. 1 is a cross-sectional view for explaining the present invention.

FIG. 2 is a first cross-sectional view for explaining the manufacturing method.

FIG. 3 is a second cross-sectional view for explaining the manufacturing method.

FIG. 4 is a third cross-sectional view for explaining the manufacturing method.

FIG. 5 is a fourth cross-sectional view for explaining the manufacturing method.

FIG. 6 is a fifth cross-sectional view for explaining the manufacturing method.

FIG. 7 is a sixth sectional view for explaining the manufacturing method.

FIG. 8 is a seventh cross-sectional view for explaining the manufacturing method.

FIG. 9 is an eighth sectional view for explaining the manufacturing method.

FIG. 10 is a ninth cross-sectional view for explaining the manufacturing method.

FIG. 11 is a circuit diagram showing an output stage inverter circuit.

FIG. 12 is a sectional view showing another embodiment of the present invention.

FIG. 13 is a cross-sectional view showing another part of the device of the present invention.

FIG. 14 is a circuit diagram showing a conventional output stage inverter circuit.

FIG. 15 is a circuit diagram showing a conventional output stage inverter circuit.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical indication location H03K 19/08 A 8941-5J 7377-4M H01L 29/72

Claims (4)

[Claims] 1. A semiconductor substrate of one conductivity type, first and second opposite conductivity type epitaxial layers sequentially stacked on the substrate, and formed at the boundary between the substrate and the first epitaxial layer. A plurality of reverse conductivity type buried layers, and a collector buried layer of a conductivity type transistor formed at the boundary between the first and second epitaxial layers and contacting the reverse conductivity type buried layer; A lower part of an isolation region which is formed at the same time as the conductivity type collector buried layer and forms a part of the isolation region of one conductivity type which penetrates the first and second epitaxial layers to form an island region; The second conductive layer is formed on the surface of the second epitaxial layer and is formed at the boundary between the first and second epitaxial layers and the upper portion of the isolation region that is connected to the lower portion of the isolation region, and the reverse conductivity type burying is performed. Border the layers A second reverse conductivity type buried layer,
A low-resistance take-out region formed on the surface of the second epitaxial layer and in contact with the second reverse-conductivity type buried layer, and a one-conductivity type transistor formed on the surface of the island region to form the other conductivity-type transistor. The base region and the emitter region of the opposite conductivity type are formed at the same time as the upper portion of the isolation region and are surrounded by the collector extraction region of the one conductivity type transistor connected to the collector buried layer and the collector extraction region. A DMOSFET formed on the surface of the base at the same time as the emitter region of the one conductivity type high conductivity one-conductivity type transistor formed on the surface of the base and on the surface of the island region at the same time as the emitter region of the one conductivity type transistor. And a body region of the one-conductivity-type diffusion region, the DMOSFE being integrally formed with the body region.
A channel region of the one-conductivity type diffusion region serving as a T channel and a DM formed on the surface of the one-conductivity type diffusion region.
DMOSFE disposed on the source region of the opposite conductivity type of the OSFET and the channel region via a gate insulating film
A semiconductor integrated circuit comprising a T gate electrode. 2. The vertical DMOSF in which the DMOSFET takes out a drain current through the reverse conductivity type buried layer.
The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is an ET. 3. The semiconductor integrated circuit according to claim 1, wherein the DMOSFET is a lateral DMOSFET that takes out a drain current from an opposite conductivity type drain region formed on the surface of the island region. 4. The one conductivity type transistor constitutes one transistor of an output stage inverter circuit,
2. The semiconductor according to claim 1, wherein the OSFET constitutes the other transistor of the output stage inverter circuit, and the connection point between the collector of the one conductivity type transistor and the drain of the DMOSFET is connected to the output terminal. Integrated circuit.