JPH053292A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To realize effective integration of a longitudinal PNP transistor and a DMOSFET which are suitable for an n-channel MOSFET and an output step inverter circuit. CONSTITUTION:First and second epitaxial layers 17, 18 are formed on a substrate 16, an N<+>-type buried layer 19 is formed on a surface of the substrate 16 and a P<+>-type collector buried layer 28 is formed on a surface of the first epitaxial layer 17. A P<+>-type emitter region 30 is formed on a surface of a region which becomes a base as a longitudinal PNP transistor 12. A body region 33 of a P<+>-type diffusion 32 is formed simultaneously with the P<+>-type emitter region 30. A P-type channel region 34 is formed integrally with the P<+>-type body region 33, and an N<+>-type source region 35 and a gate electrode 36 are formed as a DMOSFET 13. A P<+>-type buried layer 38 of an nMOSFET 11 is formed simultaneously with the collector buried layer 28 of the longitudinal PNP transistor 12.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a vertical PNP transistor and a DMOSFET (diffusion self-a).
The present invention relates to a semiconductor integrated circuit for forming an output stage inverter circuit in combination with an output MOSFET.

[0002]

2. Description of the Related Art With the development of Bi-CMOS technology in which bipolar elements and MOS elements are mixed, there is a movement to use DMOSFETs in the final stage of the output circuit of a semiconductor device.
As the output circuit, a CMOS inverter circuit in which a P-channel MOS and an N-channel MOS are combined is generally used, but a pMOSFET having the same size and size is usually used.
And nMOSFET are compared, the driving capability of pMOSFET is low due to the relation of carrier mobility.
The driving capability of T is only 1/3 to 1/2 that of nMOSFET.

Therefore, in the conventional output circuit, pMOSF is used.
In order to have the same driving capability for ET and nMOSFET, p
Since the size of the MOSFET is increased, the area of the output circuit is increased. In order to solve the above-mentioned problems, a method of replacing the pMOSFET with an NPN transistor has been proposed as described in, for example, Japanese Patent Laid-Open No. 2-264519. That is, as shown in FIG.
An inverter output circuit is formed by combining the OSFET (1) and the NPN transistor (2), and the nMOSF is connected to the base of the NPN transistor (2) via the inverter (3).
ET (1) is configured to give an input signal of opposite phase.

As another method, as shown in FIG.
Replace pMOSFET with nMOSFET (4)
Via the inverter (6) to the other nMOSFET (5)
Input the reverse phase signal to the external capacitor (7)
The replaced nMOSF via the boot circuit (8)
V on the gate of ET (4)_DD+ V_C(V_CIs an external capacitor
Gate voltage), which is the voltage due to the charge accumulated in
It has been proposed that it is configured to. NMOS
V to the gate of FET (4)_DD+ V_CMinute gate voltage
When the nMOSFET (4) is ON, the saw
(V_DD-I _DSr_DS) Minute voltage
This is for obtaining a wide output waveform.

[0005]

[Problems to be Solved by the Invention]
In the method, the emitter potential of the NPN transistor (2) is V
_B-V_BE(V_BIs the base potential, V_BEBetween base and emitter
Voltage) and V_BECannot be reduced
Therefore, there is a drawback that the output amplitude cannot be increased. One latter
Then, the boot circuit (8) eliminates the similar drawbacks.
Yes, but circuit to add an external capacitor (7)
Has the drawback of increasing complexity and costing the set
There is.

[0006]

The present invention has been made in view of the above-mentioned drawbacks, and a vertical PNP transistor (12) is provided.
And an n-channel DMOSFET (13) constitute an inverter output circuit. The first and second epitaxial layers (17) and (18) are laminated and a vertical PNP transistor (12) is formed at the boundary between the two. A P ⁺ -type collector buried layer (28) is formed, and the region surrounded by the collector lead-out region (29) is used as the base of the vertical PNP transistor (12), and the vertical PNP transistor (1
2) P ⁺ type emitter region (30) is formed, and simultaneously with the emitter region (30) of the vertical PNP transistor (12), the P ⁺ type diffusion region (3) of the DMOSFET (13) is formed.
The body region (33) of 2) is formed, and the body region (3) is formed.
The channel region (34) of the DMOSFET (13) is formed so as to be integrated with 3), and the P ⁺ type diffusion region (32) is formed.
An N ⁺ type source region (35) is formed on the surface of the gate electrode, a gate electrode (36) is formed on the channel region (34), and a collector buried layer (2) of the vertical PNP transistor (12) is formed.
Simultaneously with 8), a P ⁺ type buried layer (38) reaching from the surface of the first epitaxial layer (17) to the substrate (16) is formed, and an n channel type MOS is formed on the P ⁺ type buried layer (38). The transistor (11) is formed.

[0007]

According to the present invention, the first epitaxial layer (1
7) By forming the collector burying layer (28) on the surface, the collector series resistance is reduced and the saturation voltage V _{CE (sat)}
The vertical PNP transistor (12) having a small Further, since the emitter region (30) of the vertical PNP transistor (12) is formed with a high impurity concentration, the carrier (hole) emitter injection efficiency is increased, and the collector current can be increased (driving capability is increased). Type PNP transistor (12) can be provided.

Further, a vertical PNP transistor (12)
P ⁺ type emitter region (30) and DMOSFET (1
Since the P ⁺ type body region (33) of 3) is formed at the same time, the process can be simplified. Furthermore, since the P ⁺ type buried layer (38) of the n-channel MOSFET (11) is formed on the surface of the first epitaxial layer (17), P
The thickness of the ⁺ type buried layer (38) can be increased, the resistance component is reduced, and the parasitic effect is prevented.

[0009]

An embodiment of the present invention will be described in detail below with reference to the drawings. 1 is a sectional view showing an nMOSFET (11), a vertical PNP transistor (12), and a DMOSFET (13) in the semiconductor integrated circuit of the present invention, and FIG. 2 is an NPN transistor (14) and a pMO.
It is sectional drawing which shows SFET (15).

In these figures, (16) is a P-type silicon semiconductor substrate, (17) is an N-type first epitaxial layer laminated on the substrate (16), and (18) is a first epitaxial layer ( 17) N-type second epitaxial layer laminated on top, (19) is an N ⁺ -type buried layer buried in the surface of the substrate (16), and (20) is the first and second epitaxial layers ( 17) an isolation region for forming an island region penetrating (18), (21) an isolation region (20) formed from the surface of the first epitaxial layer (17)
Lower part, (22) is the second epitaxial layer (1
8) The upper part of the separation region (20) formed from the surface.

The main component of the NPN transistor (14) shown in FIG. 2 is formed from the surface of the first epitaxial layer (17) and is formed so as to be in contact with the N ⁺ type buried layer (19). 2 N ⁺ type buried layer (23),
The N ⁺ type collector low resistance region (24) formed to reach the second N ⁺ type buried layer (23) from the surface of the second epitaxial layer (18) and the P type of the P type formed on the surface of the island region. It comprises a base region (25) and an N ⁺ type emitter region (26) formed on the surface of the base region (25).
(27) is a P ⁺ type base contact region formed for taking out the base. By forming the second N ⁺ type buried layer (23) on the entire lower surface of the base region (25), the NPN transistor (14) is selected as a high-speed type and only in a portion corresponding to the collector low resistance region (24). These NPN transistors (14) can be respectively formed to have high breakdown voltage.

The vertical PNP transistor (1
The main component of 2) is the first epitaxial layer (1
P ⁺ type collector burying layer which is formed on the surface of 7) simultaneously with the lower part (21) of the isolation region (20) and is electrically separated from the substrate (16) by the N ⁺ type burying layer (19). (28) and the P ⁺ -type collector lead-out region (29) which is formed simultaneously with the upper part (22) of the isolation region (20) from the surface of the second epitaxial layer (18) and reaches the collector buried layer (28). ) And a collector buried layer (2
8) and the second epitaxial layer (18) completely surrounded by the collector lead-out region (29) as a base, and a P ⁺ -type emitter region (30) formed on the surface of the base and N serving as a base extraction. ⁺ Type base contact area (3
It consists of 1). A second N ⁺ -type buried layer (23) is arranged on both sides of the P ⁺ -type collector buried layer (28) to separate the collector buried layer (28) by autodoping and the collector buried layer (20). 28) to prevent short circuit. Further, if the N-type impurity is diffused from the surface into the region serving as the base, the speed of the vertical PNP transistor (12) is increased.

The vertical DMOSFET (13) shown in FIG.
The main component of the body region (33) of the P ⁺ type diffusion region (32) formed simultaneously with the P ⁺ type emitter region (30) of the vertical PNP transistor (12) on the surface of the island region.
And DMOSF integrated with the P ⁺ type body region (33)
P ⁺ type diffusion region (3
2) P-type channel region (34) and N ⁺ -type source region (35) formed on the surface of P ⁺ -type diffusion region (32)
And a polysilicon gate electrode (36) disposed on the channel region (34) via a gate oxide film.

The drain current is equal to the N ⁺ type buried layer (1
9) via the second N ⁺ type buried layer (23) formed on the surface of the first epitaxial layer (17) and the N ⁺ type low resistance region (37) formed on the surface of the second epitaxial layer (18). ) And take out from the surface at the drain electrode. The region for extracting the drain current is formed so as to surround the unit cell for each individual unit cell or for each unit cell. A source electrode that makes ohmic contact with both the N ⁺ type source region (35) and the P ⁺ type body region (33) is formed on the P ⁺ type diffusion region (32). Incidentally, D
N ⁺ type low resistance region (37) of MOSFET (13) and N
Collector low resistance region (2) of PN transistor (14)
4) is an area in which the process is shared.

The main components of the nMOSFET (11) shown in FIG. 1 are formed simultaneously with the collector buried layer (28) of the vertical PNP transistor (12), and are formed from the surface of the first epitaxial layer (17). A P ⁺ -type buried layer (38) reaching the substrate (16) and a P ⁺ -type buried layer (3) formed on the surface of the second epitaxial layer (18).
8), a P-type well region (39), and an N ⁺ -type source / drain region (40) simultaneously formed with the emitter region (26) of the NPN transistor (14) on the surface of the well region (39), The gate electrode (41) is formed on the channel portion sandwiched by the source / drain regions (40) via a gate oxide film. P-type well region (3
9), V _SS (GND) is formed by a P ⁺ -type contact region (not shown) provided outside the source / drain region (40).
A back gate voltage such as

The main components of the pMOSFET (15) shown in FIG. 2 are the N-type well region (42) formed on the surface of the second epitaxial layer (18) corresponding to the N ⁺ -type buried layer (19). ) And a P ⁺ type source / drain region (43) formed simultaneously with the emitter region (30) of the vertical PNP transistor (12) on the surface of the well region (42).
And a gate electrode (44) formed on the channel portion sandwiched by the source / drain regions (43) via a gate oxide film. The vertical PNP transistor (1
If the base of 2) is formed by diffusion, pMOSFET
It can be shared with the well region (42) of (15).

A method of manufacturing the above semiconductor integrated circuit will be described with reference to FIGS. 3 to 11 are cross-sectional views of the portion shown in FIG. 1 at each manufacturing stage, and the portion shown in FIG. 2 is omitted. (A) First, antimony (Sb) for forming the N ⁺ type buried layer (19) on the surface of the P type semiconductor substrate (16)
Are selectively diffused (FIG. 3).

(B) An N type first epitaxial layer (17) having a thickness of 5 to 7 μ is laminated on the surface of the substrate (16) by an epitaxial growth method. Then, boron (B) is selectively diffused on the surface of the first epitaxial layer (16) to form a lower portion (21) of the isolation region (20) and a collector buried layer (28) of the vertical PNP transistor (12). ), And the P ⁺ type buried layer (3) of the nMOSFET (11).
8) is formed (FIG. 4).

(C) Next, antimony (Sb) is diffused on the surface of the first epitaxial layer (17) to form the second N ⁺ type buried layer (23) of the vertical PNP transistor (12) and the DMOSFET. Second N ⁺ of (13)
A mold embedding layer (23) is formed (FIG. 5). At that time, in the portion shown in FIG. 2, the NPN transistor (1
4) The second buried layer (23) is formed.

(D) First by epitaxial growth method
The N-type second epitaxial layer (18) having a thickness of 8 to 12 μ is laminated on the surface of the epitaxial layer (17). Then, the surface of the second epitaxial layer (18) is selectively doped with phosphorus (P) or arsenic (As) to form a DMOS.
A low resistance region (37) of the FET (13) is formed. Figure 2
In the NPN transistor (14), the collector low resistance region (24) is formed. Next, in FIG. 1, the P-type well region (39) of the nMOSFET (11) is
In FIG. 2, the N-type well region (42) of the pMOSFET (15) is formed (FIG. 6). In addition, if a heat treatment for diffusing the lower part (21) of the separation region (20) upward is performed after this, the upper part (2) of the separation region (20) is
The diffusion depth of 2) can be made shallow.

(E) Selectively diffusing boron (B) forming the upper part (21) of the isolation region (20) on the surface of the second epitaxial layer (18), and performing extension diffusion by heat treatment. Connects the upper part (22) and the lower part (21) of the separation area (20) (FIG. 7). P-type well region (3
9) and the P ⁺ type buried layer (38), the collector lead-out region (29) and the collector buried layer (28) of the vertical PNP transistor (12), and the low resistance region (37) of the DMOSFET (13) and the second. The N ⁺ type buried layers (23) are also connected to each other. The collector buried layer (28) of the vertical PNP transistor (12) is an N ⁺ type buried layer (19).
Are electrically separated from the substrate (16). In the portion of FIG. 2, the collector low resistance region (24) of the NPN transistor (14) and the second N ⁺ -type buried layer (2
3) and the N-type well region (42) of the pMOSFET (15) is diffused into the epitaxial layer.

(F) A gate oxide film having a film thickness of 200 to 600 Å is formed on the surface of the second epitaxial layer (18),
Polysilicon having a film thickness of 1.0 to 2.0 μ is deposited thereon,
Photoetching is performed to form a gate electrode (36) (FIG. 8). a gate electrode (41) of the nMOSFET (11),
And the gate electrode (44) of the pMOSFET (15) is also formed at the same time.

(G) A selective mask is formed on the surface of the second epitaxial layer (18), and boron (B) is selectively diffused by an ion implantation method or the like to form an emitter region (30) of the vertical PNP transistor (12). ), And DMOS
A body region (33) of the FET (13) is formed (FIG. 9). These areas have a surface sheet resistance of 10 to 20.
It is formed in a region having a sufficiently high impurity concentration of Ω · cm. Figure 2
In, the base contact region (27) of the NPN transistor (14) and the source / drain region (43) of the pMOSFET (15) are simultaneously formed. Incidentally, the order of forming the gate electrodes (36) (41) and this step can be reversed.

(H) A part of the selection mask is changed and DMO is changed.
While using the gate electrode (36) of the SFET (13) as a part of the mask, the channel region (3) of the DMOSFET (13) is selectively diffused by boron (B).
4) is formed (FIG. 10). In FIG. 2, the base region (25) of the NPN transistor (14) is simultaneously formed. Channel region (34) of DMOSFET (13)
The boron (B) forming the P is a P ⁺ type body region (33)
In the base region (25) of the NPN transistor (14)
The boron (B) forming the layers is introduced into the P ⁺ type base contact region (27) in an overlapping manner. In addition, vertical PNP
It may be overlapped with the P ⁺ type emitter region (30) of the transistor (12). The impurity concentration of boron (B) introduced in this step is lower than that of the emitter region (30) of the vertical PNP transistor (12), and the sheet resistance is 100 to 100.
It is 200 Ω · cm.

(I) The selection mask is changed and DMOSFE
At T (13), again using the gate electrode (36) as a part of the mask, phosphorus (P) or arsenic (As) is selectively diffused from the surface to form a base contact region (31) of the vertical PNP transistor (12). A source region (35) of the DMOSFET (13) and a source / drain region (40) of the nMOSFET (11) are formed (FIG. 11). In the portion of FIG. 2, the emitter region (26) of the NPN transistor (14) is formed in this step. After this,
The semiconductor integrated circuit of the present invention is manufactured by disposing Al electrodes and the like.

FIG. 12 shows an output stage inverter circuit which can be constructed by the device of the present invention. This circuit includes a PNP transistor (50) replaced by a vertical PNP transistor (12) instead of a pMOSFET, and a DMOSFET.
NMOS transistor formed by (13) (5
1) and a PNP transistor (5
0) applies the same input signal to the base of the nMOS transistor (51) and the gate of the nMOS transistor (51),
The output signal is taken out from the connection point between the collector of 0) and the drain of the nMOS transistor (51), the nMOS transistor (51) is turned on when the input signal is positive, and the PNP transistor (50) is turned on when the input signal is negative. It is configured to be turned on to drive a load. In this case, the minimum level of the output waveform is determined by the ON resistance R _DS of the nMOS transistor (51), and the maximum level of the output waveform is determined by the saturation voltage V _{CE (sat )} of the PNP transistor (50). An output amplitude that makes the most effective use of the potential difference (V _DD −V _SS ) is obtained, and the drive capability of the output circuit is high.

In the vertical PNP transistor (12) of the present invention, the collector buried layer (28) is formed from the surface of the first epitaxial layer (17),
Since the collector buried layer (28) can be thickened to reduce the collector series resistance r _C , its saturation voltage V
_{CE (sat)} can be made sufficiently small. Therefore, the amplitude of the output waveform can be further increased.

Further, in the vertical PNP transistor (12) of the present invention, since the emitter is the P ⁺ type emitter region (30) having a higher impurity concentration than the base region (25) of the NPN transistor (14), The carrier (hole) injection efficiency to the base can be increased and the collector maximum current I _Cmax of the transistor can be increased. Therefore P
By increasing the driving capability of the NP transistor (50), n
The area occupied by the PNP transistor (50) can be reduced when the driving capability is made equal to that of the MOS transistor (51).

Further, a vertical PNP transistor (12)
P ⁺ type emitter region (30) and DMOSFET (1
Since the process of 3) and the P ⁺ type body region (33) is shared, the process can be simplified. And further, nMOSF
In the ET (11), since the P ⁺ type buried layer (38) is formed on the surface of the first epitaxial layer (17),
The thickness can be increased, and the resistance of the P ⁺ -type buried layer (38) in the lateral direction of the drawing can be reduced. Therefore, the entire P-type well region (39) can be uniformly maintained at the back gate voltage, and the leakage current from the channel and the source / drain regions (40) can be absorbed by the bias voltage, so that the parasitic effect can be prevented. Can be increased.

FIG. 13 shows a second embodiment of the present invention.
While the DMOSFET (13) in FIG. 1 is a vertical DMOS that takes out a drain current through the buried layer (19), the present embodiment has an N ⁺ -type drain region (53) provided at a position opposite to the channel region. ) Is a lateral DMOS that extracts the drain current. The N ⁺ type drain region (53) is formed at the same time as the emitter region (26) of the NPN transistor (14), and channel current flows from the channel region (34) to the second epitaxial layer (18) below the gate electrode (36). ) It is called a lateral DMOS because it flows laterally through the surface. Other configurations and operational effects are the same as in FIG.

[0031]

As described above, according to the present invention, P
NP transistor (50) and nMOS transistor (5
This has the advantage that an inverter output circuit combining 1) and 1) can be configured in an integrated circuit. Moreover, the vertical PNP transistor (1
Since the saturation voltage V _{CE (sat)} of 2) can be reduced, the amplitude of the output waveform can be further increased, and the emitter can be made to have a higher impurity concentration than the base region (25) of the NPN transistor (14), so that PNP can be obtained. Transistor (50)
Has the advantage that the drive capacity of the device can be improved and its occupied area can be reduced.

Further, a vertical PNP transistor (12)
Emitter region (30) and P of DMOSFET (13)
Sharing the process with the ⁺ type body region (33) also has an advantage that the manufacturing process can be simplified. Further, the source / drain region (4
0) is the emitter region (2) of the NPN transistor (14).
6) and the P ⁺ -type buried layer (38) of the nMOSFET (11) are shared with the collector buried layer (28) of the vertical PNP transistor (12), respectively.
The OSFET (11) can be easily incorporated, and since the P ⁺ type buried layer (38) is formed on the surface of the first epitaxial layer (18), the thickness can be increased,
It also has the advantage that the parasitic effect can be increased.

[Brief description of drawings]

FIG. 1 is a first sectional view illustrating the present invention.

FIG. 2 is a second sectional view illustrating the present invention.

FIG. 3 is a first cross-sectional view explaining the manufacturing method.

FIG. 4 is a second cross-sectional view illustrating the manufacturing method.

FIG. 5 is a third cross-sectional view explaining the manufacturing method.

FIG. 6 is a fourth cross-sectional view illustrating the manufacturing method.

FIG. 7 is a fifth cross-sectional view illustrating the manufacturing method.

FIG. 8 is a sixth sectional view illustrating the manufacturing method.

FIG. 9 is a seventh cross-sectional view illustrating the manufacturing method.

FIG. 10 is an eighth cross-sectional view explaining the manufacturing method.

FIG. 11 is a ninth cross-sectional view explaining the manufacturing method.

FIG. 12 is a circuit diagram showing an output stage inverter circuit.

FIG. 13 is a sectional view showing another embodiment of the present invention.

FIG. 14 is a circuit diagram showing a conventional output stage inverter circuit.

FIG. 15 is a circuit diagram showing a conventional output stage inverter circuit.

Claims (4)

[Claims] 1. A semiconductor substrate of one conductivity type, first and second opposite conductivity type epitaxial layers sequentially stacked on the substrate, and formed at the boundary between the substrate and the first epitaxial layer. A plurality of reverse conductivity type buried layers, and a collector buried layer of a conductivity type transistor formed at the boundary between the first and second epitaxial layers and contacting the reverse conductivity type buried layer; A lower part of an isolation region which is formed at the same time as the conductivity type collector buried layer and forms a part of the isolation region of one conductivity type which penetrates the first and second epitaxial layers to form an island region; An upper part of the isolation region formed from the surface of the second epitaxial layer and connected to the lower part of the isolation region, and an upper part of the isolation region formed at the same time and connected to the collector buried layer. Type A collector lead-out region of the transistor; an emitter region of a one-conductivity-type one-conductivity-type transistor formed on the surface of the base with a region surrounded by the collector lead-out region as a base;
Formed on the surface of the epitaxial layer simultaneously with the emitter region of the one conductivity type transistor
A body region of the one-conductivity type diffusion region, a channel region of the one-conductivity type diffusion region that is integrally formed with the body region and serves as a channel of the DMOSFET, and a A source region of opposite conductivity type, a gate electrode of a DMOSFET provided on the channel region via a gate insulating film, and a collector buried layer of the one conductivity type transistor are formed simultaneously, and the first epitaxial layer is formed. One conductivity type buried layer reaching from the surface to the surface of the substrate, one conductivity type well region formed on the surface of the second epitaxial layer corresponding to the one conductivity type buried layer, and formed on the surface of the well region. A reverse-conductivity type source / drain region and a gate insulating film on the channel part sandwiched by the source / drain region. The semiconductor integrated circuit characterized by comprising a gate electrode formed via. 2. The vertical DMOSF in which the DMOSFET takes out a drain current through the reverse conductivity type buried layer.
The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is an ET. 3. The semiconductor integrated circuit according to claim 1, wherein the DMOSFET is a lateral DMOSFET that takes out a drain current from an opposite conductivity type drain region formed on the surface of the island region. 4. The one conductivity type transistor constitutes one transistor of an output stage inverter circuit,
2. The semiconductor according to claim 1, wherein the OSFET constitutes the other transistor of the output stage inverter circuit, and the connection point between the collector of the one conductivity type transistor and the drain of the DMOSFET is connected to the output terminal. Integrated circuit.