JPH02370A - Integrated circuit device - Google Patents

Abstract

PURPOSE:To minimize effect of output current from a vertical MOSFET to a control circuit, by forming a deep P-type diffused layer between the vertical MOSFET and an integrated circuit. CONSTITUTION:A multiplicity of circuit elements including a vertical MOSFET 23 having a current passage extending from one principal surface to the other principal surface of a semiconductor substrate 1 of one conductivity type are formed in the same semiconductor substrate 1. A deep dopant diffused region 12 of the other conductivity type is provided between the vertical MOSFET and the other circuit elements. This deep dopant diffused region 12 limits the passage of output current from the vertical MOSFET, so that effect to the other circuit elements is decreased.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to an integrated circuit device in which a plurality of circuit elements including a vertical MOSFET are formed on the same chip. The present invention relates to a structure that separates circuit elements from each other.

[Conventional technology]

In recent years, vertical MOSFETs have been used as switching elements for driving various on-vehicle power loads such as automobile lamps and solenoids and relays.

Recently, since the manufacturing processes of vertical MOSFET and 0MO8IC are compatible, a vertical MO3FET and multiple peripheral circuit elements are formed on the same chip, and these peripheral circuit elements are used to control current limiting circuit, heating detection circuit, overvoltage Integrated circuit devices have been proposed in which various protection circuits such as detection circuits are formed to protect vertical MOSFETs from large currents or high voltage surges when a load is short-circuited.

In an integrated circuit device in which a large number of other circuit elements are formed on the same chip along with a vertical MOSFET, the vertical MOSFET for output
Structures for separating OSFETs from other circuit elements include insulation separation and dielectric separation.

Figure 5 is an example of insulation separation (IEEE 1987
CLISTOM INTEGRATED CIRCUI
(See T C0NPERENCEP, 276). FIG. 6 shows an example of dielectric separation (see Japanese Patent Laid-Open No. 196576/1983).

[Problem to be solved by the invention]

The conventional separation techniques described above have the drawbacks of complicated processes and high production costs.

For example, if we take the insulation isolation shown in Figure 5 as an example, N+ substrate l has N
A + buried layer 51 is provided, a P- type epitaxial layer 52 is deposited thereon, an N-type epitaxial layer 3 is further deposited, and P-type impurities are diffused from the surface to form a P-type diffusion layer 53 for insulation isolation. It requires a complicated process of forming.

In addition, the dielectric isolation shown in FIG. 6 is achieved by oxidizing the back surface of the N+ substrate 63 to form an internal oxide film 62 for isolation.
After partially etching the isolation internal oxide film 62 in the area where the N+ substrate 63 is to be formed, an N+ polysilicon layer 61 is deposited on the back side of the N+ substrate 63, and then an N+ polysilicon layer 61 is deposited on the surface of the N+ substrate 63.
-Layer epitaxial layer 3 and finally trench groove 64
Insulation is performed by digging a trench and burying a PSG film 11 in the trench. This method uses technically difficult steps such as the need to align the back and front sides of the substrate and the need to dig deep trenches 64.

Now, as shown in Figures 5 and 6, the vertical MOSFET uses its N+ substrate as the drain region, so a load is connected to the positive power supply line, and the drain of the vertical MOSFET used as a switching element is connected to this load. When the drain is used as an output terminal, such as in a so-called low-side switch where the source is connected to the ground and the source is grounded, a vertical MO
The voltage at the drain electrode of the SFET changes depending on the output state. On the other hand, the substrate potential and well potential of the peripheral CMO3 control circuit need to be fixed, and therefore the substrate and well of the peripheral circuit need to be separated from the drain region of the vertical MOSFET.

Therefore, it is necessary to electrically insulate and separate the vertical MOSFET from other circuit elements using the above-mentioned insulation isolation, dielectric isolation, or other structures.

By the way, in the electric circuit of an automobile, the body of the automobile itself is used as a ground electrode for the purpose of reducing wiring (wire harness). On the other hand, if a load such as a car lamp or solenoid relay is connected to the positive power supply line, there is a risk of a fire occurring when the load touches the car body, which is a ground electrode. Therefore, for safety, a method is adopted in which these loads are connected to the ground side and the switching elements that drive the loads are connected to the positive power supply line. This method of grounding the load and connecting the switching element to the power supply line is called a 7% aside switch.

The high-side switch is N-channel type (N ch
) When configured with a vertical MOSFET, its drain is connected to the positive power supply side, its source becomes an output terminal, and is connected to one electrode of various on-vehicle power loads such as automobile lamps and solenoid relays.

Note that in order to completely turn on such an Nch vertical MO3FET, it is necessary to make the gate voltage higher than the power supply voltage, but this can be easily done using a booster circuit.

In this way, in high-side switches, etc., the output terminal becomes the source electrode, and the potential of the drain electrode is fixed to the common power supply voltage with other circuit elements, so it is not always necessary to separate the elements by electrically insulating them. There isn't. Therefore, it is possible to form the vertical MOSFET and other circuit elements on a common substrate.

However, vertical MO3F as an output transistor
Since ET switches high voltages and large currents, it is necessary to devise the structure and arrangement of the elements so as not to affect other circuit elements. It is necessary to create a structure that requires less.

[Means to solve the problem]

According to the present invention, a large number of circuit elements including a vertical MOSFET having a current path on a main surface other than one main surface of a -conductivity type semiconductor substrate are formed on the same semiconductor substrate, and a vertical MOSFET is formed on the same semiconductor substrate.
An integrated circuit device having a deep impurity diffusion region of another conductivity type between a FET and another circuit element is obtained.

In the present invention, unlike the conventional technology, the vertical MOSFET and the integrated circuit are not electrically insulated and separated, but the output current path of the vertical MOSFET is limited by a deep P-type diffusion layer, so that other circuit elements can be connected to each other. It has a simpler structure and is easier to manufacture.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a sectional view of a first embodiment of the invention.

An epitaxial wafer in which an N type epitaxial layer 13 is stacked on an N+ substrate 1 is used. This is the same as that used when creating a discrete vertical MOSFET. However, when forming the deep P-type diffusion region 12 later, impurity diffusion occurs from the N+ substrate 1 and an N+ rising region 2 is formed, reducing the effective thickness of the N- epitaxial film. The thickness of the epitaxial layer 13 is set to be thicker than when manufacturing a discrete vertical MOSFET. Since the breakdown voltage normally required for a semiconductor device for use in a vehicle is around 60V, the resistivity of the epitaxial layer is about 1Ω·cm. Epitaxial layer 1 before pressing P type diffusion layer 12 required at this time
The thickness of No. 3 is about 20 to 30 μm.

Poron is injected between the vertical MOSFET 23 and the control circuit 26 by ion implantation or the like, and deep P-type diffusion regions 12 for element isolation are formed by injecting at a high temperature.

By performing the embedding at a high temperature for a long time, impurities are diffused from the N- substrate 1, and an N+ rising region 2 is formed. A deep P-type diffusion region 12 for element isolation is formed on an epitaxial film 13 so as to be in contact with this N+ rising region 2.
Set the film thickness and embedding time. Resistivity 1Ω・cm.

In the case of an epitaxial wafer in which the thickness of the epitaxial film 13 before indentation is 25 μm, the temperature is 1200°C.

After 50 hours of pressing, the thickness of the N+ rising region 2 becomes approximately 13 μm. Poron ion implantation amount is 1.5
When X is 1013 cm-', the depth of the deep P-type diffusion region 12 is about 11 μm. After that, vertical MOS
FET 23 and control circuit 26 are formed.

FIG. 2(a) shows a cross-sectional view of an integrated circuit device having a shallow P-type diffusion region 36 between it and a control circuit for a vertical MOSFET. N-channel MOSFET 25 shown in Figure 1
is omitted. Since the switch shown in the figure is a high-side switch, the drain 14 of the vertical MOSFET and the source 19 of the P-channel MO3FET are connected to a power supply 35, and the source 16 of the vertical MOSFET is connected to a load resistor 34. Since the P-type diffusion region 36 is shallow, the base of the parasitic bipolar transistor 33 and the epitaxial resistor 30 of the vertical MO3FET are connected through the epitaxial resistor 31 under the shallow P-type diffusion region 36.

When the output current of the vertical MOSFET increases, the vertical MOSFET
The voltage drop across the ET epitaxial resistor 30 increases,
Since the base of parasitic bipolar transistor 33 is negatively biased with respect to its emitter, parasitic bipolar transistor 33 is turned on.

The current flowing at this time acts as a trigger and causes the control circuit to latch up. To avoid latch-up, it is necessary to widen the width of the shallow P-type diffusion region 360 and make the epitaxial resistance 31 at the bottom of the shallow P-type diffusion region 36 larger than the base resistance 32 of the bipolar transistor. This results in an increase in area.

On the other hand, in FIG. 2(b), the deep P-type diffusion region 12 reaches the N+ rising region 2, so the vertical MOSFE
The output current of T has no effect on the control circuit side.

The base of the parasitic bipolar transistor 33 is connected to the N+ rising region 2 through the base resistor 32, and since this region has a relatively high impurity concentration, it is always biased to the power supply voltage VDD. Therefore, the parasitic bipolar transistor 33 is never turned on. Also, the second
The chip area does not increase as in the case where the P-type diffusion region is shallow as shown in FIG.

When the resistivity of the epitaxial layer 13 is 1 Ω·cm and the thickness is 25 μm before the P-type head region 12 is pushed in, the depth of the deep P-type diffusion region 12 is about 11 μm as described above. If the width of the diffusion region 12 is set to 15 μm or more, latch-up of the control circuit can be avoided.

Note that the deep P-type diffusion region 12 and the N+ rising region 2
Even if they come into contact, the withstand voltage is unlikely to drop because the bond is an inclined bond. Under the above-mentioned diffusion conditions, a withstand voltage of around 180V is generated, and there is no particular problem in application.
The impurity concentration profile below the type diffusion region 12 is shown. Figure 2 (C) is before pushing, Figure 2 (d) is 750 minutes,
FIG. 2(e) shows the impurity profile after the P-type diffusion region 36 was pushed in for 3000 minutes. The push is 12
The test was carried out in an inert gas at 00°C.

Since the N+ substrate 1 becomes the drain electrode of the vertical MOSFET, it has a resistivity of 0006 to 0.0, making it easy to establish ohmic contact.
Use one with 30Ω·cm. The impurity concentration is 10'a~lO''cm-3, and antimony (Sb), which has a relatively small diffusion coefficient, is used as the impurity. Concentration 5.
A 25 μm thick epitaxial layer 13 of 6×10 ”cm” was deposited.The impurity was phosphorus (P) (see Fig. 2(
C)).

Figure 2(d) shows the profile when boron was ion-implanted at a dose of 1.5 x 1013 cm-2 and then pressed in an inert gas at 1200°C for 750 minutes.
The profile when pressed for 00 minutes is shown in FIG. 2(e).

Here, the depth from the surface of the PN junction is assumed to be Xj.

In addition, the effective epitaxial film thickness Xe from the surface to N
It is defined as the distance to the point where the concentration of the type region becomes equal to the concentration of the initial epitaxial layer 13. When pushing for 750 minutes, Xj=7. ! lJum, Xe = 15.9 μm, and the ratio of the PN junction depth Xj to the effective epitaxial film thickness Xe is approximately 50%, which is relatively small (see Figure 2).
d)). As a result, the concentration of the N- region 3 sandwiched between the P-type diffusion region 36 and the N+ rising region 2 is approximately equal to the concentration of the initial epitaxial layer 13. In such a case, the resistance 31 at the bottom of the shallow P-type diffusion region 36 shown in FIG. 2(a) and the base resistance 32 of the parasitic bipolar transistor will have approximately the same magnitude, and the latch-up capacitance caused by turning on the parasitic bipolar transistor will be reduced. I'm concerned.

On the other hand, in the case of pushing for 3000 minutes, X j = 10.
4 μin, Xe = 15.9 μm, and the ratio of the PN junction depth Xj to the effective epitaxial film thickness Xe reaches approximately 80% (FIG. 2(e)). Depth X of PN junction with respect to effective epitaxial film thickness Xe
When the ratio of j is large (X j / considerably lower than that of Therefore, the second
The resistance corresponding to the epitaxial resistance 31 under the shallow P-type diffusion region 36 shown in FIG.
The value of is negligible compared to that, and latch-up due to parasitic bipolar turning on can be prevented.

Note that the N+ substrate l needs to have a high impurity concentration in order to make ohmic contact with the drain electrode 14, and preferably one with an impurity concentration of 1017 to 1020 cm'' is used. Furthermore, in order to prevent the wafer from cracking or chipping, a certain degree of thickness is required, and preferably 200 mm.
~900 μm is used.

In addition, in order to produce a withstand voltage of 50 to 250V, P+ region 1
The thickness of the epitaxial layer 13 before pressing 2 is 20 to 3
0μm, its impurity concentration is 15'8~10I60ff
! -3 is preferable.

Further, the depth of the deep P-type diffusion region 12 is 5 to 20 μm, the width is 10 μm or more, and the impurity concentration on the surface is 1015 to 20 μm.
10"cm" is preferably chosen. The thickness of the N+ rising region 2 is preferably set to 5 to 25 μm.

In this case, the depth of the deep P-type diffusion region 12 is defined as Xj,
The thickness of the epitaxial layer 13 before indentation is Xepi,
Assuming that the thickness of the N+ rising region 2 is XN, this is a cross-sectional view of an example of the resistance R8 at the bottom of the P-type diffusion region 12. N
Channel MO3) transistor (N c h MO8T
r) Since the P-well 40 is formed simultaneously with the deep P-type diffusion region 12 for element isolation, the number of steps can be reduced.

Furthermore, since this P-type diffusion region has a width of, for example, about 10 μm, it may be of an offset gate type or a fourth type as shown in FIG.
It is possible to form a high voltage Nch MOSFET such as a double doped drain type (DDD type) as shown in the figure. Even if the depth of the junction of the drain diffusion region 41 is increased to, for example, about 3 μm in order to reduce the electric field in the drain region and increase the voltage, the depth of the P-type diffusion region 40 is about 10 μm, which makes the contact with the substrate difficult. There will be no punch-through in between.

〔Effect of the invention〕

As explained above, the present invention suppresses the influence of the output current of the vertical MOSFET on the control circuit by a simple and inexpensive method of forming a deep P-type diffusion layer between the vertical MOSFET and the integrated circuit. It has the effect of

[Brief explanation of the drawing]

Fig. 1 is a sectional view of the first embodiment of the present invention, Fig. 2(a)
, (b) are cross-sectional views when the depth of the P-type diffusion region is shallow and deep, respectively, Figures 2 (c) to (e) are diagrams showing impurity profiles, and Figures 3 and 4 are cross-sectional views, respectively, of the present invention. FIG. 5 is a cross-sectional view of a conventional insulation isolation structure, and FIG. 6 is a cross-sectional view of a conventional dielectric isolation structure. DESCRIPTION OF SYMBOLS 1...N+ substrate, 2...N+ rising region, 3...N- epitaxial layer, 4...
...P well for Nch MOSFET, 5...
...P base, 6...N+ diffusion layer, 7...
...P+ diffusion layer, 8... Gate oxide film, 9...
... Oxide film, 10 ... Polysilicon gate, 11 ... PSG film, 12 ... Deep P
Type diffusion region, 13... Epitaxial layer before indentation, 14... Drain of vertical MOSFET,
15...Gate of vertical MOSFET, 16...
...Vertical MO3FET source, l 7=...-
Pch MOSFET drain, 18=-・Pch
Gate of MOSFET, 1'9-Pc hMO
3FET source, 20-N ch MOS F E
Drain of T, 21...Nch MOSFET
gate, 22... source of Nch MOSFET, 23... vertical MOSFET, 24...
...Pch MOSFET. 25...Nch MOSFET, 26...
... Control circuit, 30 ... Epitaxial resistance of vertical MOSFET, 31 ... Epitaxial resistance under the shallow P-type diffusion region, 32 ... Base resistance of parasitic bipolar transistor , 33...
Parasitic bipolar transistor, 34...Load resistance, 35...Power supply, 36...Shallow P
Uzuru, 4・O-...P for Nch MOSFET
Two. 41...Drain diffusion region of Nch MOSFET, 42...Offset resistance of Nch MOSFET, 43...Nch MOSFET
(offset gate type), 44...Pch M
Drain diffusion region of OSFET, 45...Pc
hMOSFET offset resistance, 46...P
ch MOSFET (offset gate type), 47-N
ch MOSFET (double doped drain type), 4
8--Pch MOSFET (double doped drain type), 51...N+ buried layer, 52...
P- epitaxial layer, 53...Insulating P-type diffusion layer, 61...N+ polysilicon layer, 62...
...Separation internal oxide film, 63...N+ substrate,
34...Separation groove.

Claims (1)

[Claims] In an integrated circuit device in which a plurality of circuit elements including vertical MOSFETs are formed on a semiconductor substrate of one conductivity type, and the circuit elements are interconnected, a semiconductor substrate of another conductivity type is disposed between the vertical MOSFET and another circuit element. An integrated circuit device characterized by having a diffusion region of