JPH05326520A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH05326520A
JPH05326520A JP12376092A JP12376092A JPH05326520A JP H05326520 A JPH05326520 A JP H05326520A JP 12376092 A JP12376092 A JP 12376092A JP 12376092 A JP12376092 A JP 12376092A JP H05326520 A JPH05326520 A JP H05326520A
Authority
JP
Japan
Prior art keywords
heat
film
semiconductor device
bumps
bump
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12376092A
Other languages
Japanese (ja)
Inventor
Satoshi Oe
聡 大江
Atsushi Miki
淳 三木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Sumitomo Electric Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Priority to JP12376092A priority Critical patent/JPH05326520A/en
Publication of JPH05326520A publication Critical patent/JPH05326520A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To provide a semiconductor device of a structure wherein heat generated in the semiconductor device is efficiently dissipated. CONSTITUTION:A semiconductor element 1 containing GaAs (The heat conductivity is 0.46W/cm deg.C) as its main component is formed and bumps 4 and 5 for connection with the outside are respectively formed via pads 31 and 32. A region excluding the bumps 4 and 5 is covered with a passivation film 2 consisting of an insulative SiO2 film (the heat conductivity is 0.14W/cm deg.C) for the protection and stability of a circuit. Moreover, a heat conduction film 6 consisting of a gold film (the heat conductivity is 3.1W/cm deg.C) is formed on this film 2 without being jointed with the bump 4 for electrode terminal use and being jointed with the bump 5 for heat conduction use. As the heat conductivity of the whole semiconductor element can be made to rise, a heat dissipation effect can be increased in a semiconductor device of a structure, wherein a flip-chip mounting is performed, without requiring other heat dissipation means. Thereby, a semiconductor device having power consumption higher than that of a conventional semiconductor device can be realized.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明はフリップチップ方式によ
り実装を行う半導体装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device mounted by a flip chip method.

【0002】[0002]

【従来の技術】電子機器の高性能化、多機能化に伴っ
て、これらの電子回路に用いられる集積回路においても
高速化、高密度化が進んできている。この結果、半導体
素子の高集積化が進み、これに伴い、外部回路との接続
端子数の増加および高密度実装に対応する技術が求めら
れるようになってきた。この要求に応える実装技術とし
てはフリップチップ方式がある。しかしながら、集積回
路の高密度化が進むにつれて、半導体チップの発熱密度
も多くなり、機器の性能を十分に発揮するためには、電
子回路の熱放散についてさらに考慮する必要がある。従
来技術については、IEEE TRANSACTION
S ON COMPONENTS,HYBRIDS,A
ND MANUFACTURING TECHNOLO
GY,VOL.12,NO.2,JUNE 1989に
記載されている。
2. Description of the Related Art With the increase in performance and multi-functionality of electronic equipment, the speed and density of integrated circuits used in these electronic circuits have been increasing. As a result, the degree of integration of semiconductor elements has increased, and along with this, there has been a demand for a technique that is compatible with an increase in the number of connection terminals with external circuits and high-density mounting. A flip-chip method is a mounting technology that meets this demand. However, as the density of the integrated circuit increases, the heat generation density of the semiconductor chip also increases, and in order to fully exhibit the performance of the device, it is necessary to further consider the heat dissipation of the electronic circuit. For conventional technology, see IEEE TRANSACTION
S ON COMPONENTS, HYBRIDS, A
ND MANUFACTURING TECHNOLO
GY, VOL. 12, NO. 2, JUNE 1989.

【0003】[0003]

【発明が解決しようとする課題】フリップチップ方式に
よる実装を行う従来の半導体装置を図2に示す。
FIG. 2 shows a conventional semiconductor device which is mounted by the flip chip method.

【0004】この図に示すように、半導体装置内で発生
した熱の大部分は半導体素子1またはパッシベーション
膜2を通して、熱伝導用バンプ5に伝わることになる。
従って、半導体素子1にGaAs(熱伝導率0.46W
/cm℃)、また、パッシベーション膜2にSiO
2 (熱伝導率0.14W/cm℃)の様な低熱伝導物質
を使用していると、素子内の発熱部から熱伝導用バンプ
5までの熱伝達が良好に行われず、素子の熱伝導率が低
下してしまうという課題があった。
As shown in this figure, most of the heat generated in the semiconductor device is transferred to the heat conduction bumps 5 through the semiconductor element 1 or the passivation film 2.
Therefore, GaAs (thermal conductivity 0.46 W
/ Cm ° C.) and SiO on the passivation film 2
If a low thermal conductivity material such as 2 (thermal conductivity 0.14 W / cm ° C) is used, heat transfer from the heat generating part in the element to the heat conduction bumps 5 will not be performed well, and the heat conduction of the element will not occur. There was a problem that the rate would decrease.

【0005】本発明は以上の問題に鑑み、半導体装置内
で発生した熱を効率良く熱放散させる装置を提供するこ
とを目的とする。
In view of the above problems, it is an object of the present invention to provide a device which efficiently dissipates heat generated in a semiconductor device.

【0006】[0006]

【課題を解決するための手段】以上の問題を解決するた
め本発明は、半導体素子の上に熱伝導用バンプと電極端
子用バンプとパッシベーション膜とが形成されている半
導体装置において、さらにパッシベーション膜上の所望
の領域に熱伝導性の優れた物質である熱伝導膜が被着さ
れている構造を有し、記熱伝導膜と熱伝導用バンプとは
接合され、熱伝導用バンプと電極端子用バンプとは電気
的に絶縁されていることを特徴とする。さらにこの熱伝
導膜が金またはダイヤモンドの薄膜であることを特徴と
してもよい。
In order to solve the above problems, the present invention provides a semiconductor device in which bumps for heat conduction, bumps for electrode terminals, and a passivation film are formed on a semiconductor element. It has a structure in which a heat conductive film, which is a substance having excellent heat conductivity, is adhered to a desired region above, the heat conductive film and the heat conductive bumps are bonded, and the heat conductive bumps and the electrode terminals are connected. It is characterized in that it is electrically insulated from the use bump. Further, the heat conducting film may be a thin film of gold or diamond.

【0007】[0007]

【作用】本発明により、半導体装置内の発熱素子の上に
パッシベーション膜を介して熱伝導性の優れた物質であ
る熱伝導膜が被着されるので、発熱素子からの熱は熱伝
導膜に良好に伝わる。さらに、熱伝導膜は熱伝導用バン
プと繋がっているので、熱伝導膜を介して放熱され、従
って、半導体装置全体の熱伝導率が上昇する。特に、半
導体装置の発熱部から熱伝導用バンプまでの半導体装置
表面上の熱伝導が良好となる。
According to the present invention, since the heat conductive film, which is a substance having excellent thermal conductivity, is deposited on the heat generating element in the semiconductor device through the passivation film, the heat from the heat generating element is transferred to the heat conductive film. Good transmission. Further, since the heat conducting film is connected to the heat conducting bumps, heat is radiated through the heat conducting film, and therefore the heat conductivity of the entire semiconductor device is increased. In particular, the heat conduction on the surface of the semiconductor device from the heat generating portion of the semiconductor device to the bumps for heat conduction becomes good.

【0008】[0008]

【実施例】本発明の実施例を図1に示す。以下、図に沿
って説明する。図1(a)は本発明の実施例の半導体装
置の断面図であり、図1(b)はこの半導体装置の上面
図である。
FIG. 1 shows an embodiment of the present invention. Hereinafter, description will be given with reference to the drawings. 1A is a sectional view of a semiconductor device according to an embodiment of the present invention, and FIG. 1B is a top view of this semiconductor device.

【0009】半導体素子1と外部との接続のためのバン
プ4、5がパッド31、32を介して形成されている。
また、バンプ4、5を除く領域はパッシベーション膜2
で覆われている。さらに、このパッシベーション膜2の
上に熱伝導膜6が電極端子用バンプ4とは接合せず、ま
た、熱伝導用バンプ5とは接合して形成されている。
Bumps 4 and 5 for connecting the semiconductor element 1 to the outside are formed via pads 31 and 32.
Further, the area excluding the bumps 4 and 5 is the passivation film 2.
Is covered with. Further, the heat conduction film 6 is formed on the passivation film 2 so as not to be joined to the electrode terminal bumps 4 and joined to the heat conduction bumps 5.

【0010】図3乃至図4に本発明の実施例の工程を示
し、図に沿って説明する。
3 to 4 show steps of the embodiment of the present invention, which will be described with reference to the drawings.

【0011】GaAs(熱伝導率0.46W/cm℃)
を主成分とする半導体素子1の上に、バンプ4、5の土
台となるべきパッド31、32と、これらのパッド3
1、32を除いた領域にパッシベーション膜2が形成さ
れている。パッド31、32はPtにより、また、パッ
シベーション膜2は、回路の保護、安定のために絶縁性
のSiO2 (熱伝導率0.14W/cm℃)により形成
されている。
GaAs (thermal conductivity 0.46 W / cm ° C.)
On the semiconductor element 1 containing as a main component, pads 31 and 32 to be the bases of the bumps 4 and 5, and these pads 3
The passivation film 2 is formed in the region excluding the regions 1 and 32. The pads 31 and 32 are made of Pt, and the passivation film 2 is made of insulating SiO 2 (heat conductivity of 0.14 W / cm ° C.) for protecting and stabilizing the circuit.

【0012】このパッシベーション膜2の上に、金(熱
伝導率3.1W/cm℃)により熱伝導膜6を形成する
(図3(a))。この時、熱伝導膜6はパッド31にほ
ぼ接するように、また、パッド31の付近では電極端子
との接続を避けるため、パッド31の直径程度の距離を
離して形成する必要がある。
On the passivation film 2, a heat conducting film 6 is formed of gold (heat conductivity 3.1 W / cm ° C.) (FIG. 3 (a)). At this time, the heat conductive film 6 needs to be formed so as to be almost in contact with the pad 31 and be separated from the pad 31 by a distance of about the diameter of the pad 31 in order to avoid connection with the electrode terminal.

【0013】次に、パッド31、32を除く領域、すな
わち、パッシベーション膜2と熱伝導膜6との上にレジ
スト7を塗布する。そして、パッド31、32を含む全
領域にTi/Auによるメッキ下地金属8が形成される
(図3(b))。パッド31、32の上方を除く領域、
すなわち、バンプ4、5の形成される部分を除く領域に
厚膜レジスト9を塗布する(図3(c))。
Next, a resist 7 is applied on the region excluding the pads 31 and 32, that is, on the passivation film 2 and the heat conducting film 6. Then, the plating base metal 8 of Ti / Au is formed on the entire region including the pads 31 and 32 (FIG. 3B). Area excluding above the pads 31 and 32,
That is, the thick film resist 9 is applied to the area excluding the portions where the bumps 4 and 5 are formed (FIG. 3C).

【0014】金メッキ層10を全体に成長させる(図4
(d))。その後、厚膜レジスト9をリフトオフする
(図4(e))。そして、ミリングとアッシングとを行
うことにより不要部分のメッキ下地金属8およびレジス
ト7を除去し、パッド31の上に電極端子用バンプ4
を、パッド32の上に熱伝導用バンプ5を形成する(図
4(f))。
The gold plating layer 10 is entirely grown (see FIG. 4).
(D)). Then, the thick film resist 9 is lifted off (FIG. 4E). Then, the plating base metal 8 and the resist 7 in unnecessary portions are removed by performing milling and ashing, and the electrode terminal bumps 4 are provided on the pads 31.
The bumps 5 for heat conduction are formed on the pads 32 (FIG. 4 (f)).

【0015】上記工程では、熱伝導膜6には金を用いた
が、ダイヤモンド(熱伝導率約20W/cm℃)を気相
合成した薄膜を用いることもできる。ダイヤモンドの薄
膜を用いる場合は、ダイヤモンドは電気的に絶縁体であ
るので電極端子用バンプ4と熱伝導膜6とを隔離する必
要はない。
In the above steps, gold was used for the heat conductive film 6, but a thin film obtained by vapor phase synthesis of diamond (heat conductivity of about 20 W / cm ° C.) can also be used. When a diamond thin film is used, it is not necessary to separate the electrode terminal bumps 4 from the heat conductive film 6 because diamond is an electrical insulator.

【0016】また、上記とは別の工程を図5に示す。Another process different from the above is shown in FIG.

【0017】半導体素子1の上にパッド31、32を介
してバンプ4、5が形成され、バンプ4、5を除く領域
がパッシベーション膜2により覆われている(図5
(a))。これは従来の構造と同じ状態である。そし
て、バンプ4を覆ってレジスト71が塗布される(図5
(b))。全ての領域に熱伝導膜61を形成する(図5
(c))。
Bumps 4 and 5 are formed on the semiconductor element 1 via pads 31 and 32, and regions other than the bumps 4 and 5 are covered with the passivation film 2 (FIG. 5).
(A)). This is the same state as the conventional structure. Then, a resist 71 is applied to cover the bumps 4 (see FIG. 5).
(B)). The heat conductive film 61 is formed in all regions (FIG. 5).
(C)).

【0018】その後、レジスト71をリフトオフするこ
とにより、バンプ4を覆っていたレジスト71と熱伝導
膜61とを除去し、電極端子用バンプ4とする。また、
バンプ5とこれを覆う熱伝導膜61とを熱伝導用バンプ
51とする(図5(d))。
Then, the resist 71 is lifted off to remove the resist 71 covering the bumps 4 and the heat conductive film 61 to form the electrode terminal bumps 4. Also,
The bumps 5 and the heat conducting film 61 covering the bumps 5 are used as the heat conducting bumps 51 (FIG. 5D).

【0019】上記工程によれば、従来の工程、構造をそ
のまま生かすことができる。
According to the above process, the conventional process and structure can be utilized as they are.

【0020】本発明は前述の実施例に限らず様々な変形
が可能である。
The present invention is not limited to the above-described embodiment, but can be variously modified.

【0021】熱伝導膜は金、ダイヤモンドの膜に限ら
ず、熱伝導性の良好なものであれば他の金属膜、非金属
膜でも良い。例えば、Al、Cu等の膜でも良い。ま
た、半導体素子の主成分はGaAsに限らず、例えば、
Siでも良く、さらに、パッシベーション膜はSiO2
に限らず、例えば、Si3 4 、Al2 3 等でも良い
ということは言うまでもない。
The heat conducting film is not limited to a gold or diamond film, but may be another metal film or non-metal film as long as it has a good heat conductivity. For example, a film of Al, Cu or the like may be used. Further, the main component of the semiconductor element is not limited to GaAs, and for example,
Si may be used, and the passivation film is SiO 2
Needless to say, for example, Si 3 N 4 , Al 2 O 3 or the like may be used.

【0022】また、熱伝導膜を形成した後、半導体素子
の保護、安定化のために絶縁膜をさらにこの熱伝導膜の
上から形成しても良い。さらに、半導体素子の動作に支
障がない場合は、熱伝導用バンプと電極端子用バンプと
を共用することも可能である。
After forming the heat conducting film, an insulating film may be further formed on the heat conducting film in order to protect and stabilize the semiconductor element. Further, when there is no hindrance to the operation of the semiconductor element, the heat conduction bump and the electrode terminal bump can be shared.

【0023】[0023]

【発明の効果】以上の通り本発明によれば、半導体装置
全体の熱伝導率を上昇させることができるので、フリッ
プチップ実装を行う半導体装置において、他の放熱手段
を取ることなく、放熱効果を大きくすることができる。
よって、従来の半導体装置よりも消費電力の大きいもの
が実現できる。
As described above, according to the present invention, since the thermal conductivity of the entire semiconductor device can be increased, the heat dissipation effect can be obtained in the flip chip mounting semiconductor device without using other heat dissipation means. Can be large.
Therefore, a device having higher power consumption than the conventional semiconductor device can be realized.

【0024】また、半導体装置上の発熱部から熱伝導用
バンプまでの熱伝導率が高くなることから、局所的に発
熱部を持つ半導体装置に対して特に有効である。
Further, since the heat conductivity from the heat generating portion on the semiconductor device to the heat conducting bump is increased, it is particularly effective for a semiconductor device having a heat generating portion locally.

【0025】これにより、集積回路の熱放散の問題を解
決することができ、さらに高電力の半導体素子を高密度
に集積化した半導体装置を実現することができる。
As a result, the problem of heat dissipation of the integrated circuit can be solved, and a semiconductor device in which high power semiconductor elements are integrated at high density can be realized.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施例の概略図である。FIG. 1 is a schematic diagram of an embodiment of the present invention.

【図2】従来のフリップチップ実装を行う半導体装置の
構造の概略図である。
FIG. 2 is a schematic view of the structure of a conventional semiconductor device for flip-chip mounting.

【図3】本発明の実施例の工程を示す概略図である。FIG. 3 is a schematic view showing a process of an example of the present invention.

【図4】本発明の実施例の工程を示す概略図である。FIG. 4 is a schematic view showing a process of an example of the present invention.

【図5】本発明の実施例の工程を示す概略図である。FIG. 5 is a schematic view showing a process of an example of the present invention.

【符号の説明】[Explanation of symbols]

1…半導体素子、2…パッシベーション膜、31…電極
端子用バンプのパッド、32…熱伝導用バンプのパッ
ド、4…電極端子用バンプ、5…熱伝導用バンプ、6…
熱伝導膜、7…レジスト、8…メッキ下地金属、9…厚
膜レジスト、10…金メッキ層。
DESCRIPTION OF SYMBOLS 1 ... Semiconductor element, 2 ... Passivation film, 31 ... Electrode terminal bump pad, 32 ... Heat conduction bump pad, 4 ... Electrode terminal bump, 5 ... Heat conduction bump, 6 ...
Thermal conductive film, 7 ... Resist, 8 ... Plating base metal, 9 ... Thick film resist, 10 ... Gold plating layer.

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 半導体素子の上に熱伝導用バンプおよび
電極端子用バンプとパッシベーション膜とが形成されて
いる半導体装置において、 熱伝導性の優れた物質である熱伝導膜が前記パッシベー
ション膜上の所望の領域に被着されている構造を有し、 前記熱伝導膜と前記熱伝導用バンプとは接合され、前記
熱伝導用バンプと前記電極端子用バンプとは電気的に絶
縁されていることを特徴とする半導体装置。
1. In a semiconductor device in which bumps for heat conduction, bumps for electrode terminals and a passivation film are formed on a semiconductor element, the heat conduction film, which is a substance having excellent heat conductivity, is formed on the passivation film. It has a structure that is adhered to a desired region, the heat conducting film and the heat conducting bump are bonded, and the heat conducting bump and the electrode terminal bump are electrically insulated. A semiconductor device characterized by.
【請求項2】 前記熱伝導膜は金またはダイヤモンドの
薄膜であることを特徴とする請求項1記載の半導体装
置。
2. The semiconductor device according to claim 1, wherein the heat conducting film is a thin film of gold or diamond.
JP12376092A 1992-05-15 1992-05-15 Semiconductor device Pending JPH05326520A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12376092A JPH05326520A (en) 1992-05-15 1992-05-15 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12376092A JPH05326520A (en) 1992-05-15 1992-05-15 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH05326520A true JPH05326520A (en) 1993-12-10

Family

ID=14868612

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12376092A Pending JPH05326520A (en) 1992-05-15 1992-05-15 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH05326520A (en)

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