JPH05325590A - Charge coupled device - Google Patents

Abstract

PURPOSE:To decrease the number of the constituent elements of a pulse circuit which generates clock pulses phitr to be applied to the transfer gate of the final stage of a CCD output part that can be driven with a low voltage and to reduce the element formation area. CONSTITUTION:When a clock pulse phib is at 'L', an FET 36 turns ON and a clock pulse phif is outputted to an output node N2. When the (fit falls to 'L', a capacitor 32 is charged to the potential difference 4V between 5V of a clock pulse phia a and 1V of the output node N2 through the FET 36 in the ON state. When the phib rises to 'H', the phib is inverted by an inverter 31 while the FET 36 turns OFF, the phia becomes 0V, and the N2 enters a floating state. so that the potential difference charged in the capacitor 32 is outputted from the N2. Consequently, the pulses phitr outputted from the N2 become pulses which vary between the level 'L' of -3V and the level 'H' of 5V.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is for driving a floating diffusion amplifier (hereinafter referred to as FDA) type charge coupled device (hereinafter referred to as CCD), and particularly for driving an output section capable of operating at a low voltage. The pulse circuit of.

[0002]

2. Description of the Related Art Conventionally, as a technique in such a field,
For example, some documents were described in the following documents. Reference 1: Japanese Patent Laid-Open No. 62-238665 Document 2: Japanese Patent Laid-Open No. 63-289865 FIG. 2 is a conventional FDA system C described in Document 1 above.
Schematic block diagram showing the CD output section, and FIG. 3 shows the CCD.
It is a circuit diagram of a pulse circuit of the output unit. In the CCD output section of FIG. 2, an N-type buried channel (not shown) is formed below the surface of the P-type semiconductor substrate SB, and a plurality of stages of transfer gates are formed on the buried channel via a gate insulating film ... 1 _n-2 ~
1 _n , ... 2 _n-2 to 2 _n are formed. Each stage has a second layer transfer gate ... 1 _n-2 to 1 _n and a first layer transfer gate ... 2
_{n−2 to} 2 _n, and is driven by two-phase clock pulses φ _a and φ _b except for the final stage. The clock pulses φ _a and φ _b are complementary pulses having opposite phases, for example, a low level (“L” level) of 0 V and a high level (“H” level) of 5 V. The second layer transfer gate 1 _n and the first layer transfer gate 2 _n in the final stage are
It is adapted to be driven by the clock pulse φ _tr generated by the pulse circuit 20 shown in FIG. Clock pulse φ
_tr is, for example, 0V as a reference, "L" level is -4V,
This is a pulse whose "H" level changes to 5V.

A second-layer output gate (OG) 3 to which a ground potential VSS (= 0 V) is applied is provided adjacent to the first-stage first-layer transfer gate 2 _n . Adjacent to the output gate 3, an N ⁺ type floating diffusion region (hereinafter referred to as FD region) 4 is formed on the semiconductor substrate SB.
Is formed inside. An N ⁺ type drain region (DD) 5 is arranged in the vicinity of the FD region 4 so as to face it, and a gate insulating film is provided on the N type buried channel between the FD region 4 and the drain region 5. Drain gate (D
G) 6 is formed. A power supply potential VDD (for example, 5 V) is applied to the drain region 5 and _a reset pulse φ _r (= φ _a ) is applied to the drain gate 6, and the drain region 5 and the drain gate 6 constitute a reset means. ..

The FD region 4 is connected to a source follower type output amplifier 10 formed on the semiconductor substrate SB.
The output amplifier 10 has N-type field effect transistors (hereinafter referred to as FETs) 11 and 12, which are connected in series between the power supply potential VCC and the ground potential VSS. The gate of one FET 11 is connected to the FD region 4, and its source and drain are connected to the power supply potential VDD and the output terminal OUT. Source of the other FET12
The drain is connected to the output terminal OUT and the ground potential VSS, and the clock pulse φ _b is applied to its gate.

The pulse circuit 20 shown in FIG. 3 is a circuit for generating the clock pulse φ _tr from the output node N1 by the clock pulses φ _a , φ _c and φ _d , and is formed on the same semiconductor substrate SB as the CCD of FIG. Has been done. Clock pulses phi _c has the same pulse width and a clock pulse phi _a, a reverse phase with respect to the clock pulse phi _a, and a pulse timing is delayed. Clock pulse φ
_d is the same as the pulse width of the clock pulse φ _c ,
It is a pulse whose phase is opposite to that of the clock pulse φ _{c and} whose timing is delayed. The clock pulse φ _d is applied to one electrode of the capacitor 21, and the other electrode is connected to the output node N1. The output node N1 and the clock pulse φ _a are connected to the source / drain of the P-type FET 23, the gate thereof is connected to one electrode of the capacitor 22, and the clock pulse φ _c is applied to the other electrode of the capacitor 22. It is like this. FET23
The source and drain of the P-type FET 24 are connected to the gate and the ground potential VSS, and the source or drain and the gate are commonly connected to the ground potential VSS.

FIG. 4 is a timing chart showing the operation of FIG. 3, and the CC shown in FIGS. 2 and 3 with reference to this figure.
The operation of the D output section will be described. First, the pulse circuit 2 of FIG.
The operation of 0 will be described. Clock pulse φ _a , φ _c , φ _d
Is supplied, the pulse circuit 20 operates. For example,
The clock pulse φ _a is a complementary M of the clock pulse φ _b.
It is generated by inverting with an inverter composed of an OS transistor (hereinafter referred to as CMOS). Clock pulses phi _c is obtained by inverting the clock pulses phi _a of the CMOS inverter, if further inverts the clock pulse phi _c a CMOS inverter, the clock pulse phi _d is obtained.

At time t1 in FIG. 4, the clock pulse φ _b changes from “L” level (= 0 V) to “H” level (= 5).
Stand up to V). At this time, the clock pulse φ _a maintains “H” level (= 5 V), φ _c maintains “L” level (= 0 level), and φ _d maintains “H” level (= 5 V). Since the clock pulse φ _c is at "L" level, the FET
Gate voltage -3V next 23, the FET23 is turned on, 5V clock pulse phi _a is sent to the output node N1 through the FET23, the clock pulses phi _tr outputted from the output node N1 becomes 5V. When the clock pulse φ _a falls to the “L” level (= 0 V) at time t2, the 0 V is sent to the output node N1 through the FET 23 in the ON state, and the clock pulse φ _tr falls to 0 V. When the clock pulse φ _c rises to the “H” level (= 5 V) at time t3, the gate voltage of the FET 23 rises to 1.5 V through the capacitor 22, so that the FET 23 is turned off and the clock pulse φ of the output node N1. _tr maintains 0V.

When the clock pulse φ _d falls to "L" level (= 0 V) at time t4, the voltage of the output node N1 is lowered through the capacitor 21 and the clock pulse φ _tr falls to -4V. At time t5, when the clock pulse φ _a rises from the “L” level to the “H” level, the base voltage of the FET 23 becomes 1.5 V by the 5 V clock pulse φ _c , but the FET 23 is turned on. Therefore, 5V of clock pulse φ _a
Is sent to the output node N1 through the FET 23, and the clock pulse φ _tr rises to 5V. When the clock pulse φ _c falls to the “L” level at time t6, the gate voltage of the FET 23 is lowered to −3V via the capacitor 22. Accordingly, FET 23 is kept in the ON state, the clock pulse phi _tr maintains a 5V by 5V clock pulses phi _a. The same operation is repeated thereafter,
Clock pulse φ _tr is + 5V to -4V with 0V as reference
Transition between. This clock pulse φ _tr is applied to the transfer gates 1 _n and 2 _n at the final stage in FIG.

In the CCD output section of FIG. 2, two-phase clock pulses φ _a and φ _b are transferred to each stage of transfer gates ... 1 _n- 2.
_{When applied to n-2} , 1 _n-1 and 2 _n-1 , the signal charges Q _S thereunder are sequentially transferred to the transfer gates 1 _n and 2 _{n at the} final stage. Since the potential well is formed by the clock pulse φ _tr below the first-stage transfer gate 1 _{n in} the final stage, the signal charge Q flowing into the potential well is generated.
_S is _{pushed out} by the clock pulse φ _tr and flows into the FD region 4 over the potential barrier created under the output gate 3 by the ground potential VSS. The signal charge Q _S that has flowed into the FD region 4 is converted into a voltage value by the FET 11 in the output amplifier 10 and taken out from the output terminal OUT as a voltage signal. After the voltage signal is taken out from the output terminal OUT, the drain gate 6 causes the reset pulse φ _r (= φ
It is opened in _a ) and unnecessary charges are discharged to the drain region 5. In this type of CCD output section, the transfer gate 1 at the final stage is
_Since the reset pulse φ _tr for driving _n and 2 _n has a waveform as shown in FIG. 4 and the low-voltage reset pulse φ _r = φ _a is applied to the drain gate 6, the drain voltage of the FET 11 can also be lowered, and thereby the signal can be reduced. A low voltage drive becomes possible without the charge Q _s flowing backward.

[0010]

However, in the conventional CCD output section, the pulse circuit 20 for generating the clock pulse φ _tr to be applied to the transfer gates 1 _n and 2 _n at the final stage.
Are two capacitors 21, 22 and two FET2
3 and 24 are required, and there is a problem that not only the number of elements is large but also the element formation area is increased when integrated into an integrated circuit, which is difficult to solve. The present invention provides a CCD which solves the problem that the above-mentioned conventional technique has, although it can be driven at a low voltage, but has a large number of elements and an increased element formation area when integrated into a circuit. Is.

[0011]

In order to solve the above-mentioned problems, the present invention outputs the signal charge sent from the transfer gate of the preceding stage by the clock pulse φ _b formed on the semiconductor substrate by the clock pulse φ _tr . A transfer gate at the final stage for transferring to the side, an output gate for forming a potential barrier formed on the semiconductor substrate adjacent to the transfer gate at the final stage, and in the semiconductor substrate adjacent to the output gate. An FD region formed to store the signal charge;
Reset means formed adjacent to the D region on the semiconductor substrate and discharging the accumulated charge of the FD region to the drain region by a reset pulse φ _r ; and a stored charge amount of the FD region formed on the semiconductor substrate as a voltage value. In a charge-coupled device including an output amplifier for converting to and outputting and a pulse circuit formed on the semiconductor substrate for generating the clock pulse φ _tr , the pulse circuit is configured as follows.

Namely, the pulse circuit, a clock pulse phi _a reverse phase with respect to the clock pulse phi _b is applied to one electrode, the other electrode being connected to the output node of the clock pulse phi _tr output ON / OFF operation between the capacitor and the first and second electrodes by the clock pulse φ _b , the first electrode is connected to the output node,
And switching elements said clock pulse phi pulse width and smaller than _a the clock pulses phi advanced timings than _a clock pulse phi _f is applied to the electrode of the second comprises.

[0013]

According to the present invention, since the pulse circuit of the CCD output section is configured as described above, the switching element is turned on and off by the clock pulse φ _b , and the clock pulse φ _f is output through the switching element. It is output to the node. Further, the capacitor is charged by the potential difference between the clock pulse φ _a and the output node, and the potential difference is output from the output node when the switching element is off. Therefore, a clock pulse having an amplitude changing from “H” level to “L” level with reference to a certain voltage is output from the pulse circuit. By the clock pulse of this pulse circuit,
The signal charge under the transfer gate at the final stage is sent to the FD region via the output gate. Then, the signal charge in the FD region is detected and output by the output amplifier. This allows the CCD
It is possible to drive at a low voltage without the signal charges flowing back at the output section. Therefore, the above problem can be solved.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an embodiment of the present invention.
FIG. 3 is a circuit diagram of a pulse circuit provided in a CCD output section in the A system, and elements common to those in the conventional FIG. 2 are denoted by common reference numerals. The CCD output section of the present embodiment is different from the conventional CCD output section only in the circuit configuration of the pulse circuit, and the other configurations are the same as the conventional one. In the pulse circuit of this embodiment, for example, the "L" level is -3V,
This is a circuit that generates a clock pulse φ _tr having an “H” level of 5 V and drives the transfer gates 1 _n and 2 _n at the final stage of FIG. 2 by the clock pulse φ _tr .
A CMOS inverter 31 is provided which inverts the clock pulse φ _b for driving 1 _n-1 and 2 _n-1 and outputs the clock pulse φ _a for driving the transfer gates 1 _n-2 and 2 _n-2. is doing. The inverter 31 has a P-type FET 31a and an N-type FET 31b, which are connected to the power supply potential VDD (= 5
V) and the ground potential VSS (= 0V) are connected in series. Output side of inverter 31 and clock pulse φ _tr
The capacitor 32 is connected between the output node N2 and the output node N2, and the output node N2 and the ground potential VSS are connected.
A capacitor 33 for output level adjustment is connected between and.

Further, two CMOS inverters 34 and 35 for buffers, which are connected in cascade and which receive the clock pulse φ _e and output the clock pulse φ _f , are provided. Clock pulses phi _e is smaller pulse width than the clock pulse phi _a, and a pulse advanced timings than its clock pulse phi _a. The inverter 34 is P
Has a type FET 34a and an N-type FET 34b, which are connected in series between the power supply potential VDD and the ground potential VSS. Similarly, the inverter 35 is a P-type FET 35a.
And N-type FET 35b, which are power source potential VD
It is connected between D and the ground potential VSS. The source and drain of a switching element (for example, P-type FET) 36 are connected to the output side of the inverter 35 and the output node N2, and the gate thereof is connected to the clock pulse φ _b .

Next, the operation of the pulse circuit shown in FIG. 1 will be described with reference to FIG. FIG. 5 is a timing chart showing the operation of FIG. 1, and T1, T2, T3 in the figure represent each period of the clock pulse φ _a , .... In the period T1 of FIG. 5, after the clock pulse φ _e rises from the “L” level (= 0 V) to the “H” level (= 5 V), the clock pulse φ _b changes from the “H” level (= 5 V) to the “L” level. When it falls to the "level (= 0V), the clock pulse φ _e is driven by the inverters 34 and 35 to generate the clock pulse φ _f.
Is from "L" level (= 0V) to "H" level (= 5V)
Stand up to. When the clock pulse φ _b falls from the “H” level to the “L” level, it is inverted by the inverter 31 and the clock pulse φ _a becomes the “L” level (= 0.
V) rises to "H" level (= 5V). When the clock pulse φ _b falls to “L” level, FET3
6 is turned on, the clock pulse φ _f is sent to the output node N2, and the clock pulse φ _tr output from the output node N2 changes from “L” level (= −3 V) to “H” level (=
5V).

In the period T2, the clock pulse φ _e ,
When φ _f falls from “H” level to “L” level,
It is transmitted to the output node N2 through the FET 36 in the ON state. For example, the capacitance value of the capacitor 32 is 2 pF,
When the capacitance value of the capacitor 33 is 0.25 pF, the clock pulse φ _tr output from the output node N2 becomes 1V. Therefore, the potential difference 4V between 5V of the clock pulse φ _a and 1V of the output node N2 is charged in the capacitor 32. In period T3, clock pulse φ _b
Rises to the “H” level, the inverter 31
And the clock pulse φ _a becomes "L" level. When the clock pulse φ _b becomes “H” level, FE
T36 is turned off. At this time, clock pulse φ
_{Since a} is at the “L” level (= 0 V), the output node N2 is in a floating state, and the potential difference 4 between the 5 V of the clock pulse φ _a and the 1 V of the output node N2 during the period T2 is 4
Since V is output from the output node N2, the clock pulse φ _tr becomes -3V.

Such "L" level is -3V, "H"
When a clock pulse φ _tr having a level of 5 V is applied to the transfer gates 1 _n and 2 _n at the final stage of FIG. 2, the signal charge Q _s flowing into the potential well below the first layer transfer gate 2 _n is applied.
Are extruded and flow into the FD region 4 over the potential barrier created under the output gate 3 by the ground potential VSS. The signal charge Q _s flowing into the FD region 4 is converted into a voltage value by the FET 11 in the output amplifier 10 as in the conventional case,
It is taken out from the output terminal OUT as a voltage signal. After the voltage signal is taken out from the output terminal OUT, the drain gate 6 is opened by the reset pulse φ _r (= φ _a ) and unnecessary charges are discharged to the drain region 5. In addition, conventional CC
In the D output section, the clock pulse φ _tr applied to the transfer gates 1 _n and 2 _n at the final stage is -4 V to +5 with 0 V as the center.
While the pulse has the amplitude value of V, the "L" level is -3V in the clock pulse φ _tr of this embodiment.
Although the “H” level is a pulse of 5 V, it does not cause any problem in the transfer operation, and the efficient transfer of the signal charge Q _s can be performed.

In the pulse circuit of this embodiment, the clock pulses φ _a , φ _b and φ _f correspond to the clock pulses φ _a , φ _c and φ _d of the conventional pulse circuit, and the conventional capacitor 21 and FET 23 are used. It corresponds to the example capacitor 32 and FET 36. The capacitor 33 of this embodiment is
The capacitance value is smaller than that of the capacitor 32 because it is provided for adjusting the output level. Therefore, the total capacitance value of the capacitors 32 and 33 of the present embodiment is smaller than the total capacitance value of the conventional capacitors 21 and 22, and one FET is present in the present embodiment as compared with the two conventional FETs 23 and 24. Since it is sufficient to use the FET 36, the number of elements can be reduced and the element formation area at the time of integration into an integrated circuit can be reduced.

The present invention is not limited to the above embodiment,
Various modifications are possible. Examples of such modifications include the following. (I) Since the capacitor 33 in FIG. 1 is for adjusting the output level, it may be omitted. As a result, the number of elements can be reduced and the element formation area can be reduced. (Ii) for the clock pulse phi _b of FIG. 1 is inverted by the inverter 31 is generating the clock pulse phi _a, the timing of the clock pulse phi _a is shifted slightly by the inverter 31. This clock pulse phi _a and phi _b may be the same timing, the clock pulses phi _a and phi
_b may be separately produced and supplied to the pulse circuit of FIG. Similarly, clock pulse φ _e
While making the clock pulses phi _f by the driving by the inverter 35, the clock pulse phi _f
May be directly supplied to the pulse circuit of FIG. 1 from the outside. Further, the circuit configuration may be such that the clock pulses φ _f , φ _b , and φ _a are generated from the clock pulse φ _e by an inverter or the like. (Iii) The P-type FET 36 in FIG. 1 may be an N-type FET or another transistor by changing the polarity of the semiconductor substrate SB or the power supply. (Iv) The CCD of FIG. 2 has a two-phase clock pulse φ _a , φ
_{Although the} transfer operation is performed in _b , the structure may be changed so that it operates with clock pulses of other phase numbers.

[0021]

As described [Effect the Invention above, according the present invention, on the switching element by the clock pulse phi _b, and OFF operation, by charging and discharging the capacitor at the clock pulse phi _a and phi _f, predetermined amplitude Since the pulse is generated, it is possible to reduce the number of elements in the pulse circuit, reduce the element formation area, and provide a CCD output section that can be accurately driven at a low voltage.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a pulse circuit provided in a CCD output section showing an embodiment of the present invention.

FIG. 2 is a configuration diagram of a conventional CCD output unit.

FIG. 3 is a circuit diagram of a pulse circuit provided in a conventional CCD output section.

FIG. 4 is a timing diagram showing the operation of FIG.

5 is a timing chart showing the operation of FIG. 1. FIG.

[Explanation of symbols]

1 _n-2 , 1 _n-1 second layer transfer gate 2 _n-2 , 2 _n-1 first layer transfer gate 1 _n final stage second layer transfer gate 2 _n final stage first layer Transfer gate 3 Output gate 4 FD region 5 Drain region 6 Drain gate 10 Output amplifier 32, 33 Capacitor 36 P-type FET φ _a , φ _b , φ _e , φ _f Clock pulse φ _r Reset pulse SB Semiconductor substrate VDD Power supply potential VSS Ground potential

Claims (1)

[Claims] 1. A transfer gate at a final stage, which transfers signal charges sent from a transfer gate at a previous stage by a clock pulse φ _b to a output side by a clock pulse φ _tr , formed on a semiconductor substrate, and a transfer at the final stage. An output gate for forming a potential barrier formed on the semiconductor substrate adjacent to the gate, a floating diffusion region formed in the semiconductor substrate adjacent to the output gate for accumulating the signal charge, and Reset means formed on the semiconductor substrate adjacent to the floating diffusion region to discharge accumulated charges in the floating diffusion region to a drain region by a reset pulse φ _r; and the floating diffusion formed on the semiconductor substrate. An output amplifier that converts the accumulated charge amount in the fusion region into a voltage value and outputs it Wherein a pulse circuit for generating the clock pulses phi _tr formed on a semiconductor substrate, in the charge coupled device having, the pulse circuit, a clock pulse phi _a reverse phase with respect to the clock pulse phi _b has one electrode And a capacitor whose other electrode is connected to the output node for outputting the clock pulse φ _tr, and the clock pulse φ _b turns on and off between the first and second electrodes, and the first electrode There is connected to the output node, and a switching element and the clock pulse phi _a pulse width than that and less that clock pulses phi advanced timings than _a clock pulse phi _f is applied to the second electrode, A charge-coupled device, characterized in that it is provided.