JPH053251A - Standard cell type semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To obtain a highly accurate delay circuit corresponding to the correction characteristics of timing created in circuit design by a method wherein delay blocks composed of capacitance elements and resistance elements are provided on a semiconductor device. CONSTITUTION:Delay blocks 210 composed of resistance elements 201R and capacitance elements 210C which are connected in parallel with each other are provided beneath a logic part 110a and near a first RAM 130-1 on the basic of circuit connection information. The respective blocks are connected to each other with second aluminum wirings 1, 2 and 117-7 and a first aluminum wiring 11 in wiring regions 150-2, 160-2 and 116-1 to realize a semiconductor integrated circuit device (LSI). The respective delay blocks are composed of the capacitance elements and the resistance elements having different capacitance values and resistance values and, by combining the blocks, a delay circuit having higher accuracy can be obtained corresponding to the correction characteristics of timings created by various circuit design and, further, a misoperation caused by the increase of the wiring length, i.e., the increase of the wiring capacitance, can be avoided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a standard cell type semiconductor integrated circuit device.

[0002]

2. Description of the Related Art In recent years, standard cell type semiconductor integrated circuit devices have a greater degree of freedom in design than a gate array and can use large ROMs and RAMs, and the chips can be configured without waste, so that communication, personal computers, home appliances, etc. Has come to be used in a wide range of fields. For this reason, the circuit configuration of the standard cell has become complicated, and more precise layout has been required.

Usually, in a standard cell type semiconductor integrated circuit device, as shown in FIGS. 3A and 3B, a logic section 110, a microprocessor section 120, a first RAM 130-1, and a second RAM 130-1. RAM 130-2, first
Each block of different sizes, such as the ROM 140-1 and the second ROM, is arranged in the internal area of the LSI chip 100. In addition, the standard cell wiring area 150
-1 to 150 to 4, 160-1 to 160-3 expand or contract depending on the number of wirings.

Further, according to the circuit connection information, in the wiring area,
Second aluminum wirings 1, 2, 3, ... First aluminum wirings 11, 12, 13 ,.
2, 23, 24 ... Are used to connect the logic unit 110, the first RAM 130-1 and the microprocessor unit 120 to realize an LSI. Such layout design is usually automatically performed by a computer.

Further, the microprocessor unit 120, the first RAM 130-1, the second RAM 130-2, the first R
Each of the OMs 140-2 exists as a single block, but the logic unit 110 has the same structure as that shown in FIGS.
Inverters 111-1 to 111-4, F / F
112-1, NAND gate 113-1, NOR gate 114-1, composite gate 115-1 and other functional blocks and wiring areas 116-1, 116-2, ...
Second aluminum wirings 117-1, 117-2, ... First
Aluminum wiring 118-1, through hole 119-
It is realized by connecting the respective functional blocks using 1, 119-2, .... Such layout design is also usually automatically performed by a computer.

In this case, as shown in FIG. 5, the first RAM
When the output (OUT) of the first RAM 130-1 is delayed by several ns due to a timing problem in circuit design, the output (OUT) of the first RAM 130-1 is set to the inverter 111.
The output (OUT1) of the delay circuit 200 is connected to the delay circuit 200 composed of -1 to 111-4, and the gate delay is used to correct the timing of the circuit.
It is assumed that the M block 130-1 is an apparent output.

That is, from the circuit connection information, as shown in FIG. 6, the wiring area 15 in which the first RAM 130-1 and the inverters 111-1 to 111-4 of the logic section 110 are arranged.
0-1, 160-2, 116-1, 116-2 and second aluminum wirings 1, 2, 117-1 to 117-6, first
An LSI is realized by connecting the respective blocks using aluminum wirings 11, 118-1 to 118-4 and through holes 21, 22, 119-1 to 119-7.

[0008]

As described above,
Since the conventional standard cell type semiconductor integrated circuit device uses a delay circuit including an inverter for timing adjustment of the circuit, a delay time of a plurality of stages of the inverter can be obtained. For this reason, there is a disadvantage that a highly accurate circuit design cannot be performed. Further, there is a problem that the number of blocks increases by the number of inverters used in the delay circuit.

Further, since the arrangement and wiring are automatically performed on the computer, the inverters for the delay circuit are arranged irregularly. For this reason, there is a drawback that the wiring length becomes long, the wiring capacitance becomes large, and it causes a malfunction.

The present invention has been made in view of the above problems, and improves the accuracy of delay, prevents malfunctions, and improves the quality of circuit design.
An object is to provide a cell type semiconductor integrated circuit device.

[0011]

According to the present invention, an inverter, a NOR gate, a NAND gate, a functional block such as an F / F, and RA, which are prepared in advance on a semiconductor substrate, are provided.
In a standard cell type semiconductor integrated circuit device that realizes a required circuit function by combining a memory block such as M and ROM and a large general-purpose functional block such as a microprocessor, the semiconductor substrate includes a capacitor element and / or a resistance element. It includes a delay block.

[0012]

According to the present invention, by providing a delay block composed of a capacitor element and a resistance element, the capacitance value and the resistance value of the capacitor element and the resistance element can be set in various ways. Arbitrary capacitance values and resistance values can be obtained by arranging various combinations of elements and resistance elements.

Thus, the delay time can be easily selected, and a highly accurate delay circuit can be provided according to the timing correction characteristic generated in the circuit design. In addition, it is possible to prevent malfunction due to an increase in the wiring length and wiring capacitance of the delay circuit.

[0014]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 (a) is a block diagram showing an embodiment of the present invention, FIG. 1 (b) is an enlarged view of part A of FIG. 1 (a), and FIG. 2 is a block diagram of a delay block.

The delay block 201 comprises a resistance element 201R and a capacitance element 201C connected in parallel.

From the circuit connection information, as shown in FIG.
The delay block 201 is arranged below the logic unit 110a and near the first RAM 130-1, and the wiring area 15
2nd aluminum wiring 1, 2, 117-7, 1st aluminum wiring 1 in 0-2, 160-2, 116-1
1,118-5 and through holes 21, 22, 119-8
Is used to connect each block to realize a semiconductor integrated circuit device (LSI).

The delay block is not limited to the RC parallel circuit, but a capacitor element having a capacitance value of 0.5 pF, 1 pF, 2 pF may be prepared, and the capacitance value may be changed as necessary. The delay time can be easily selected. Similarly in the resistance element, several Ω to several kΩ
The delay block with various variations such as a capacitor element, a resistance element, or a combination of a capacitor element and a resistance element is prepared.

By using several kinds of delay blocks in this way, it is possible to obtain a delay circuit with higher accuracy according to the timing correction characteristics that occur in various circuit designs.

Further, since it is not necessary to use many stages of inverters as the delay circuit, it is possible to prevent malfunction due to an increase in wiring capacitance of the wiring length of the delay circuit.

Further, even if the delay block is used, the LSI can be realized by using a computer as in the conventional case.

[0022]

As described above, according to the present invention, by providing the delay block including the capacitor element and / or the resistance element, it is possible to provide the delay time according to the correction characteristic of the timing generated in various circuit designs. . Therefore, there is an effect that it is possible to design a circuit with higher accuracy than in the past.

Further, according to the present invention, it is not necessary to form a delay circuit by using a number of stages of functional blocks such as an inverter, and it is possible to prevent malfunction due to an increase in the wiring capacitance of the wiring length of the delay circuit. effective.

[Brief description of drawings]

FIG. 1 is a block diagram (FIG. 1A) and a partially enlarged view (FIG. 1B) showing a configuration of an embodiment of the present invention.

FIG. 2 is a configuration diagram of a delay block according to an embodiment.

FIG. 3 is a block diagram showing a configuration of a conventional example (FIG. 3 (a)).
3 is a partially enlarged view (FIG. 3B).

FIG. 4 is a block diagram (FIG. 4A) and a partially enlarged view showing a configuration of a logic unit in a conventional example.

FIG. 5 is a circuit diagram of a delay circuit in a conventional example.

FIG. 6 is a layout diagram showing a configuration of a delay circuit in a conventional example.

[Explanation of symbols]

100 LSI chips 110, 110a Logic part 111-1 to 111-4 inverter 112-1 F / F 113-1 NAND gate 114-1 NOR gate 115-1 compound gate 116-1, 116-2 wiring area 117-1 to 117-7 Second Aluminum Wiring 118-1 to 118-5 First Aluminum Wiring 119-1 to 119-8 Through hole 120 microprocessor 130-1 First RAM 130-2 Second RAM 140-1 First ROM 140-2 Second ROM 150-1 to 150-4 Wiring area 160-1 to 160-3 wiring area 200 delay circuit 201 delay block 201R resistance element 201C capacitor element

Claims (2)

[Claims] 1. A standard cell type semiconductor integrated circuit device that realizes a required circuit function by combining a functional block, a memory block, and a general-purpose functional block prepared in advance on a semiconductor substrate, wherein a capacitor element is provided on the semiconductor substrate. And / or a standard cell type semiconductor integrated circuit device including a delay block including a resistance element. 2. The standard cell type semiconductor integrated circuit device according to claim 1, wherein the delay block is arranged in a logic section including a plurality of functional blocks.