JPH05312906A - Simulating apparatus - Google Patents

Abstract

PURPOSE:To make it possible to display the result of the timing verification in the overlapped pattern on a logic circuit diagram as a simulation object. CONSTITUTION:The net list, which is obtained from a logic circuit as a simulation object, is read and inputted into a central processing part 1 from a net-list storing file F1. The test pattern is read and inputted into the central processing part 1 from a test-pattern storing file F2. Timing verification is performed in the central processing par 1. The result of the timing verification is displayed on a display part 2 in the overlapped state on the logic circuit as the simulation object.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a simulation device for verifying operation timing of a logic circuit used in an LSI design process or the like.

[0002]

2. Description of the Related Art A simulation device of this type creates a netlist from mutual connection information such as elements and nodes based on a logic circuit diagram to be verified, and also a test pattern based on the logic circuit diagram. Create a netlist, input each of these netlists and test patterns to the central processing unit that performs timing verification, perform timing verification, determine the presence or absence of a timing error, and display it on the display if there is a timing error. It is supposed to do.

Next, the processing steps of such a conventional simulation apparatus will be specifically described with reference to the flowchart shown in FIG. The designer performs a logic design according to the requested logic operation and inputs a logic circuit diagram (see FIG. 2) (step S1). In the simulation device, a netlist is created by the netlist creating means (step
S2), and a test pattern is created by the test pattern creating means based on this netlist (step S
3), timing verification is performed by the timing verification means based on these netlists and test patterns (step
S4). The timing verification means determines the presence / absence of a timing error, and outputs the presence / absence of an error message if a timing error exists, so the designer confirms this (step S5), and if there is an error message, another Open the window and specify the desired signal line to display the waveform diagram shown in Fig. 2 (step S6).
The designer checks the elements, nodes, signals, etc., to which signals that do not meet the timing specifications are input, and determines whether to change the logic (step S7).

FIG. 2 is a logic circuit diagram showing an example of a logic circuit which is a timing verification target. In FIG. 2, 11 to 14 are elements, and 21 to 30 are nodes connected to the input and output terminals of the elements 11 to 14, respectively. Now, for example, step S4
As a result of the timing verification, the element (flip-flop) 14
When a signal that does not satisfy the timing specifications required for the input is input to each input terminal D of the element 14 as shown in FIG.
The waveform of the signal input to T, S, and R is displayed on the display unit 2. The designer calculates the time required to satisfy the requested timing specifications, determines in step S6 whether or not to change the logic circuit diagram, and if there is a change, the logic circuit diagram is changed and step S1 Returning to FIG.
Obtain the required logic circuit diagram as shown in. As is clear from comparison between FIGS. 2 and 4, the modified logic circuit diagram shown in FIG. 4 is a node connected to the input terminals S and R of the element 14 shown in FIG.
21 and 28 are modified so that new elements 15 and 16 are inserted respectively.

[0005]

By the way, in the conventional simulation apparatus as described above, when the result satisfying the timing specification required in the timing verification in step S4 is not obtained, an error message is issued in step S5. There is a problem that it takes a long time for verification because it is necessary to confirm and manually confirm the waveform display of the signal input to the element in which the timing error has occurred in step S6.

The present invention has been made in view of the above circumstances, and its purpose is to reduce the burden on the designer by displaying the timing verification result together on the logic circuit diagram, and to reduce the load in a short time. It is to provide a simulation device capable of verifying timing.

[0007]

A simulation apparatus according to the present invention is a central processing unit for performing logic simulation for timing verification based on a netlist created based on connection information of a logic circuit to be simulated and a test pattern. And a logic circuit diagram of a simulation target and a display unit for displaying the timing verification result in combination with the logic circuit diagram.

[0008]

In the present invention, since the timing verification result is also displayed on the logic circuit diagram to be simulated, the timing error can be checked quickly and effectively, and the logic needs to be corrected. Also in this case, the corrected logic circuit diagram can be obtained in a short time.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below with reference to the drawings showing the embodiments. FIG. 5 is a block diagram of a simulation apparatus according to the present invention, in which 1 indicates a central processing unit. The central processing unit 1 reads the netlist of the logic circuit to be simulated from the netlist storage file F1 and the test pattern from the test pattern storage file F2, checks the timing of signal transmission in the logic circuit, and displays the result. It is designed to be displayed on the part 2.

The netlist is created by a netlist creating means (not shown) based on the logic circuit to be subjected to timing verification, and the test pattern is created by the test pattern creating means (not shown) corresponding to the logic circuit to be simulated. Then, they are respectively stored in the netlist storage file F1 and the test pattern storage file F2.

Next, the operation of such a simulation apparatus will be described with reference to the timing chart shown in FIG.
First, a logic circuit diagram to be simulated as shown in FIG. 2 is input by a circuit diagram input means (not shown) (step
S11), each element 11 to 16 by the netlist creating means, each node 21 to 30 connecting the input and output ends of each element and data relating to these connection relationships, that is, a netlist is created (step S12). Separately, a test pattern, which is each input / output signal pattern of the logic circuit, is created by the test pattern creating means in correspondence with the target logic circuit diagram (step S1).
3).

The central processing unit 1 executes a timing verification simulation based on the netlist and the test pattern (step S14), and displays the simulation result on the display unit 2 (step S15). The display of the results on the display unit 2 is such that the logic circuit diagram as the simulation target is displayed together with the timing verification result as shown in FIG. 7, and the element having the timing error as shown in FIG. Waveform diagram of each input terminal of the group is interactively displayed (step S16).

The display of the logic circuit diagram on the display unit 2 is shown in FIG.
If there is a timing error as a result of the timing check and the logic circuit diagram that is the simulation target in the mode shown in FIG. The so-called blink display A is made.

Also on the waveform diagram, as shown in FIG. 8, blinking displays B and C are similarly provided for both signals in which a timing error has occurred so as to surround the portion in which the timing error has occurred. For example, the signals at the respective input terminals of the flip-flop are normally between the rising edge of the input signal to the terminal T and the rising edge of the input signal to the terminal S, and the rising edge of the input signal to the terminal T and the input signal to the terminal R. A predetermined time difference is required between the rising and the rising of the element, but if such a time difference is insufficient, a blinking display A in which the periphery of the element is blinking is made as shown in FIG. Also in the waveform diagram as shown in FIG. 8, the portions surrounding the rising and falling regions of both the input signals of the terminals T and S, and the portions surrounding the rising and falling regions of both the input signals of the terminals T and R are broken lines. The blinking similar blink displays B and C are made.

The designer visually recognizes the logic circuit diagram and the waveform diagram of the display unit 2 and corrects the logic circuit, for example, as shown in FIG. The display mode on the display unit 2 is not limited to the blink display as described above, but the circuit component element itself and / or the waveform itself in the portion where the timing error occurs is blinked or displayed in a different color. Of course, it is okay.

[0016]

As described above, in the device of the present invention, the timing verification result, which is the simulation result, is displayed on the display unit in a state of being superimposed on the logic circuit. Therefore, it is easy and quick to confirm the timing error. The present invention has excellent effects such that the logic can be changed quickly and efficiently, and the time required to obtain a logic circuit diagram satisfying the required timing specifications can be shortened.

[Brief description of drawings]

FIG. 1 is a flowchart showing a processing process of a conventional simulation apparatus.

FIG. 2 is a logic circuit diagram showing an example of a logic circuit to which a conventional simulation device is applied.

FIG. 3 is an input / output signal waveform diagram of one element of the logic circuit diagram shown in FIG.

FIG. 4 is a logic circuit showing a state after the correction of the logic circuit.

FIG. 5 is a block diagram of a simulation apparatus according to the present invention.

FIG. 6 is a flowchart showing a processing process of the simulation apparatus according to the present invention.

7 is an explanatory diagram showing a mode in which a simulation result is displayed on a display unit when the simulation apparatus according to the present invention is applied to the logic circuit diagram shown in FIG.

FIG. 8 is an explanatory diagram showing another mode in which a waveform diagram and a timing error portion are also displayed in an overlapping manner on the simulation result display portion.

[Explanation of symbols]

 1 Central processing unit 2 Display unit 11 to 14 elements 21 to 30 nodes

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[Procedure amendment]

[Submission date] October 20, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0004

[Correction method] Change

[Correction content]

FIG. 2 is a logic circuit diagram showing an example of a logic circuit which is a timing verification target. In FIG. 2, 11 to 14 are elements, and 21 to 30 are nodes connected to the input and output terminals of the elements 11 to 14, respectively. Now, for example, step S4
As a result of the timing verification, the element (flip-flop) 14
When a signal that does not satisfy the timing specifications required for the input is input to each input terminal D of the element 14 as shown in FIG.
The waveform of the signal input to T, S, and R is displayed on the display unit 2. The designer calculates the time required to satisfy the requested timing specifications, determines in step S7 whether or not to change the logic circuit diagram, and if there is a need to change the logic circuit diagram, change it in step S1. Returning to FIG.
Obtain the required logic circuit diagram as shown in. As is clear from comparison between FIGS. 2 and 4, the modified logic circuit diagram shown in FIG. 4 is a node connected to the input terminals S and R of the element 14 shown in FIG.
21 and 28 are modified so that new elements 15 and 16 are inserted respectively.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0011

[Correction method] Change

[Correction content]

Next, the operation of such a simulation apparatus will be described with reference to the timing chart shown in FIG.
First, a logic circuit diagram to be simulated as shown in FIG. 2 is input by a circuit diagram input means (not shown) (step
S11), each element 11 to 14 by the netlist creating means, each node 21 to 30 connecting the input and output ends of each element and data relating to their connection, that is, a netlist is created (step S12), Separately, a test pattern, which is each input / output signal pattern of the logic circuit, is created by the test pattern creating means in correspondence with the target logic circuit diagram (step S1).
3).

[Procedure 3]

[Document name to be amended] Statement

[Name of item to be corrected] Figure 3

[Correction method] Change

[Correction content]

3 is an input / output signal waveform diagram of an element of the example of the logic circuit diagram shown in FIG. 2. FIG.

Claims (1)

[Claims] 1. A central processing unit that performs a logic simulation for timing verification based on a netlist created based on connection information of a logic circuit to be simulated and a test pattern, a logic circuit diagram to be simulated, and timing to this. And a display unit for displaying the verification result in a combined manner.