JPH0531236U - Package carrier of semiconductor integrated circuit device - Google Patents

Abstract

(57) [Abstract] [Purpose] It is possible to surely bring a pin into contact with a test terminal even if the length of the pin of the semiconductor integrated circuit device varies. [Structure] A pin 2 of a semiconductor integrated circuit device 2 is provided at an exit of a pin insertion hole 13 provided in a bottom portion 11 of a package carrier 1.
2 is provided with a guide groove 14 that is larger than the test terminal 3 that is in electrical contact with the test terminal 3. Therefore, the test terminal 3 can enter the guide groove 14, enter the pin insertion hole 13, and contact the pin 22 that does not project from the pin insertion hole 13.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to the structure of a package carrier that accommodates semiconductor integrated circuit devices such as LSI and VLSI.

[0002]

[Prior Art]

 As shown in FIG. 3, the package carrier of the conventional semiconductor integrated circuit device is formed in a shallow dish shape, and a large number of pin insertion holes 13 are provided in the bottom 12 of the recess 11. In this package carrier 1, as shown in FIGS. 4 and 5, the package main body 21 of the semiconductor integrated circuit device 2 is housed inside, and the pins 22 of the semiconductor integrated circuit device are inserted into the pin insertion holes 13 respectively. The tip of the pin 22 is configured to project from the bottom surface of the package carrier 1. As shown in the enlarged sectional view of FIG. 6, this pin insertion hole 13 is formed as an insertion hole having a uniform hole diameter, and in particular, the outlet side of the pin insertion hole 13 corresponding to the bottom surface of the package carrier 1 has a flat structure. Is becoming.

[0003]

[Problems to be solved by the device]

 In such a structure, if the length of the pin 22 of the semiconductor integrated circuit device 2 varies, the tip of the pin 22 may not be projected to the outlet side of the pin insertion hole 13 in the case of a short pin. is there. If the tip of the pin 22 is not projected to the exit side of the pin insertion hole 13 as described above, the test terminal 3 of the test device of the semiconductor integrated circuit device is brought into contact with the bottom surface side of the package carrier 1 as shown in FIG. Then, there is a problem that the test terminal 3 is not contacted with the pin 22 and the test cannot be performed. An object of the present invention is to provide a package carrier for a semiconductor integrated circuit device, which makes it possible to reliably bring the pin into contact with a test terminal even when the pin length of the semiconductor integrated circuit device varies. It is in.

[0004]

[Means for Solving the Problems]

 The package carrier of the present invention is provided with a guide groove at the outlet of the pin insertion hole on the bottom surface of the package carrier, which is larger than the test terminal electrically contacting the pin.

[0005]

[Action]

 According to the present invention, by guiding the test terminal into the guide groove, the test terminal can enter the pin insertion hole and come into contact with the pin that does not protrude from the pin insertion hole.

[0006]

【Example】

 Next, the present invention will be described with reference to the drawings. FIG. 1 is a sectional view of an essential part of a first embodiment of the present invention, which is a sectional view of an essential part of the package carrier shown in FIGS. As shown in FIG. 3, the package carrier 1 formed in a shallow dish can house the package body 21 of the semiconductor integrated circuit device 2 in the recess 11. Further, in the bottom portion 12 of the package carrier, a large number of pin insertion holes 13 for inserting a large number of pins 22 protruding from the lower surface of the semiconductor integrated circuit device 2 are formed. Further, as shown in FIG. 1, a guide groove 14 is formed on the bottom surface of the package carrier 1 so as to enlarge the opening width dimension of the pin insertion hole 13 on the outlet side.

The guide groove 14 can be formed, for example, by forming a groove that extends between the pin insertion holes 13 on the bottom surface of the package carrier 1. In this embodiment, the guide groove 14 has a rectangular cross section. is doing. Further, the groove width of the guide groove 14 is set to be larger than the width dimension of the test terminal 3 provided in the device for testing the semiconductor integrated circuit device 2.

According to this configuration, when the semiconductor integrated circuit device 2 is housed in the package carrier 1 and the pins 22 are inserted into the pin insertion holes 13, the tips of some of the pins 22 are dispersed due to variations in the pin length. Even if the state in which the pin does not project to the outlet side of the pin insertion hole 13 occurs, the test terminal 4 is inserted into the pin insertion hole 13 side by using the guide groove 14 by using the guide groove 14 to insert the test terminal 4 into the pin 22. It is possible to contact the tip of the.

FIG. 2 shows a second embodiment of the present invention and is a sectional view similar to FIG. In this embodiment, the guide groove 15 provided on the outlet side of the pin insertion hole 13 is formed in a tapered shape. Even in this case, the opening width dimension of the guide groove 15 is formed larger than the width of the test terminal 3. Also in this embodiment, even when the tip of the short pin 22 is not projected from the outlet side of the pin insertion hole 13, the test terminal 3 is inserted into the pin insertion hole 13 side by using the guide groove 15 and the test terminal 3 is inserted. It becomes possible to contact the tip of the pin 22.

[0010]

[Effect of the device]

 As described above, according to the present invention, the outlet of the pin insertion hole is provided with a guide groove that is larger than the test terminal that makes electrical contact with the pin. This has the effect of making reliable contact with the pin.

[Brief description of drawings]

FIG. 1 shows a first embodiment of the present invention and is an enlarged sectional view of a part of a portion corresponding to line AA of FIG.

FIG. 2 is an enlarged sectional view similar to FIG. 1 in a second embodiment of the present invention.

FIG. 3 is a perspective view of a package carrier to which the present invention is applied.

FIG. 4 is a perspective view showing a state in which a semiconductor integrated circuit device is mounted on the package carrier of FIG.

5 is a cross-sectional view corresponding to the line AA in FIG.

6 is an enlarged cross-sectional view of a part of FIG.

[Explanation of symbols]

 1 Package Carrier 2 Semiconductor Integrated Circuit Device 3 Test Terminal 13 Pin Insertion Hole 14, 15 Guide Groove 21 Package Body 22 Pin

Claims (1)

[Scope of utility model registration request] 1. A package carrier for accommodating a semiconductor integrated circuit device and having a pin insertion hole at the bottom thereof for inserting a pin of the semiconductor integrated circuit device, wherein the pin and the electrical outlet are at the outlet of the pin insertion hole on the bottom surface of the package carrier. A package structure for a semiconductor integrated circuit device, characterized in that a guide groove larger than the contact terminal to be contacted is provided.