JPH05303110A - Manufacture of thin film transistor matrix - Google Patents

Abstract

PURPOSE:To prevent the breakage of a gate insulating film and characteristic deterioration due to the accumulation of static electricity in the manufacturing process of the TFT matrix. CONSTITUTION:The gate insulating film 5 is deposited on a substrate 1 where gate electrodes and gate bus lines 2 are formed so that one-end sides of the gate bus lines 2 are exposed, and then a conductive film 30 which constitutes source and drain electrodes and drain bus lines 3 is deposited on the substrate 1. When this conductive film 30 is pattern into the drain bus lines 3, etc., the film is left as electrodes which make mutual connections between the respective gate bus lines 2 and drain bus lines 3 nearby two adjacent end sides on the substrate 1. The mutual connection electrodes 20 are separated from the substrate in the final stage of the manufacture of the TFT matrix or a liquid crystal display device which uses it.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor matrix (TFT) which constitutes a so-called active matrix type liquid crystal display device.

[0002]

2. Description of the Related Art An attempt to put a color display device of a portable personal computer or a word processor or a wall-mounted color television into practical use by utilizing a liquid crystal and a TFT has been vigorously developed in various fields.

The TFT applied to the display device or the color television as described above is defective in one of several hundreds of millions to several millions of transistors arranged in a matrix on an insulating substrate such as a glass plate. Is not allowed either. One of the main reasons why these transistors are defective is the electrostatic breakdown of the insulating film. For example, in processes such as sputtering or CVD (Chemical Vapor Deposition) for depositing conductive films or insulating films, or for using plasma in the patterning process of wiring such as gate electrodes or bus lines,
Static electricity accumulates on the floating gate electrode and the source and drain electrodes, causing dielectric breakdown of the insulating film, especially the gate insulating film. Dielectric breakdown due to such static electricity also occurs due to various other causes. For example, in the lithographic process for forming the source and drain electrodes, static electricity is accumulated in the electrodes due to so-called peeling charging that occurs when the substrate coated with the resist is baked and then removed from the support. Also,
If a finger touches these bus lines in the manufacturing process of TFT or in the process of bonding a substrate with TFT formed to another substrate, or in the process of injecting liquid crystal into the gap between the bonded substrates, it will accumulate in the human body. The generated static electricity may flow to the bus line and cause dielectric breakdown of the gate insulating film. In addition, deterioration of TFT characteristics due to the accumulation of static electricity as described above,
In particular, the threshold voltage may fluctuate.

[0004]

In order to avoid the electrostatic breakdown as described above, as shown in FIG. 6, the end portions 2A of the gate bus line 2 and the drain bus line 3 respectively.
The electrodes 3 and 3A are interconnected by an electrode 20 formed of an aluminum thin film or the like formed in a region near the edge of the substrate 1. However, conventionally, the interconnect electrode 20 was formed after the TFT matrix was completed. For this reason, it was not effective in the electrostatic breakdown or TFT characteristic deterioration caused by the above-mentioned charging by plasma treatment or peeling charging in the previous process.

According to the present invention, when a conductive film forming at least source and drain electrodes is formed, the conductive film and the gate electrode are automatically short-circuited, and a TFT matrix or a liquid crystal display device including the TFT matrix is provided. It is an object of the present invention to provide a method in which a gate electrode can be separated from a source electrode and a drain electrode made of the conductive film after the above is completed.

[0006]

The above-mentioned object is to provide a plurality of gate electrodes arranged in a matrix on an insulating substrate, a plurality of gate bus lines each connecting the gate electrodes on the same row, and a plurality of gates. A gate insulating film covering the electrodes and the bus lines; a plurality of active regions each of which is composed of a semiconductor layer deposited on the gate insulating film and arranged in the matrix corresponding to the gate electrodes; A plurality of source and drain electrode pairs, which are a pair of electrodes formed in contact with one of the active regions and facing each other through a channel region defined in the active region, and each pair of source and drain electrodes are in the same column. In manufacturing an inverted stagger type thin film transistor matrix having a plurality of drain bus lines connecting the drain electrodes in contact with the active region above, one surface of the insulating substrate, After forming the gate electrode, the gate bus line, and a plurality of end portions extending from each gate bus line to a region near at least one end side of the insulating substrate, the end portions are selectively formed. The gate insulating film covering the gate electrode and the gate bus line is formed so as to be exposed, and an active region made of the semiconductor layer is formed on the gate insulating film. After forming an interconnection electrode selectively extending in at least one adjacent edge side region, a conductive film is formed on the surface of the insulating substrate including both edge side regions, and then the conductive film is formed. To form a plurality of source and drain electrode pairs, a plurality of the drain bus lines, and a plurality of end portions extending from the drain bus lines to the region near the other end side, and the subsequent steps. And a step of separating the gate bus line and the drain bus line from the interconnection electrode, or in the method of manufacturing the thin film transistor matrix according to the present invention, or This is achieved by a method of manufacturing a thin film transistor matrix according to the present invention, characterized in that the interconnection electrodes are molded together with lines.

[0007]

[Operation] In the inverted staggered TFT matrix, the end of the gate electrode formed on the insulating substrate is exposed, and the conductive film that constitutes the source and drain electrodes and the drain bus line is deposited on the entire surface of this substrate. To do. Therefore, the conductive film and the gate electrode are automatically short-circuited, which prevents electrostatic breakdown in the gate insulating film. When patterning this conductive film into source and drain electrodes, etc., it is left on the edge of the substrate as an electrode for interconnecting the gate bus line and the drain bus line. Therefore,
The short circuit between the gate electrode and the source and drain electrodes is maintained in the above patterning and subsequent steps. At the final stage, if the edge of the substrate on which the interconnection electrode is formed is cut and separated, the short circuit between the gate electrode and the source and drain electrodes is released, and the individual gate bus lines and the individual drain bus lines are released. The lines are electrically separated. Therefore, until the TFT is completed, or until the assembly of the liquid crystal display device composed of the TFT and the filling of the liquid crystal are completed, electrostatic breakdown and characteristic deterioration between the gate electrode and the source and drain electrodes are surely avoided.

[0008]

EXAMPLES In order to facilitate understanding of the present invention, the structure and manufacturing process of an inverted stagger type TFT matrix to which the present invention is applied will be described with reference to FIGS.

FIG. 1 is a plan view showing an arrangement of one TFT and gate bus lines 2 and drain bus lines 3 related thereto. That is, the TFT is the gate bus line 2
A drain electrode 3B extending from the drain bus line 3, and a source electrode 4 made of the same conductive film as the drain electrode 3B.

FIG. 2 shows how the XX cross section in FIG. 1 changes with the manufacturing process of the TFT. Same figure
As shown in the sectional view of (a), a gate electrode 2B made of a titanium film is formed on the surface of a substrate 1 made of, for example, transparent glass. The gate bus line 2 (not shown) is also formed of the same titanium film as the gate electrode 2B. Further, usually, an auxiliary electrode made of, for example, an aluminum film is previously formed between the gate bus line 2 and the substrate 1. Then, on the surface of the substrate 1, a gate insulating film 5 made of, for example, silicon nitride (SiN _x ) and having a thickness of about 0.4 μm is formed so as to cover the gate electrode 2B and the gate bus line 2.
Then, a semiconductor layer 6 made of non-doped amorphous silicon and a channel protection film 7 made of SiN _x and having a thickness of about 0.12 μm are sequentially deposited.

Then, as shown in FIG. 2 (b), the channel protection film 7 is patterned into a shape substantially corresponding to the gate electrode 2B, and then, as shown in FIG. 2 (c), a thickness of about 0.05 μm is obtained.
The conductive film 3 ₀ made of amorphous silicon film 3 ₁ and thickness of about 0.1 titanium film 3 ₂ μm of the n-type deposition. Then, the conductive film 3 _0, as shown in FIG. 2 (d), is patterned into the shape of the drain electrode 3B and the source electrode 4 and the drain bus line 3, further semiconductor layer 6, separated for each TFT active Pattern the regions. The drain bus line 3 extends perpendicularly to the paper surface. In one embodiment of the invention,
As described later, the conductive film 3 _0, patterning the interconnect electrode 20 (not shown) for connecting the drain bus line 3 and the gate bus line 2.

Then, as shown in FIG. 2 (e), the drain bus line 3 is extended, and connected to the auxiliary electrode 8 and the source electrode 4 made of, for example, an aluminum film, for example,
After forming the display electrode 9 made of ITO (Indium Tin Oxide) film, the TFT, the gate bus line 2 and the drain bus line 3 are covered. For example, a protective film 10 made of SiN _x and having a thickness of about 0.3 μm is formed to form a TFT. The matrix is complete.

In the present invention, the conductive film forming the drain electrode 3B and the drain bus line 3 is connected to the gate bus line 2 when it is deposited on the substrate 1. This will be described with reference to FIGS. 3 and 4.

As shown in FIG. 3 (a), a gate bus line 2 made of a titanium film is formed on a substrate 1 made of, for example, glass by a usual process. Although not shown in the figure, it goes without saying that the gate electrode 2B as shown in FIG. 1 extends from the gate bus line 2.
The end 2A of the gate bus line 2 extends to the region 1A near the edge of the substrate 1. After that, gate bus line 2
The gate insulating film 5 made of, for example, Si ₃ N ₄ to cover the substrate 1.
Deposit on top. The gate insulating film 5 depends on whether a mask is used during the deposition or etching is performed after the deposition.
It is formed so as to expose the end 2A of the gate bus line 2.

FIGS. 3B and 3C show the substrate 1 on which the gate bus line 2 and the gate insulating film 5 are formed as described above.
It is a partially enlarged sectional view of the former, the former being the gate bus line 2
The cross section is parallel to the stretching direction, and the latter is the cross section perpendicular to the stretching direction. As shown in FIG. 3B, the gate insulating film 5 is formed so as to expose the end 2A of the gate bus line 2 in the region 1A near the edge of the gate bus line 2 in the extending direction. It is necessary. However, the area 1A near the edge on the direction perpendicular to the extending direction of the gate bus line 2 is shown in FIG.
As shown in (c), it may be covered with the gate insulating film 5. Area 1A near the edge on the entire circumference of substrate 1
Alternatively, the gate insulating film 5 may not be formed. Further, it does not matter if the auxiliary electrode made of an aluminum film is formed between the gate bus line 2 and the substrate 1 as described above.

Then, as described with reference to FIG.
Semiconductor layer 6 made of non-doped amorphous silicon
Is deposited and a channel protection film 7 as shown in FIG. 2 is formed in a predetermined region on the semiconductor layer 6, and then an n-type amorphous silicon film 3 ₁ and a titanium film 3 ₂ are sequentially deposited on the substrate 1. Then, a titanium film 3 _2, by patterning the amorphous silicon film 3 ₁ and the semiconductor layer 6, as shown in FIG. 4 (a), to form a drain bus line 3 perpendicular to the gate bus line 2. Although not shown in the figure, the drain electrode 3B as shown in FIG.
Needless to say, the source electrode 4 is formed at the same time.

FIGS. 4 (b) and 4 (c) are respectively shown in FIG. 3 (b).
FIG. 3B is a partially enlarged cross-sectional view corresponding to (c), which shows a conductive film 3 ₀ composed of the amorphous silicon film 3 ₁ and the titanium film 3 _2.
The in patterning the drain bus line 3 or the like, leaving the conductive film 3 ₀ to the end side near region 1A of the substrate 1 as an interconnection electrode 20. The interconnection electrode 20 in FIG. 4 (b) extends as a strip layer perpendicular to the plane of the paper. In Figure 4 (c),
The interconnect electrode 20 is shown as an end 3A extending from the drain bus line 3.

In the present embodiment, because it is patterned and the conductive film 3 ₀ and the semiconductor layer 6 by using the same mask, FIG. 4 (b) and 4 (c), the drain bus line 3 and the interconnecting electrode The case where the semiconductor layer 6 remains under 20 is shown. In after the semiconductor layer 6 was patterned amorphous silicon film 3 ₁ so as to remain only in in the TFT area by depositing a conductive film 3 _0, by forming the drain bus line 3 or the like by patterning the interconnection electrode 20
Is in direct contact with the gate bus line 2, and the drain bus line 3 is in direct contact with the gate insulating film 5. When the gate insulating film 5 is not formed in the region 1A near the edge on the entire circumference of the substrate 1, the drain bus line 3 has a structure in direct contact with the substrate 1.

[0019] In the above embodiment uses the conductive film 3 ₀ that constitutes the drain bus line 3 such as the interconnect electrode 20, prior to formation of the gate electrode 2B and the gate bus line 2,
You may form the interconnection electrode 20 which consists of another conductive film.
Alternatively, after the formation such as a gate bus line 2, prior to deposition of the conductive film 3 ₀ may form an interconnect electrode 20 made of another conductive film. As shown in FIG. 2 (e), the aluminum film and the like which form the auxiliary electrode 8 provided on the drain bus line 3 are
It may be patterned so that it also remains on the interconnect electrode 20.

The conductive film 3 ₀ of providing the n-type amorphous silicon film 3 ₁ as lower layer has the following advantages. That is, the amorphous silicon film 3 ₁ low power plasma CVD
Since it can be deposited by the (chemical vapor deposition) method, the probability of electrostatic breakdown occurring in the gate insulating film 5 in this step is low. In the step of depositing a titanium film 3 ₂ by a sputtering method, the gate bus line 2 is connected amorphous silicon film 3 ₁ electrically, electrostatic breakdown of the gate insulating film 5 is completely prevented.

The interconnection electrodes 20 are formed in the adjacent regions 1A on the two adjacent sides of the substrate 1, and the gate bus lines 2 and the drain bus lines 3 are left open at their respective ends. For example, disconnection inspection of these bus lines is possible. When one end of each bus line is open, short circuit between gate bus line 2 or gate electrode 2B and drain bus line 3 or drain electrode 3B and individual TFT characteristic test are also possible. is there. That is, the gate bus line 2 each other and the drain bus line 3 cross and between the gate bus line 2 and the drain bus line 3 are connected by an interconnect electrode 20, the resistance of the amorphous silicon film 3 _1, prevents electrostatic breakdown This is because it is sufficiently low for the purpose of performing, but is sufficiently high for short-circuit test and characteristic test.

As shown in FIG. 5, the substrate 1 on which the TFT matrix obtained as described above is replaced with another substrate.
11 and facing each other with a predetermined gap, joining the peripheries of both substrates, filling the inside of the gap with liquid crystal, and electrically connecting each gate bus line 2 and drain bus line 3 and the interconnection electrode 20. The liquid crystal display device is completed by separating.
This separation is performed using a diamond cutter, etc.
The edge side region 1A may be cut from. Or board 1
Instead of disconnecting, the end 2A between the gate bus line 2 and the drain bus line 3 and the interconnection electrode 20 and
It may be a method of cutting only 3A. Alternatively, the interconnect electrode 20 may be formed by forming the interconnect electrode 20 at the outermost end of the substrate 1 and removing this portion in the end face polishing step of the substrate 1 to separate the interconnect electrode 20. Needless to say, when the auxiliary electrode 8 is formed from the drain bus line 3 to the interconnection electrode 20, this part of the auxiliary electrode 8 is removed.

[0023]

According to the present invention, the gate bus line is formed in the initial stage of the step of depositing the conductive film forming the source and drain electrodes and the drain bus line on the substrate on which the gate electrode and the gate bus line are formed. Is electrically connected to this conductive film, and after that, the TFT
Since the electrical connection between the gate bus line and the drain bus line is maintained until the final stage of the manufacturing process of the liquid crystal display device using the matrix or TFT matrix,
This prevents dielectric breakdown of the gate insulating film and deterioration of the TFT characteristics due to static electricity, and contributes to the improvement of the manufacturing yield of the TFT matrix or liquid crystal display device.

[Brief description of drawings]

[Fig.1] Schematic diagram of TFT

[Figure 2] TFT manufacturing process explanatory diagram

FIG. 3 is an explanatory diagram of an embodiment of the present invention (No. 1)

FIG. 4 is an explanatory view of an embodiment of the present invention (No. 2)

FIG. 5 is an explanatory view of another embodiment of the present invention.

FIG. 6 is an explanatory diagram of conventional problems

[Explanation of symbols]

1, 11 Substrate 3B Drain electrode 1A Near edge region 4 Source electrode 2 Gate bus line 5 Gate insulating film 2A, 3A Edge 6 Semiconductor layer 2B Gate electrode 7 Channel protective film 3 Drain bus line 8 Auxiliary electrode 3 ₀ Conductive film 9 Display electrode 3 ₁ Amorphous silicon film 10 Protective film 3 ₂ Titanium film 20 Interconnection electrode

Claims (5)

[Claims] 1. A plurality of gate electrodes arranged in a matrix on an insulating substrate, a plurality of gate bus lines each connecting the gate electrodes on the same row, and a gate covering the gate electrodes and the bus lines. An insulating film, a plurality of active regions each of which is composed of a semiconductor layer deposited on the gate insulating film and arranged in the matrix corresponding to the gate electrode, and each pair is one of the active regions. And a plurality of source and drain electrode pairs, which are a pair of electrodes formed to face each other through a channel region defined in the active region, and each of which contacts the active region on the same column. In the manufacturing of an inverted stagger type thin film transistor matrix having a plurality of drain bus lines connecting the drain electrodes, the gate electrode and the gate are provided on one surface of the insulating substrate. After forming a bus line and a plurality of end portions extending from each of the gate bus lines to a region near at least one end side of the insulating substrate, the end portions are selectively exposed. Forming the gate insulating film covering the gate electrode and the gate bus line;
A step of forming an active region made of the semiconductor layer on the gate insulating film, and an interconnect electrode selectively extending from within the edge side region to at least one other edge side region adjacent thereto And a conductive film is formed on the surface of the insulating substrate including the regions near the edges on both sides, and the conductive film is connected to the plurality of source and drain electrode pairs and the plurality of drain bus lines. Forming a plurality of ends extending from each of the drain bus lines to the region near the other edge, and separating the gate bus line and the drain bus line from the interconnection electrode A method of manufacturing a thin film transistor matrix, comprising: 2. The method of manufacturing a thin film transistor matrix according to claim 1, wherein the conductive film is formed into the interconnection electrode together with the drain bus line. 3. The gate bus line and the drain bus line and the interconnection electrode are separated by cutting and separating the regions near the edges on which the interconnection electrodes are formed from the central region of the insulating substrate. The method of manufacturing a thin film transistor matrix according to claim 1, wherein. 4. The conductive film is formed into the drain bus line and the interconnection electrode, and then comprises a second conductive film having a resistance lower than that of the conductive film and extends on at least each of the drain bus line lines. The method of claim 1, further comprising the step of forming an auxiliary electrode. 5. Before forming the gate electrode, the gate bus line, and a plurality of end portions extending from the gate bus line on one surface of the insulating substrate, at least in a region where the gate bus line is arranged. 2. The method of manufacturing a thin film transistor matrix according to claim 1, further comprising the step of forming an auxiliary electrode made of a third conductive film having a resistance lower than that of the gate bus line so as to extend selectively.