JPH05299358A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH05299358A
JPH05299358A JP9799092A JP9799092A JPH05299358A JP H05299358 A JPH05299358 A JP H05299358A JP 9799092 A JP9799092 A JP 9799092A JP 9799092 A JP9799092 A JP 9799092A JP H05299358 A JPH05299358 A JP H05299358A
Authority
JP
Japan
Prior art keywords
temperature
group
gas
silicon substrate
iii
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP9799092A
Other languages
Japanese (ja)
Inventor
Satoshi Okubo
聡 大久保
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP9799092A priority Critical patent/JPH05299358A/en
Priority to US08/047,202 priority patent/US5492860A/en
Publication of JPH05299358A publication Critical patent/JPH05299358A/en
Withdrawn legal-status Critical Current

Links

Landscapes

  • Crystals, And After-Treatments Of Crystals (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

PURPOSE:To provide the manufacturing method of semiconductor device capable of forming III-V compound semiconductor layer excellent both in the crystallinity and the surface homology on a silicon substrate. CONSTITUTION:The title manufacturing method is composed of an oxide film removing step (b) removing the oxide film on the surface of a silicon substrate at a first temperature, a low temperature deposited film formation step (c) forming the low temperature deposited film of III-V compound semiconductor on the silicon substrate at a second temperature lower than the first temperature as well as a single crystal film depositing step (d) depositing a single crystal film of III-V compound semiconductor on the low temperature deposited film during the temperature discending time and starting the leading-in step of the group V base gas when the temperature attains a specific higher level than the third temperature in the single crystal film depositing step.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明はシリコン基板上にIII −
V族化合物半導体結晶層を形成する半導体装置の製造方
法に関する。
BACKGROUND OF THE INVENTION The present invention relates to a silicon substrate on which III-
The present invention relates to a method for manufacturing a semiconductor device for forming a V-group compound semiconductor crystal layer.

【0002】[0002]

【従来の技術】近年、シリコン基板上にGaAs等のII
I −V族化合物半導体の結晶層を成長させる結晶成長技
術の研究開発が盛んに行われている。シリコン基板は製
造コストが低く大口径基板を容易に製造することがで
き、また強度的にも優れているので、このシリコン基板
上に化合物半導体層を形成した大口径の半導体基板を形
成することができれば、この半導体基板に化合物半導体
素子を大量に形成できるようになるからである。
2. Description of the Related Art Recently, II such as GaAs has been formed on a silicon substrate.
Research and development of a crystal growth technique for growing a crystal layer of an IV compound semiconductor have been actively conducted. Since a silicon substrate is low in manufacturing cost, a large-diameter substrate can be easily manufactured, and is also excellent in strength, it is possible to form a large-diameter semiconductor substrate on which a compound semiconductor layer is formed. If possible, a large amount of compound semiconductor elements can be formed on this semiconductor substrate.

【0003】シリコン基板上にIII −V族化合物半導体
結晶を成長させる従来の方法として、還元性ガスとV族
系ガスの雰囲気中でシリコン基板を熱処理した後に、低
温でIII −V族化合物半導体の低温成長層をまず形成
し、続いて、この低温成長層上にIII −V族化合物半導
体をエピタキシャル成長させる方法が知られている。し
かしながら、この従来の方法により(100)面から
[011]方向にオフセットしたシリコン基板上にIII
−V族化合物半導体層を成長させた場合、成長された化
合物半導体層をKOH処理により形成されるエッチピッ
トの長軸の方向がオフセットの方向に垂直になる。この
ようにオフセットしたシリコン基板上に形成された化合
物半導体層のエッチピットの長軸の方向が、オフセット
の方向に垂直になると、成長された化合物半導体層が表
面モホロジと結晶性に点で劣っていることが現象的に知
られている。このように、従来の方法では表面モホロジ
と結晶性の点で優れた化合物半導体層を形成することが
できない。
As a conventional method for growing a III-V group compound semiconductor crystal on a silicon substrate, after heat treating the silicon substrate in an atmosphere of a reducing gas and a V group-based gas, the III-V group compound semiconductor is grown at a low temperature. A method is known in which a low temperature growth layer is first formed, and then a III-V group compound semiconductor is epitaxially grown on the low temperature growth layer. However, by this conventional method, III is formed on a silicon substrate offset in the [011] direction from the (100) plane.
When the -V group compound semiconductor layer is grown, the major axis direction of the etch pits formed by KOH treatment of the grown compound semiconductor layer is perpendicular to the offset direction. When the long axis direction of the etch pits of the compound semiconductor layer formed on the offset silicon substrate is perpendicular to the offset direction, the grown compound semiconductor layer is inferior in surface morphology and crystallinity. It is known that there is a phenomenon. As described above, the conventional method cannot form a compound semiconductor layer excellent in surface morphology and crystallinity.

【0004】このような従来の方法の問題点を解決する
ものとして、特開平2−175690号公報に記載され
た方法がある。この方法は、還元性ガス雰囲気中でシリ
コン基板を熱処理した後に、低温で初めてV族系ガスを
導入してIII −V族化合物半導体の低温成長層をまず形
成し、続いて、この低温成長層上にIII −V族化合物半
導体をエピタキシャル成長させるものである。
As a method for solving the above problems of the conventional method, there is a method described in Japanese Patent Application Laid-Open No. 2-175690. In this method, after a silicon substrate is heat-treated in a reducing gas atmosphere, a group V gas is first introduced at a low temperature to first form a low temperature growth layer of a III-V compound semiconductor, and then this low temperature growth layer is formed. A III-V group compound semiconductor is epitaxially grown thereon.

【0005】この方法によれば従来の方法に比べて、成
長される化合物半導体層の結晶性が改善されている。
According to this method, the crystallinity of the grown compound semiconductor layer is improved as compared with the conventional method.

【0006】[0006]

【発明が解決しようとする課題】しかしながら、特開平
2−175690号公報に記載された方法では、成長さ
れる化合物半導体層の結晶性が改善されるものの、還元
性ガス雰囲気中でシリコン基板を熱処理した後、低温成
長層が形成される前にシリコン基板表面が汚染され、成
長される化合物半導体層の表面モホロジが悪化するとい
う問題があった。
However, according to the method described in Japanese Patent Laid-Open No. 2-175690, although the crystallinity of the grown compound semiconductor layer is improved, the silicon substrate is heat-treated in a reducing gas atmosphere. After that, there is a problem that the surface of the silicon substrate is contaminated before the low temperature growth layer is formed, and the surface morphology of the grown compound semiconductor layer is deteriorated.

【0007】本発明の目的は、シリコン基板上に結晶性
の点でも表面モホロジの点でも優れたIII −V族化合物
半導体層を形成することができる半導体装置の製造方法
を提供することにある。
An object of the present invention is to provide a method of manufacturing a semiconductor device capable of forming a group III-V compound semiconductor layer excellent in crystallinity and surface morphology on a silicon substrate.

【0008】[0008]

【課題を解決するための手段】上記目的は、シリコン基
板上にIII −V族化合物半導体結晶層を形成する半導体
装置の製造方法において、第1の温度で前記シリコン基
板の表面の酸化膜を除去する酸化膜除去工程と、前記第
1の温度より低い第2の温度で、III 族系ガスとV族系
ガスとを導入しながら、前記シリコン基板上にIII −V
族化合物半導体の低温成長膜を形成する低温成長膜形成
工程と、前記第2の温度より高く、前記第1の温度より
も低い第3の温度で、前記III 族系ガスと前記V族系ガ
スとを導入しながら、前記低温成長膜上にIII −V族化
合物半導体の単結晶膜を成長する単結晶膜成長工程とを
有し、前記酸化膜除去工程と前記低温成長膜形成工程間
の前記第1の温度から前記第2の温度への降温中であっ
て、前記第1の温度より低く前記第3の温度より高い所
定温度に達した時点から前記V族系ガスの導入を開始す
ることを特徴とする半導体装置の製造方法によって達成
される。
SUMMARY OF THE INVENTION The above object is to remove an oxide film on the surface of a silicon substrate at a first temperature in a method of manufacturing a semiconductor device in which a III-V compound semiconductor crystal layer is formed on a silicon substrate. And a group III-based gas and a group V-based gas at a second temperature lower than the first temperature while introducing a group III-V gas on the silicon substrate.
A low temperature growth film forming step of forming a low temperature growth film of a group compound semiconductor, and a third temperature higher than the second temperature and lower than the first temperature, the group III gas and the group V gas. And a single crystal film growing step of growing a single crystal film of a III-V group compound semiconductor on the low temperature growth film, the step of removing the oxide film and the low temperature growth film forming step. The introduction of the group V system gas is started at the time when a predetermined temperature lower than the first temperature and higher than the third temperature is reached during the temperature decrease from the first temperature to the second temperature. And a method for manufacturing a semiconductor device.

【0009】[0009]

【作用】本発明によれば、酸化膜除去工程と低温成長膜
形成工程間の第1の温度から第2の温度への降温中であ
って、第1の温度より低く単結晶膜成長工程の第3の温
度より高い所定温度に達した時点からV族系ガスの導入
を開始するようにしたので、低温成長層が形成される前
のシリコン基板表面の汚染が防止され、結晶性の点でも
表面モホロジの点でも優れたIII −V族化合物半導体層
を形成することができる。
According to the present invention, during the temperature decrease from the first temperature to the second temperature between the oxide film removing step and the low temperature growth film forming step, the temperature is lower than the first temperature and the single crystal film growth step is performed. Since the introduction of the group V gas is started when the temperature reaches a predetermined temperature higher than the third temperature, contamination of the surface of the silicon substrate before the low temperature growth layer is formed is prevented, and the crystallinity is also improved. It is possible to form a III-V compound semiconductor layer that is also excellent in terms of surface morphology.

【0010】[0010]

【実施例】本発明の一実施例による半導体装置の製造方
法を図1を用いて説明する。本実施例ではMOCVD装
置を用いてシリコン基板上にIII −V族化合物半導体と
してGaAs層を形成する。まず、シリコン基板を10
00℃まで昇温する。続いて、温度を1000℃に維持
したまま、水素ガスのような還元性ガス雰囲気中で約1
0分間熱処理する。これによりシリコン基板表面の酸化
膜を除去される(酸化膜除去工程)。このときにはIII
族系ガスであるTMG(トリメチルガリウム)もV族系
ガスであるAsH3 (アルシン)も導入されていない。
EXAMPLE A method of manufacturing a semiconductor device according to an example of the present invention will be described with reference to FIG. In this embodiment, a GaAs layer is formed as a III-V group compound semiconductor on a silicon substrate using a MOCVD device. First, the silicon substrate 10
Raise the temperature to 00 ° C. Then, while maintaining the temperature at 1000 ° C., the temperature is maintained at about 1 ° C. in a reducing gas atmosphere such as hydrogen gas.
Heat treatment for 0 minutes. As a result, the oxide film on the surface of the silicon substrate is removed (oxide film removing step). At this time III
Neither group gas TMG (trimethylgallium) nor group V gas AsH 3 (arsine) is introduced.

【0011】次に、温度を1000℃から、低温成長膜
形成工程の処理温度である450℃に向かって降温を開
始する。1000℃から温度が降温して単結晶成長工程
の処理温度である650℃に達するまでの間にV族系ガ
スであるAsH3 の導入を開始する。本実施例ではV族
系ガスであるAsH3 の導入開始時期を、酸化膜除去工
程の処理温度である1000℃から単結晶成長工程の処
理温度である650℃に達するまでの間にした点に特徴
がある。
Next, the temperature is lowered from 1000 ° C. to 450 ° C. which is the processing temperature in the low temperature growth film forming step. The introduction of AsH 3 , which is a group V gas, is started until the temperature drops from 1000 ° C. to 650 ° C. which is the processing temperature of the single crystal growth step. In the present embodiment, the introduction start time of AsH 3 which is a group V gas is set to be a point from when the processing temperature of the oxide film removing step is 1000 ° C. to when the processing temperature of the single crystal growing step is 650 ° C. There are features.

【0012】なお、V族系ガスであるAsH3 の導入開
始時期を、酸化膜除去工程直後ではなく800℃から単
結晶成長工程の処理温度である650℃に達するまでの
間にすることが望ましい。酸化膜除去工程直後からV族
系ガスであるAsH3 を導入を開始すると、成長される
GaAs層に異なる結晶方位を有する結晶が混在しやす
くなるのに対し、AsH3 の導入開始時期を800℃よ
りも低くなった時期にすると単一の結晶方位のGaAs
層を得ることができるからである。
It is desirable that the introduction of AsH 3 which is a group V gas be started not immediately after the oxide film removing step but from 800 ° C. to 650 ° C. which is the processing temperature of the single crystal growing step. .. If the introduction of AsH 3 which is a group V gas immediately after the oxide film removal step is started, crystals having different crystal orientations are likely to be mixed in the grown GaAs layer, whereas the introduction start time of AsH 3 is 800 ° C. GaAs with a single crystal orientation when it is lower than
This is because layers can be obtained.

【0013】更に、AsH3 を導入したまま降温し45
0℃に達すると、III 族系ガスであるTMGの導入も開
始し、シリコン基板上にGaAsの低温成長膜の形成を
開始する。温度を450℃に維持したまま、約1分間だ
けAsH3 とTMGを導入し、シリコン基板上に約20
0nm厚のGaAsの低温成長膜を形成する。次に、A
sH3 を導入したままでTMGの導入を停止した後、処
理温度を昇温する。温度が単結晶成長工程の処理温度で
ある650℃に達すると、III 族系ガスであるTMGの
導入を再開し、シリコン基板上に低温成長膜上にGaA
sの単結晶膜をエピタキシャル成長させる。温度を65
0℃に維持したまま、約40分間だけAsH3 とTMG
を導入し、シリコン基板上に約3μm厚のGaAs単結
晶膜を形成する。
Further, the temperature is lowered while introducing AsH 3 to 45
When the temperature reaches 0 ° C., introduction of TMG, which is a group III gas, is also started, and formation of a low temperature growth film of GaAs is started on the silicon substrate. While keeping the temperature at 450 ° C, AsH 3 and TMG were introduced for about 1 minute, and about 20 minutes were put on the silicon substrate.
A low-temperature grown film of 0 nm thick GaAs is formed. Next, A
After the introduction of TMG is stopped while introducing sH 3 , the treatment temperature is raised. When the temperature reaches 650 ° C., which is the processing temperature in the single crystal growth process, the introduction of TMG, which is a group III gas, is restarted, and GaA is formed on the low temperature growth film on the silicon substrate.
The single crystal film of s is epitaxially grown. Temperature 65
AsH 3 and TMG for about 40 minutes while maintaining at 0 ℃
Is introduced to form a GaAs single crystal film having a thickness of about 3 μm on the silicon substrate.

【0014】次に、TMGの導入を停止した後に処理温
度を降温し、ある程度温度が降下した後にAsH3 の導
入を停止して、シリコン基板上へのGaAs層の形成を
終了する。本実施例の半導体装置の製造方法によれば、
低温成長層が形成される前のシリコン基板表面の汚染が
防止され、結晶性の点でも表面モホロジの点でも優れた
GaAs層を形成することができた。このGaAs層表
面を光学顕微鏡で観察した結果を図2として示す。比較
のため、特開平2−175690号公報に記載された従
来の方法により形成したGaAs層表面を光学顕微鏡で
観察した結果を図3として示す。図2と図3を比較すれ
ば明らかなように、本実施例により形成されたGaAs
層の表面モホロジが従来の方法に比べて改善されている
ことがわかる。
Next, after stopping the introduction of TMG, the processing temperature is lowered, and after the temperature drops to some extent, the introduction of AsH 3 is stopped and the formation of the GaAs layer on the silicon substrate is completed. According to the method for manufacturing the semiconductor device of the present embodiment,
Contamination of the surface of the silicon substrate before formation of the low temperature growth layer was prevented, and a GaAs layer excellent in crystallinity and surface morphology could be formed. The result of observing the surface of the GaAs layer with an optical microscope is shown in FIG. For comparison, the result of observing the surface of the GaAs layer formed by the conventional method described in Japanese Patent Laid-Open No. 2-175690 with an optical microscope is shown in FIG. As is clear from comparison between FIG. 2 and FIG. 3, the GaAs formed according to the present embodiment.
It can be seen that the surface morphology of the layer is improved compared to conventional methods.

【0015】表面モホロジと結晶性の点が改善されてい
ることを確認するために、本実施例の方法により(10
0)面から[011]方向にオフセットしたシリコン基
板上にGaAs層を成長させ、このGaAs層をKOH
処理してエッチピットを形成した。その結果、GaAs
層に形成されたエッチピットの長軸の方向は、ほとんど
がシリコン基板のオフセットの方向と平行になり、表面
モホロジと結晶性の点が改善されていることが判明し
た。
In order to confirm that the surface morphology and crystallinity were improved, the method of this example was used (10
The GaAs layer is grown on a silicon substrate offset in the [011] direction from the (0) plane, and this GaAs layer is KOH.
Processed to form etch pits. As a result, GaAs
It was found that the major axis direction of the etch pit formed in the layer was almost parallel to the offset direction of the silicon substrate, and the surface morphology and crystallinity were improved.

【0016】本発明は上記実施例に限らず種々の変形が
可能である。例えば、上記実施例ではIII −V族化合物
半導体としてGaAsをシリコン基板上に形成したが、
本発明の方法を次に記載する他のIII −V族化合物半導
体の形成に適用してもよい。例えば、GaP、GaS
b、AlAs、AlP、AlSb、InAs、InP、
InSb等や、AlX Ga1-X As、AlX Ga
1-X P、AlX Ga1-X Sb、InX Ga1-X As、I
X Ga1-X P、InX Ga1- X Sb、InX Al1-X
As、InX Al1-X P、InX Al1-X Sb、GaA
X 1-X 、GaAsX Sb1-X 、GaPX Sb1-X
AlAsX 1-X 、AlAsX Sb1-X 、AlPX Sb
1-X 、InAsX 1-X 、InAsX Sb1-X 、InP
X Sb1-X 等の三元混晶や、Ga1-X AlX As1-Y
Y 、Ga1-X Al X 1-Y SbY 、Ga1-X AlX As
1-Y SbY 、In1-X AlX As1-Y Y、In1-X
X 1-Y SbY 、In1-X AlX As1-Y SbY 、I
1-X Ga X As1-Y Y 、In1-X GaX 1-Y Sb
Y 、In1-X GaX As1-Y SbY、(Ga1-X
X Y In1-Y P、(Ga1-X AlX Y In1-Y
s、(Ga1-X AlX Y In1-Y Sb、Al(As
1-X X Y Sb1-Y 、Ga(As 1-X X Y Sb
1-Y 、In(As1-X X Y Sb1-Y 等の四元混晶等
の形成にも本発明を適用できる。
The present invention is not limited to the above embodiment, but various modifications can be made.
It is possible. For example, in the above embodiment, a III-V group compound
Although GaAs was formed on a silicon substrate as a semiconductor,
Other III-V compound semiconductors described below for the method of the present invention
It may be applied to body formation. For example, GaP, GaS
b, AlAs, AlP, AlSb, InAs, InP,
InSb, etc., AlXGa1-XAs, AlXGa
1-XP, AlXGa1-XSb, InXGa1-XAs, I
nXGa1-XP, InXGa1- XSb, InXAl1-X
As, InXAl1-XP, InXAl1-XSb, GaA
sXP1-X, GaAsXSb1-X, GaPXSb1-X,
AlAsXP1-X, AlAsXSb1-X, AlPXSb
1-X, InAsXP1-X, InAsXSb1-X, InP
XSb1-XTernary mixed crystals such as Ga and Ga1-XAlXAs1-YP
Y, Ga1-XAl XP1-YSbY, Ga1-XAlXAs
1-YSbY, In1-XAlXAs1-YPY, In1-XA
lXP1-YSbY, In1-XAlXAs1-YSbY, I
n1-XGa XAs1-YPY, In1-XGaXP1-YSb
Y, In1-XGaXAs1-YSbY, (Ga1-XA
lX)YIn1-YP, (Ga1-XAlX)YIn1-YA
s, (Ga1-XAlX)YIn1-YSb, Al (As
1-XPX)YSb1-Y, Ga (As 1-XPX)YSb
1-Y, In (As1-XPX)YSb1-YQuaternary mixed crystal, etc.
The present invention can be applied to the formation of

【0017】また、上記実施例ではV族系ガスとしてハ
イドライド系ガスのAsH3 を用いたが、ハライド系ガ
スのAsCl3 を用いてもよい。P、SbのV族系ガス
として、ハイドライド系ガスのPH3 、SbH3 を用い
てもよいし、ハライド系ガスのPCl3 、SbCl3
SbCl4 を用いてもよい。さらに、V族系ガスとして
固体As、固体P、固体Sbの蒸気を用いてもよい。
In the above embodiment, the hydride gas AsH 3 is used as the group V gas, but a halide gas AsCl 3 may be used. As the V group gas of P and Sb, hydride gas PH 3 , SbH 3 may be used, or halide gas PCl 3 , SbCl 3 ,
SbCl 4 may be used. Furthermore, vapors of solid As, solid P, and solid Sb may be used as the group V gas.

【0018】[0018]

【発明の効果】以上の通り、本発明によれば、酸化膜除
去工程と低温成長膜形成工程間の第1の温度から第2の
温度への降温中であって、第1の温度より低く単結晶膜
成長工程の第3の温度より高い所定温度に達した時点か
らV族系ガスの導入を開始するようにしたので、低温成
長層が形成される前のシリコン基板表面の汚染が防止さ
れ、結晶性の点でも表面モホロジの点でも優れたIII −
V族化合物半導体層を形成することができる。
As described above, according to the present invention, the temperature is lowered from the first temperature to the second temperature between the oxide film removing step and the low temperature growth film forming step, and the temperature is lower than the first temperature. Since the introduction of the group V gas is started at the time when the temperature reaches a predetermined temperature higher than the third temperature in the single crystal film growth step, contamination of the surface of the silicon substrate before the low temperature growth layer is formed is prevented. , Excellent in crystallinity and surface morphology III-
A group V compound semiconductor layer can be formed.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例による半導体装置の製造方法
を示す図である。
FIG. 1 is a diagram showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

【図2】本発明の一実施例の方法により製造されたGa
As層表面を光学顕微鏡で観察した結果を示す図であ
る。
FIG. 2 is a Ga produced by a method according to an embodiment of the present invention.
It is a figure which shows the result of having observed the As layer surface with the optical microscope.

【図3】従来の方法により製造されたGaAs層表面を
光学顕微鏡で観察した結果を示す図である。
FIG. 3 is a diagram showing a result of observing the surface of a GaAs layer manufactured by a conventional method with an optical microscope.

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】 シリコン基板上にIII −V族化合物半導
体結晶層を形成する半導体装置の製造方法において、 第1の温度で前記シリコン基板の表面の酸化膜を除去す
る酸化膜除去工程と、 前記第1の温度より低い第2の温度で、III 族系ガスと
V族系ガスとを導入しながら、前記シリコン基板上にII
I −V族化合物半導体の低温成長膜を形成する低温成長
膜形成工程と、 前記第2の温度より高く、前記第1の温度よりも低い第
3の温度で、前記III族系ガスと前記V族系ガスとを導
入しながら、前記低温成長膜上にIII −V族化合物半導
体の単結晶膜を成長する単結晶膜成長工程とを有し、 前記酸化膜除去工程と前記低温成長膜形成工程間の前記
第1の温度から前記第2の温度への降温中であって、前
記第1の温度より低く前記第3の温度より高い所定温度
に達した時点から前記V族系ガスの導入を開始すること
を特徴とする半導体装置の製造方法。
1. A method of manufacturing a semiconductor device for forming a III-V group compound semiconductor crystal layer on a silicon substrate, comprising: an oxide film removing step of removing an oxide film on a surface of the silicon substrate at a first temperature; At a second temperature lower than the first temperature, while introducing a group III-based gas and a group V-based gas, II on the silicon substrate
A low temperature growth film forming step of forming a low temperature growth film of an I-V group compound semiconductor; and the group III gas and the V gas at a third temperature higher than the second temperature and lower than the first temperature. A single crystal film growing step of growing a single crystal film of a III-V group compound semiconductor on the low temperature growth film while introducing a group-based gas, the oxide film removing step and the low temperature growth film forming step During the temperature decrease from the first temperature to the second temperature during the period, the introduction of the group V system gas is started from the time when a predetermined temperature lower than the first temperature and higher than the third temperature is reached. A method for manufacturing a semiconductor device, which is started.
【請求項2】 請求項1記載の半導体装置の製造方法に
おいて、 前記V族系ガスの導入を開始する前記所定温度は、約8
00℃よりも低く前記第3の温度よりも高いことを特徴
とする半導体装置の製造方法。
2. The method of manufacturing a semiconductor device according to claim 1, wherein the predetermined temperature at which the introduction of the group V gas is started is about 8
A method of manufacturing a semiconductor device, wherein the temperature is lower than 00 ° C. and higher than the third temperature.
【請求項3】 請求項1又は2記載の半導体装置の製造
方法において、 前記V族系ガスはV族ハイドライド系ガスであることを
特徴とする半導体装置の製造方法。
3. The method of manufacturing a semiconductor device according to claim 1, wherein the group V system gas is a group V hydride system gas.
【請求項4】 請求項1又は2記載の半導体装置の製造
方法において、 前記V族系ガスはV族ハライド系ガスであることを特徴
とする半導体装置の製造方法。
4. The method of manufacturing a semiconductor device according to claim 1, wherein the group V gas is a group V halide gas.
【請求項5】 請求項1又は2記載の半導体装置の製造
方法において、 前記V族系ガスは固体V族の蒸気であることを特徴とす
る半導体装置の製造方法。
5. The method of manufacturing a semiconductor device according to claim 1, wherein the group V gas is solid group V vapor.
JP9799092A 1992-04-17 1992-04-17 Manufacture of semiconductor device Withdrawn JPH05299358A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP9799092A JPH05299358A (en) 1992-04-17 1992-04-17 Manufacture of semiconductor device
US08/047,202 US5492860A (en) 1992-04-17 1993-04-16 Method for growing compound semiconductor layers

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9799092A JPH05299358A (en) 1992-04-17 1992-04-17 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH05299358A true JPH05299358A (en) 1993-11-12

Family

ID=14207112

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9799092A Withdrawn JPH05299358A (en) 1992-04-17 1992-04-17 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH05299358A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10937647B2 (en) 2016-08-31 2021-03-02 Fujitsu Limited Semiconductor crystal substrate, infrared detector, and method for producing semiconductor crystal substrate

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10937647B2 (en) 2016-08-31 2021-03-02 Fujitsu Limited Semiconductor crystal substrate, infrared detector, and method for producing semiconductor crystal substrate
US11152210B2 (en) 2016-08-31 2021-10-19 Fujitsu Limited Semiconductor crystal substrate, infrared detector, and method for producing semiconductor crystal substrate

Similar Documents

Publication Publication Date Title
US7888244B2 (en) Threading-dislocation-free nanoheteroepitaxy of Ge on Si using self-directed touch-down of Ge through a thin SiO2 layer
JP2691721B2 (en) Semiconductor thin film manufacturing method
JP3093904B2 (en) Method for growing compound semiconductor crystal
JPH05291140A (en) Growth method of compound semiconductor thin film
US5834362A (en) Method of making a device having a heteroepitaxial substrate
US5492860A (en) Method for growing compound semiconductor layers
US8242003B1 (en) Defect removal in Ge grown on Si
JP2576766B2 (en) Semiconductor substrate manufacturing method
JP3369304B2 (en) Method for growing compound semiconductor crystal layer
JPH04233219A (en) Manufacture of products comprising semiconductor devices
US6188090B1 (en) Semiconductor device having a heteroepitaxial substrate
JPH05299358A (en) Manufacture of semiconductor device
JP3270945B2 (en) Heteroepitaxial growth method
JP3487393B2 (en) Method of forming heteroepitaxial semiconductor substrate, compound semiconductor device having such heteroepitaxial semiconductor substrate, and method of manufacturing the same
JPH08167576A (en) Forming method of heteroepitaxial semiconductor substrate, compound semiconductor device provided therewith, and manufacture thereof
JP3078927B2 (en) Method for growing compound semiconductor thin film
JPH0794409A (en) Formation of iii-v compound semiconductor thin film
JP2853226B2 (en) Semiconductor device and manufacturing method thereof
JPS5982744A (en) Manufacture of sos substrate
JP2790492B2 (en) Semiconductor thin film growth method
JPH01120011A (en) Inp semiconductor thin film
JP2503255B2 (en) Method for manufacturing compound semiconductor substrate
JPH09106949A (en) Compound semiconductor substrate and manufacture thereof
JPH04324626A (en) Manufacture of hetero epitaxial substrate
JPH047819A (en) Gaas thin film

Legal Events

Date Code Title Description
A300 Withdrawal of application because of no request for examination

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 19990706