JPH05294011A - Light emitting diode array chip - Google Patents

Abstract

PURPOSE:To easily perform dicing with a high precision and simplify inspection process of cut out array chips by making decision dicing line easy. CONSTITUTION:A plurality of light emitting elements 15 consisting of light emitting sections 13 and electrodes 14 are arranged at a constant pitch on an epitaxial wafer 10. At an outside of the utmost outside light emitting element 15a, a length discrimination pattern 20 is formed. The length discrimination pattern 20 is provided on both sides of end parts. The pattern 20 is preferably provided with at least three stepped parts such as a stepped part 21a for displaying the largest notched line, a stepped part 21b for designating an optimal dicing line 18, and a stepped part 21c for displaying a limit line. Thus, when upper and lower length discrimination patterns 20, 20 are to be connected, a predetermined dicing line 18 can be decided easily. The length of cut out array chip can be obtained easily by inspecting which part of the length discrimination pattern 20 is cut off.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a light emitting diode array chip used in an LED printer or the like.

[0002]

2. Description of the Related Art An electrophotographic printer uses a light emitting diode array in which a plurality of light emitting elements are formed on a substrate at a constant pitch as a light source. This light emitting diode array is usually 64 to 2 in one array chip.
56 light emitting diodes are integrated. In addition, considering the ease of manufacturing a long high-density array and the wavelength matching between the light emission output and the light emitter sensitivity, GaAs _0.6 P _0.4
/ GaAs is widely used as a light emitting diode material.

In a conventional light emitting diode, as shown in FIG. 1, a GaAsP epitaxial layer 11b is formed on the surface of a GaAs substrate 11a to form an epitaxial wafer 10, and a light emitting portion 1 is formed on the wafer 10 via an insulating layer 12.
3 and the electrode part 14 are formed. Light emitting part 13 and electrode part 1
One light emitting element 15 is constituted by 4, and the individual light emitting portions 13 are arranged on the epitaxial wafer 10 at a constant pitch.

In order to reduce the size and improve the performance of the light emitting diode array chip, the degree of integration of the light emitting elements 15 is rapidly increasing. Recently, an array chip in which the distance between adjacent light emitting elements 15 is set to about several μm has also been used. The light emitting diode array is installed in a device such as a printer in a state where a plurality of light emitting diode arrays are arranged in parallel.

In order to obtain a uniform distribution of the light emitting points, it is necessary that the light emitting portions are distributed at a constant pitch even when the end faces of a plurality of light emitting diode array chips are arranged to face each other. is there. That is, when two light emitting diode array chips are abutted against each other, the distance between the light emitting portion 13a of the light emitting element 15a located on the outermost side on one array chip and the outermost light emitting portion of the adjacent chip is on the array chip. The other light emitting portion 13b formed in
And 13a, and 13c and 13b. As a result, the outermost light emitting element 15a
The distance L from the array chip to the end surface 10a of the array chip is 10 μm.
It becomes an extremely small interval of m or less.

[0006]

The light emitting diode array in which the light emitting element 15 is built is cut out from an epitaxial wafer into array chips of a predetermined size by dicing. The dicing work is determined by using the end surface 12a of the insulating layer 12 as a guide as shown in FIG. That is, while observing the end of the insulating layer 12 with an optical microscope, the upper limit line 16 which is the upper limit of the length of the specification chip is estimated from the insulating layer end face 12a. Also, the maximum score line 17 cut at the position closest to the outermost light emitting portion 13a is estimated in consideration of a margin of about 5 μm. Then, the dicing line 18 is set between the upper limit line 16 and the maximum cut line 17. As described above, since the dicing line 18 is estimated by the operator's observation, the actual cutting accuracy is not stable and the array chip yield is reduced.

When inspecting the length of the cut array chip, an inspection accuracy of 1 μm or more is required. For example, a light emitting diode array chip in which 128 light emitting elements are arranged at a pitch of 63.5 μm has a length of about 8 mm. When attempting to measure the length of such a light emitting diode array chip with a commonly used optical microscope, the length is adjusted by adjusting the focus at a high magnification while sending the measurement stage so that the array chips are parallel without tilting. Is required. Therefore, the inspection work has been extremely complicated and time-consuming.

The present invention has been devised to solve such a problem, and by forming a length determining pattern at predetermined positions on both end surfaces of the light emitting diode array,
The purpose is to perform dicing and inspection simply and quickly.

[0009]

In order to achieve the object, a light emitting diode array of the present invention has a plurality of light emitting elements arranged at a constant pitch, and a length discriminating pattern indicating a chip length after dicing is outermost. It is characterized in that it is formed on both outer sides of the light emitting element.

[0010]

[Operation] In the present invention, as shown in FIGS.
Is formed. The length discriminating pattern 20 is used for accurately defining a dicing line during a dicing operation and also for measuring the length of an array chip cut out by dicing. Therefore, the setting of the dicing line based on the estimation based on the operator's observation and the complicated operation in the visual field of the microscope in the inspection process described in FIG. 2 are unnecessary.

The present invention will be specifically described below. As shown in FIG. 3, the light emitting diode array chip according to the present invention coats the epitaxial layer 11b with the insulating layer 12 except the peripheral portion 10b, and the light emitting portion 13 and the electrode portion 14 are formed.
Are arranged. The length determination pattern 20 is formed by making unevenness on the end of the insulating layer 12. Alternatively, the epitaxial layer 11b itself, which is not covered with the insulating layer 12, may be provided with similar unevenness to form a length determination pattern. Further, when the metal film for the electrode portion 14 is formed, the length determination pattern 20 can be simultaneously formed by using the metal film having a predetermined shape.

For example, the insulating layer 12 is etched in the process of forming the light emitting element 15. However, when the length determination pattern 20 is simultaneously formed during this etching, the number of steps does not increase. In this case, after forming the insulating layer 12 on the entire surface of the epitaxial wafer 10,
A predetermined pattern is formed at the same time as the window portion pattern for the light emitting portion 13 by photolithography, and the insulating layer 12 is partially etched with an etching solution such as hydrofluoric acid.

The length discriminating pattern 20 has a shape as simple as possible in consideration of the work load. However, it is preferable to determine the shape of the length determination pattern 20 so that at least three positions are displayed. For example, in FIG. 3, the limit of cutting into the array chip, the reference length of the chip, and the upper limit of the chip length are three key portions 21a to 21a, respectively.
21c. The key portion 21a is normally positioned outside the outermost electrode portion 14a with a margin of about 5 μm, and is used to determine a line corresponding to the maximum cut line 17 in FIG. The key portion 21b is used to determine the dicing line 18 for cutting out the array chip having an appropriate length. The key portion 21c corresponds to the limit line 16 of FIG.
Used to determine the line corresponding to.

As shown in FIG. 4, the length discriminating pattern 20 has step portions 22a to 2 in which the corner portions of the insulating layer 12 are removed in a T shape.
It can also be formed by 2c. Alternatively, as shown in FIG. 5, the linear portions 23a to 23c provided on the insulating layer 12 can be used as the length determination pattern 20. Linear part 2
3a to 23c are formed by etching the insulating layer 12 at the same time when the window pattern for the light emitting unit 13 is formed in the insulating layer 12. Alternatively, when the electrode portion 14 is formed, it is also formed by providing a metal film at the corner portion of the insulating layer 12 at the same time.

Key portions 21a to 21c and step portions 22a to 22c
And in any of the linear portions 23a to 23c, the insulating layer 1
2 or on the upper and lower sides of the epitaxial wafer 10 symmetrically. Therefore, for example, the corresponding upper and lower key portions 21
Dicing line 1 when connecting a, 21b and 21c
8 can be known clearly. Then, when the epitaxial wafer 10 is cut along the upper and lower key portions 21b as shown in FIG. 3C, an array chip having a size according to needs is cut out with high precision.

In the chip inspection, it is not necessary to measure the entire length of the chip as in the conventional case, and the array chip is formed based on the shape of the length discriminating pattern 20 remaining on the array chip after being cut out from the epitaxial wafer 10. Can know the length of. That is, the total length of the array chip can be determined by measuring the distance from the remaining length determination pattern 20 to the chip end surface and adding the value at the position indicated by the length determination pattern 20.

[0017]

EXAMPLE When the insulating layer 12 was formed on the epitaxial wafer 10 in which the GaAsP epitaxial layer 11b was formed on the surface of the GaAs substrate 11a by the conventional method, the length discriminating pattern 20 was formed at the same time. After forming a plurality of light emitting elements 15 composed of the light emitting portion 13 and the electrode portion 14 at a pitch of 63.5 μm, the epitaxial wafer 10 is formed into 8 pieces.
It was diced into an array chip of 000 μm × 0.95 mm.

The length of each array chip cut out and the presence or absence of a cut in the outermost light emitting element 15a were investigated. An array chip having a length of more than 8000 μm and an array chip having the outermost light emitting element 15a cut therein were determined as defective products, and the number of defective products produced when cutting out 10,000 array chips was counted. 3-5
Then, each (c) corresponds to an array chip having a length within a proper range, and each (d) has a length of 8000 μm.
Corresponding to defective products exceeding m, (e) corresponds to defective products in which the outermost light emitting element 15a is cut.

The dicing accuracy was evaluated by converting the number of defective products generated into a defective product generation rate (%). The experiment is shown in FIG.
The epitaxial wafer on which the length determination pattern 20 shown in FIG. 5 is formed and the conventional epitaxial wafer on which the length determination pattern is not formed are used four times. Table 1 shows the defective product occurrence rate in each experiment.

[0020]

[Table 1]

As is clear from Table 1, in the comparative example in which chips were cut out from the conventional epitaxial wafer, defective products were generated at a rate of 5% or more. On the other hand, when dicing an epitaxial wafer on which a length determination pattern is formed, no defective products are generated,
All could be used as a light emitting diode array chip having a desired shape. From this, it can be seen that the length discrimination pattern 20 improves the dicing accuracy.

[0022]

As described above, in the light emitting diode array chip of the present invention, since the length discriminating pattern is formed on the both end surfaces, the dicing line is set accurately, and the high precision of the chip is achieved. It becomes possible to cut out.
In addition, the length determination pattern is also used as an index when inspecting the length of the diced array chip, which makes the inspection operation simple and quick. As described above, according to the present invention, the light emitting diode array chip can be manufactured with high yield with excellent productivity.

[Brief description of drawings]

FIG. 1 is a plan view of a conventional light emitting diode array (a).
And sectional view (b)

FIG. 2 is a diagram illustrating a conventional dicing work.

FIG. 3 is a plan view (a) of a light emitting diode array used in an embodiment of the present invention, a perspective view (b) of a length determination pattern formed at an end of an insulating layer, and an array chip cut into an appropriate length. Plan view (c), defective chip (d) cut out with a length exceeding a specified value, and defective chip (e) cut out with the outermost light emitting element

FIG. 4 is a plan view (a) of another light emitting diode array which is also used in the embodiment of the present invention, a perspective view (b) of a length determination pattern formed at an end of an insulating layer, and cut out to an appropriate length. Plan view (c) of array chip, defective chip (d) cut out with a length exceeding a specified value, and defective chip (e) cut out with the outermost light emitting element

FIG. 5 is a plan view (a) of another light emitting diode array which is also used in the embodiment of the present invention, a perspective view (b) of a length determination pattern formed at the end of the insulating layer, and cut out to an appropriate length. Plan view (c) of array chip, defective chip (d) cut out with a length exceeding a specified value, and defective chip (e) cut out with the outermost light emitting element

[Explanation of symbols]

10 Epitaxial Wafer 11a GaAs Substrate 11b Epitaxial Layer 12 Insulating Layer 13 Light Emitting Section 13a Outermost Light Emitting Section 14 Electrode Section 14a Outermost Electrode Section 15 Light Emitting Element 15a Outermost Light Emitting Element 20 Length Discrimination Pattern 21a to 21c Key Section 22a to 22c Step Part 23a to 23c Linear part

Claims (1)

[Claims] 1. A light emitting diode array chip, wherein a plurality of light emitting elements are arranged at a constant pitch, and a length discrimination pattern indicating a chip length after dicing is formed at both outer ends of the outermost light emitting element. ..